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Diffstat (limited to 'nuttx/arch/arm/src/lm3s/lm3s_memorymap.h')
-rw-r--r--nuttx/arch/arm/src/lm3s/lm3s_memorymap.h78
1 files changed, 39 insertions, 39 deletions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
index df49a5f3e..df8fc0460 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
@@ -56,8 +56,8 @@
/* -0x21ffffff: Reserved */
# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
/* -0x3fffffff: Reserved */
-# define LM3S_FPERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
-# define LM3S_PERIPH_BASE 0x40020000 /* -0x41ffffff: Peripherals */
+# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
+ /* -0x41ffffff: Peripherals */
# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
/* -0xdfffffff: Reserved */
# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
@@ -77,45 +77,45 @@
#ifdef CONFIG_ARCH_CHIP_LM3S6918
/* FiRM Peripheral Base Addresses */
-# define LM3S_WDOG_BASE (LM3S_FPERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
- /* -0x03fff: Reserved */
-# define LM3S_GPIOA_BASE (LM3S_FPERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-# define LM3S_GPIOB_BASE (LM3S_FPERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-# define LM3S_GPIOC_BASE (LM3S_FPERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-# define LM3S_GPIOD_BASE (LM3S_FPERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
-# define LM3S_SSI0_BASE (LM3S_FPERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
-# define LM3S_SSI1_BASE (LM3S_FPERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
- /* -0x0bfff: Reserved */
-# define LM3S_UART0_BASE (LM3S_FPERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-# define LM3S_UART1_BASE (LM3S_FPERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
- /* -0x1ffff: Reserved */
+# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+ /* -0x03fff: Reserved */
+# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
+ /* -0x0bfff: Reserved */
+# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+ /* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
-# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x007ff: I2C Master 0 */
-# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x00800) /* -0x00fff: I2C Slave 0 */
-# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x01000) /* -0x017ff: I2C Master 1 */
-# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x01800) /* -0x01fff: I2C Slave 1 */
- /* -0x03fff: Reserved */
-# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port E */
-# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port F */
-# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port G */
-# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port H */
- /* -0x0ffff: Reserved */
-# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x10000) /* -0x10fff: Timer 0 */
-# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x11000) /* -0x11fff: Timer 1 */
-# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x12000) /* -0x12fff: Timer 2 */
-# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x13000) /* -0x13fff: Timer 3 */
- /* -0x17fff: Reserved */
-# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x18000) /* -0x18fff: ADC */
- /* -0x1bfff: Reserved */
-# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x1c000) /* -0x1cfff: Analog Comparators */
- /* -0x27fff: Reserved */
-# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: Ethernet Controller */
- /* -0xdcfff: Reserved */
-# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xdc000) /* -0xdcfff: Ethernet Controller */
-# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xdd000) /* -0xddfff: FLASH Control */
-# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xde000) /* -0xdefff: System Control */
- /* -0x1fdffff: Reserved */
+# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
+# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
+# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
+# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
+ /* -0x23fff: Reserved */
+# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
+# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
+# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
+# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
+ /* -0x2ffff: Reserved */
+# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
+# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
+# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
+# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
+ /* -0x37fff: Reserved */
+# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
+ /* -0x3bfff: Reserved */
+# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
+ /* -0x47fff: Reserved */
+# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
+ /* -0xfcfff: Reserved */
+# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
+# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
+# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
+ /* -0x1ffffff: Reserved */
#else
# error "Peripheral base addresses not specified for this LM3S chip"
#endif