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-rwxr-xr-xnuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c
index 83a3e7a67..ad542534a 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_clockconfig.c
@@ -104,7 +104,7 @@ void lpc17_clockconfig(void)
/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
-#if CONFIG_LPC17_PLL0
+#ifdef CONFIG_LPC17_PLL0
/* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
* a special "feed" sequence must be written to the PLL0FEED register in order
* for changes to the PLL0CFG register to take effect.