diff options
Diffstat (limited to 'nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h')
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h index 0c223335b..911bc6764 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h @@ -712,6 +712,29 @@ # define BASE_USART0_CLKSEL_IDIVD (15 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVD */ # define BASE_USART0_CLKSEL_IDIVE (16 << BASE_USART0_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ +/* Output stage 17 control register (BASE_UART1_CLK) */ +/* NOTE: Clocks 4-19 are identical */ + +#define BASE_UART1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_UART1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_UART1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_UART1_CLK_CLKSEL_MASK (31 << BASE_UART1_CLK_CLKSEL_SHIFT) +# define BASE_UART1_CLKSEL_32KHZOSC (0 << BASE_UART1_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_UART1_CLKSEL_IRC (1 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_UART1_CLKSEL_ENET_RXCLK (2 << BASE_UART1_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_UART1_CLKSEL_ENET_TXCLK (3 << BASE_UART1_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_UART1_CLKSEL_GPCLKIN (4 << BASE_UART1_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_UART1_CLKSEL_XTAL (6 << BASE_UART1_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_UART1_CLKSEL_PLL0AUDIO (8 << BASE_UART1_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_UART1_CLKSEL_PLL1 (9 << BASE_UART1_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_UART1_CLKSEL_IDIVA (12 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_UART1_CLKSEL_IDIVB (13 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_UART1_CLKSEL_IDIVC (14 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_UART1_CLKSEL_IDIVD (15 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_UART1_CLKSEL_IDIVE (16 << BASE_UART1_CLK_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 18 control register (BASE_USART2_CLK) */ /* NOTE: Clocks 4-19 are identical */ |