diff options
Diffstat (limited to 'nuttx/arch/arm/src/sam34/chip/sam3u_supc.h')
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_supc.h | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h index aea757717..07a52082a 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h @@ -1,6 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_supc.h - * Supply Controller (SUPC) definitions for the SAM3U and SAM4S + * Supply Controller (SUPC) definitions for the SAM3U, SAM3X, SAM3A, and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -82,7 +82,7 @@ #define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ #define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) -# if defined(CONFIG_ARCH_CHIP_SAM4S) +#if defined(CONFIG_ARCH_CHIP_SAM4S) # define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */ # define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */ # define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */ @@ -99,7 +99,7 @@ # define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */ # define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */ # define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */ -# elif defined(CONFIG_ARCH_CHIP_SAM3U) +#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ # define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ # define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ @@ -133,9 +133,11 @@ #define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ #define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) +#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) # define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */ -#elif defined(CONFIG_ARCH_CHIP_SAM3U) +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ #endif @@ -157,7 +159,7 @@ # define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */ # define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */ # define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */ -#elif defined(CONFIG_ARCH_CHIP_SAM3U) +#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ # define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) # define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ @@ -201,7 +203,7 @@ /* Supply Controller Status Register */ -#if defined(CONFIG_ARCH_CHIP_SAM3U) +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ #endif @@ -213,7 +215,7 @@ #define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ #define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ -#if defined(CONFIG_ARCH_CHIP_SAM3U) +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ #elif defined(CONFIG_ARCH_CHIP_SAM4S) # define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */ |