diff options
Diffstat (limited to 'nuttx/arch/arm/src/sama5/sam_periphclks.h')
| -rw-r--r-- | nuttx/arch/arm/src/sama5/sam_periphclks.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/sama5/sam_periphclks.h b/nuttx/arch/arm/src/sama5/sam_periphclks.h index 92d403b55..a89d0f95f 100644 --- a/nuttx/arch/arm/src/sama5/sam_periphclks.h +++ b/nuttx/arch/arm/src/sama5/sam_periphclks.h @@ -54,6 +54,8 @@ #define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) #define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) #define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) +#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0) +#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0) #define sam_dbgu_enableclk() sam_enableperiph0(SAM_PID_DBGU) #define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT) @@ -155,6 +157,56 @@ #define sam_fuse_disableclk() sam_disableperiph1(SAM_PID_FUSE) #define sam_mpddrc_disableclk() sam_disableperiph1(SAM_PID_MPDDRC) +#define sam_dbgu_isenabled() sam_isenabled0(SAM_PID_DBGU) +#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT) +#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT) +#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC) +#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA) +#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB) +#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC) +#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD) +#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE) +#define sam_smd_isenabled() sam_isenabled0(SAM_PID_SMD) +#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0) +#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1) +#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2) +#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3) +#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0) +#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1) +#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0) +#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1) +#define sam_twi2_isenabled() sam_isenabled0(SAM_PID_TWI2) +#define sam_hsmci0_isenabled() sam_isenabled0(SAM_PID_HSMCI0) +#define sam_hsmci1_isenabled() sam_isenabled0(SAM_PID_HSMCI1) +#define sam_hsmci2_isenabled() sam_isenabled0(SAM_PID_HSMCI2) +#define sam_spi0_isenabled() sam_isenabled0(SAM_PID_SPI0) +#define sam_spi1_isenabled() sam_isenabled0(SAM_PID_SPI1) +#define sam_tc0_isenabled() sam_isenabled0(SAM_PID_TC0) +#define sam_tc1_isenabled() sam_isenabled0(SAM_PID_TC1) +#define sam_pwm_isenabled() sam_isenabled0(SAM_PID_PWM) +#define sam_adc_isenabled() sam_isenabled0(SAM_PID_ADC) +#define sam_dmac0_isenabled() sam_isenabled0(SAM_PID_DMAC0) +#define sam_dmac1_isenabled() sam_isenabled0(SAM_PID_DMAC1) + +#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS) +#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS) +#define sam_gmac_isenabled() sam_isenabled1(SAM_PID_GMAC) +#define sam_emac_isenabled() sam_isenabled1(SAM_PID_EMAC) +#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC) +#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI) +#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0) +#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1) +#define sam_can0_isenabled() sam_isenabled1(SAM_PID_CAN0) +#define sam_can1_isenabled() sam_isenabled1(SAM_PID_CAN1) +#define sam_sha_isenabled() sam_isenabled1(SAM_PID_SHA) +#define sam_aes_isenabled() sam_isenabled1(SAM_PID_AES) +#define sam_tdes_isenabled() sam_isenabled1(SAM_PID_TDES) +#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG) +#define sam_arm_isenabled() sam_isenabled1(SAM_PID_ARM) +#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC) +#define sam_fuse_isenabled() sam_isenabled1(SAM_PID_FUSE) +#define sam_mpddrc_isenabled() sam_isenabled1(SAM_PID_MPDDRC) + /************************************************************************************ * Public Types ************************************************************************************/ |