diff options
Diffstat (limited to 'nuttx/arch/hc/include/m9s12/irq.h')
| -rwxr-xr-x | nuttx/arch/hc/include/m9s12/irq.h | 65 |
1 files changed, 63 insertions, 2 deletions
diff --git a/nuttx/arch/hc/include/m9s12/irq.h b/nuttx/arch/hc/include/m9s12/irq.h index 9df447b14..30bed2d4c 100755 --- a/nuttx/arch/hc/include/m9s12/irq.h +++ b/nuttx/arch/hc/include/m9s12/irq.h @@ -97,8 +97,69 @@ #define HCS12_IRQ_VEMACLC 36 /* ffa2: EMAC late collision */ #define HCS12_IRQ_VEMACEC 37 /* ffa0: EMAC excessive collision */ /* ff80-ff9f: Reserved */ -#define HCS12_IRQ_VILLEGAL 38 /* Any reserved vector */ -#define NR_IRQS 39 +#define HCS12_IRQ_NVECTORS 38 + +/* GPIO interrupts. The m9s12x supports several interrupts on PIM ports G, H, + * and J. We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * Port G: Pins 0-7 + * Port H: Pins 0-6 + * Port J: Pins 0-3 and 6-7 + */ + +#ifdef CONFIG_GPIO_IRQ + +/* To conserve space, interrupts must also be configured, port by port */ + +# define HCC12_IRQ_PGFIRST HCS12_IRQ_NVECTORS +# ifdef CONFIG_HCS12_PORTG_INTS +# define HCS12_IRQ_PGSET 0xff +# define HCS12_IRQ_PG0 (HCC12_IRQ_PGFIRST+0) +# define HCS12_IRQ_PG1 (HCC12_IRQ_PGFIRST+1) +# define HCS12_IRQ_PG2 (HCC12_IRQ_PGFIRST+2) +# define HCS12_IRQ_PG3 (HCC12_IRQ_PGFIRST+3) +# define HCS12_IRQ_PG4 (HCC12_IRQ_PGFIRST+4) +# define HCS12_IRQ_PG5 (HCC12_IRQ_PGFIRST+5) +# define HCS12_IRQ_PG6 (HCC12_IRQ_PGFIRST+6) +# define HCS12_IRQ_PG7 (HCC12_IRQ_PGFIRST+7) +# define HCC12_IRQ_PHFIRST (HCC12_IRQ_PGFIRST+8) +# else +# define HCC12_IRQ_PHFIRST HCC12_IRQ_PGFIRST +# endif + +# ifdef CONFIG_HCS12_PORTH_INTS +# define HCS12_IRQ_PHSET 0x7f +# define HCS12_IRQ_PH0 (HCC12_IRQ_PHFIRST+0) +# define HCS12_IRQ_PH1 (HCC12_IRQ_PHFIRST+1) +# define HCS12_IRQ_PH2 (HCC12_IRQ_PHFIRST+2) +# define HCS12_IRQ_PH3 (HCC12_IRQ_PHFIRST+3) +# define HCS12_IRQ_PH4 (HCC12_IRQ_PHFIRST+4) +# define HCS12_IRQ_PH5 (HCC12_IRQ_PHFIRST+5) +# define HCS12_IRQ_PH6 (HCC12_IRQ_PHFIRST+6) +# define HCC12_IRQ_PJFIRST (HCC12_IRQ_PHFIRST+7) +# else +# define HCC12_IRQ_PJFIRST HCC12_IRQ_PHFIRST +# endif + +# ifdef CONFIG_HCS12_PORTJ_INTS +# define HCS12_IRQ_PJSET 0xcf +# define HCS12_IRQ_PJ0 (HCC12_IRQ_PJFIRST+0) +# define HCS12_IRQ_PJ1 (HCC12_IRQ_PJFIRST+1) +# define HCS12_IRQ_PJ2 (HCC12_IRQ_PJFIRST+2) +# define HCS12_IRQ_PJ3 (HCC12_IRQ_PJFIRST+3) +# define HCS12_IRQ_PJ6 (HCC12_IRQ_PJFIRST+4) +# define HCS12_IRQ_PJ7 (HCC12_IRQ_PJFIRST+5) +# define HCS12_IRQ_NIRQS (HCC12_IRQ_PJFIRST+6) +# else +# define HCS12_IRQ_NIRQS HCC12_IRQ_PJFIRST +# endif +#else +# define HCS12_IRQ_NIRQS HCS12_IRQ_NVECTORS +#endif /* CONFIG_GPIO_IRQ */ + +#define HCS12_IRQ_VILLEGAL HCS12_IRQ_NIRQS /* Any reserved vector */ +#define NR_IRQS (HCS12_IRQ_NIRQS+1) /************************************************************************************ * Public Types |