diff options
Diffstat (limited to 'nuttx/arch/mips/src')
31 files changed, 1169 insertions, 1169 deletions
diff --git a/nuttx/arch/mips/src/common/up_allocateheap.c b/nuttx/arch/mips/src/common/up_allocateheap.c index 73933775d..f29b2685f 100644 --- a/nuttx/arch/mips/src/common/up_allocateheap.c +++ b/nuttx/arch/mips/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_allocateheap.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_arch.h b/nuttx/arch/mips/src/common/up_arch.h index 06e2eb7e4..9496016bc 100644 --- a/nuttx/arch/mips/src/common/up_arch.h +++ b/nuttx/arch/mips/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/mips/src/common/up_arch.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_createstack.c b/nuttx/arch/mips/src/common/up_createstack.c index 08c7231dd..d5c285e25 100644 --- a/nuttx/arch/mips/src/common/up_createstack.c +++ b/nuttx/arch/mips/src/common/up_createstack.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_createstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_interruptcontext.c b/nuttx/arch/mips/src/common/up_interruptcontext.c index 48f6abd93..526e86f87 100644 --- a/nuttx/arch/mips/src/common/up_interruptcontext.c +++ b/nuttx/arch/mips/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_interruptcontext.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_lowputs.c b/nuttx/arch/mips/src/common/up_lowputs.c index 9734b584e..314e239b1 100644 --- a/nuttx/arch/mips/src/common/up_lowputs.c +++ b/nuttx/arch/mips/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_lowputs.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_mdelay.c b/nuttx/arch/mips/src/common/up_mdelay.c index ff9b790e8..c55fb55bd 100644 --- a/nuttx/arch/mips/src/common/up_mdelay.c +++ b/nuttx/arch/mips/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_mdelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_modifyreg16.c b/nuttx/arch/mips/src/common/up_modifyreg16.c index ca72dec3e..2d6579947 100644 --- a/nuttx/arch/mips/src/common/up_modifyreg16.c +++ b/nuttx/arch/mips/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_modifyreg16.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_modifyreg32.c b/nuttx/arch/mips/src/common/up_modifyreg32.c index 59bb3a1d8..e5de12e5e 100644 --- a/nuttx/arch/mips/src/common/up_modifyreg32.c +++ b/nuttx/arch/mips/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_modifyreg32.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_modifyreg8.c b/nuttx/arch/mips/src/common/up_modifyreg8.c index b590458b3..53ed99f9c 100644 --- a/nuttx/arch/mips/src/common/up_modifyreg8.c +++ b/nuttx/arch/mips/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_modifyreg8.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_puts.c b/nuttx/arch/mips/src/common/up_puts.c index 9dd4bb5f4..2394343f9 100644 --- a/nuttx/arch/mips/src/common/up_puts.c +++ b/nuttx/arch/mips/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_puts.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_releasestack.c b/nuttx/arch/mips/src/common/up_releasestack.c index 0724f1a76..a54ea70cd 100644 --- a/nuttx/arch/mips/src/common/up_releasestack.c +++ b/nuttx/arch/mips/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_releasestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_udelay.c b/nuttx/arch/mips/src/common/up_udelay.c index b26f9d956..261348726 100644 --- a/nuttx/arch/mips/src/common/up_udelay.c +++ b/nuttx/arch/mips/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_udelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/common/up_usestack.c b/nuttx/arch/mips/src/common/up_usestack.c index fc27c1e76..e41608f67 100644 --- a/nuttx/arch/mips/src/common/up_usestack.c +++ b/nuttx/arch/mips/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_usestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/mips32-memorymap.h b/nuttx/arch/mips/src/mips32/mips32-memorymap.h index f4a0fed7d..21093c3b7 100644 --- a/nuttx/arch/mips/src/mips32/mips32-memorymap.h +++ b/nuttx/arch/mips/src/mips32/mips32-memorymap.h @@ -1,96 +1,96 @@ -/********************************************************************************************
- * arch/mips/src/mips32/mips32-memorymap.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H
-#define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-/********************************************************************************************
- * Pre-Processor Definitions
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-/* MIPS32 address space organization */
-
-#define USEG_BASE 0x00000000
-#define USEG_SIZE 0x80000000
-
-#define KSEG0_BASE 0x80000000
-#define KSEG0_SIZE 0x20000000
-
-#define KSEG1_BASE 0xa0000000
-#define KSEG1_SIZE 0x20000000
-
-#define KSEG2_BASE 0xc0000000
-#define KSEG2_SIZE 0x20000000
-
-#define KSEG3_BASE 0xe0000000
-#define KSEG3_SIZE 0x20000000
-
-#define DSEG_BASE 0xff200000
-#define DSEG_SIZE 0x00200000
-
-#ifndef __ASSEMBLY__
-
-/********************************************************************************************
- * Inline Functions
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Function Prototypes
- ********************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H */
+/******************************************************************************************** + * arch/mips/src/mips32/mips32-memorymap.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H +#define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/* MIPS32 address space organization */ + +#define USEG_BASE 0x00000000 +#define USEG_SIZE 0x80000000 + +#define KSEG0_BASE 0x80000000 +#define KSEG0_SIZE 0x20000000 + +#define KSEG1_BASE 0xa0000000 +#define KSEG1_SIZE 0x20000000 + +#define KSEG2_BASE 0xc0000000 +#define KSEG2_SIZE 0x20000000 + +#define KSEG3_BASE 0xe0000000 +#define KSEG3_SIZE 0x20000000 + +#define DSEG_BASE 0xff200000 +#define DSEG_SIZE 0x00200000 + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H */ diff --git a/nuttx/arch/mips/src/mips32/up_assert.c b/nuttx/arch/mips/src/mips32/up_assert.c index 977fe8287..881ec12cb 100644 --- a/nuttx/arch/mips/src/mips32/up_assert.c +++ b/nuttx/arch/mips/src/mips32/up_assert.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_assert.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/up_copystate.c b/nuttx/arch/mips/src/mips32/up_copystate.c index 1bafffd0e..798e82b04 100644 --- a/nuttx/arch/mips/src/mips32/up_copystate.c +++ b/nuttx/arch/mips/src/mips32/up_copystate.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/up_doirq.c b/nuttx/arch/mips/src/mips32/up_doirq.c index d4a3d93a0..29cdf9c60 100644 --- a/nuttx/arch/mips/src/mips32/up_doirq.c +++ b/nuttx/arch/mips/src/mips32/up_doirq.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_doirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/up_dumpstate.c b/nuttx/arch/mips/src/mips32/up_dumpstate.c index 369d98d7f..866c17b4f 100644 --- a/nuttx/arch/mips/src/mips32/up_dumpstate.c +++ b/nuttx/arch/mips/src/mips32/up_dumpstate.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_dumpstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/up_releasepending.c b/nuttx/arch/mips/src/mips32/up_releasepending.c index 978df0c7d..13918ca21 100644 --- a/nuttx/arch/mips/src/mips32/up_releasepending.c +++ b/nuttx/arch/mips/src/mips32/up_releasepending.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_releasepending.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/up_reprioritizertr.c b/nuttx/arch/mips/src/mips32/up_reprioritizertr.c index 24e33693c..66ce687e0 100644 --- a/nuttx/arch/mips/src/mips32/up_reprioritizertr.c +++ b/nuttx/arch/mips/src/mips32/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_reprioritizertr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/mips32/up_unblocktask.c b/nuttx/arch/mips/src/mips32/up_unblocktask.c index ba29cb736..5dafe90f0 100644 --- a/nuttx/arch/mips/src/mips32/up_unblocktask.c +++ b/nuttx/arch/mips/src/mips32/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_unblocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-che.h b/nuttx/arch/mips/src/pic32mx/pic32mx-che.h index c4b0913a2..f552486ba 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-che.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-che.h @@ -1,185 +1,185 @@ -/********************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-che.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/********************************************************************************************
- * Pre-Processor Definitions
- ********************************************************************************************/
-/* Register Offsets *************************************************************************/
-
-#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */
-#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */
-#define PIC32MX_CHE_CONSET_OFFSET 0x0008 /* Pre-fetch cache control set register */
-#define PIC32MX_CHE_CONINV_OFFSET 0x000c /* Pre-fetch cache control invert register */
-#define PIC32MX_CHE_ACC_OFFSET 0x0010 /* Pre-fetch cache access register */
-#define PIC32MX_CHE_ACCCLR_OFFSET 0x0014 /* Pre-fetch cache access clear register */
-#define PIC32MX_CHE_ACCSET_OFFSET 0x0018 /* Pre-fetch cache access set register */
-#define PIC32MX_CHE_ACCINV_OFFSET 0x001c /* Pre-fetch cache access invert register */
-#define PIC32MX_CHE_TAG_OFFSET 0x0020 /* Pre-fetch cache tag register */
-#define PIC32MX_CHE_TAGCLR_OFFSET 0x0024 /* Pre-fetch cache tag clear register */
-#define PIC32MX_CHE_TAGSET_OFFSET 0x0028 /* Pre-fetch cache tag set register */
-#define PIC32MX_CHE_TAGINV_OFFSET 0x002c /* Pre-fetch cache tag invert register */
-#define PIC32MX_CHE_MSK_OFFSET 0x0030 /* Pre-fetch cache tag mask register */
-#define PIC32MX_CHE_MSKCLR_OFFSET 0x0034 /* Pre-fetch cache tag mask clear register */
-#define PIC32MX_CHE_MSKSET_OFFSET 0x0038 /* Pre-fetch cache tag mask set register */
-#define PIC32MX_CHE_MSKINV_OFFSET 0x003c /* Pre-fetch cache tag mask invert register */
-#define PIC32MX_CHE_W0_OFFSET 0x0040 /* Cache word 0 register */
-#define PIC32MX_CHE_W1_OFFSET 0x0050 /* Cache word 1 register */
-#define PIC32MX_CHE_W2_OFFSET 0x0060 /* Cache word 2 register */
-#define PIC32MX_CHE_W3_OFFSET 0x0070 /* Cache word 3 register */
-#define PIC32MX_CHE_LRU_OFFSET 0x0080 /* Cache LRU register */
-#define PIC32MX_CHE_HIT_OFFSET 0x0090 /* Cache hit statistics register */
-#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */
-#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */
-
-/* Register Addresses ***********************************************************************/
-
-#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET)
-#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET)
-#define PIC32MX_CHE_CONSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONSET_OFFSET)
-#define PIC32MX_CHE_CONINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONINV_OFFSET)
-#define PIC32MX_CHE_ACC (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACC_OFFSET)
-#define PIC32MX_CHE_ACCCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCCLR_OFFSET)
-#define PIC32MX_CHE_ACCSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCSET_OFFSET)
-#define PIC32MX_CHE_ACCINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCINV_OFFSET)
-#define PIC32MX_CHE_TAG (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAG_OFFSET)
-#define PIC32MX_CHE_TAGCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGCLR_OFFSET)
-#define PIC32MX_CHE_TAGSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGSET_OFFSET)
-#define PIC32MX_CHE_TAGINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGINV_OFFSET)
-#define PIC32MX_CHE_MSK (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSK_OFFSET)
-#define PIC32MX_CHE_MSKCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKCLR_OFFSET)
-#define PIC32MX_CHE_MSKSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKSET_OFFSET)
-#define PIC32MX_CHE_MSKINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKINV_OFFSET)
-#define PIC32MX_CHE_W0 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W0_OFFSET)
-#define PIC32MX_CHE_W1 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W1_OFFSET)
-#define PIC32MX_CHE_W2 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W2_OFFSET)
-#define PIC32MX_CHE_W3 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W3_OFFSET)
-#define PIC32MX_CHE_LRU (PIC32MX_CHE_K1BASE+PIC32MX_CHE_LRU_OFFSET)
-#define PIC32MX_CHE_HIT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_HIT_OFFSET)
-#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET)
-#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET)
-
-/* Register Bit-Field Definitions ***********************************************************/
-
-/* Pre-fetch cache control register */
-
-
-#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: PFM access time (SYSCLK wait states) */
-#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT)
-# define CHE_CON_PFMWS(n) ((n) << CHE_CON_PFMWS_SHIFT) /* n wait states, n=0-7 */
-#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: Predictive pre-fetch cache enable */
-#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT)
-# define CHE_CON_PREFEN_DISABLE (0 << CHE_CON_PREFEN_SHIFT) /* Disable predictive pre-fetch cache */
-# define CHE_CON_PREFEN_CACHE (1 << CHE_CON_PREFEN_SHIFT) /* Enable for cacheable regions only */
-# define CHE_CON_PREFEN_NONCACHE (2 << CHE_CON_PREFEN_SHIFT) /* Enable for non-cacheable regions only */
-# define CHE_CON_PREFEN_ALL (3 << CHE_CON_PREFEN_SHIFT) /* Enable for both regions */
-#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: Data cache size (lines) */
-#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT)
-# define CHE_CON_DCSZ_DISABLE (0 << CHE_CON_DCSZ_SHIFT) /* Disable data caching */
-# define CHE_CON_DCSZ_1LINE (1 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 1 line */
-# define CHE_CON_DCSZ_2LINES (2 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 2 lines */
-# define CHE_CON_DCSZ_4LINES (3 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 4 lines */
-#define CHE_CON_CHECOH (1 << 16) /* Bit 16: Cache coherency setting */
-
-/* Pre-fetch cache access register */
-
-#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: Cache line index */
-#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT)
-#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: Cache access enable */
-
-/* Pre-fetch cache tag register */
-
-#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: Line type */
-#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: Line lock */
-#define CHE_TAG_LVALID (1 << 3) /* Bit 3: Line valid */
-#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: Line tag address */
-#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT)
-#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: Line tag address boot */
-
-/* Pre-fetch cache tag mask register */
-
-#define CHE_MSK_SHIFT (5) /* Bits 5-15: Line mask */
-#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT)
-
-/* Cache word 0-3 register -- 32-bit cache line data */
-
-/* Cache LRU register */
-
-#define CHE_LRU_MASK 0x01ffffff /* Bits 0-24 */
-
-/* Cache hit statistics register -- 32 bit counter value */
-
-/* Cache miss statistics register -- 32 bit counter value */
-
-/* Pre-fetch cache abort statistics register -- 32 bit counter value */
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/********************************************************************************************
- * Inline Functions
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Function Prototypes
- ********************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H */
+/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-che.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */ +#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */ +#define PIC32MX_CHE_CONSET_OFFSET 0x0008 /* Pre-fetch cache control set register */ +#define PIC32MX_CHE_CONINV_OFFSET 0x000c /* Pre-fetch cache control invert register */ +#define PIC32MX_CHE_ACC_OFFSET 0x0010 /* Pre-fetch cache access register */ +#define PIC32MX_CHE_ACCCLR_OFFSET 0x0014 /* Pre-fetch cache access clear register */ +#define PIC32MX_CHE_ACCSET_OFFSET 0x0018 /* Pre-fetch cache access set register */ +#define PIC32MX_CHE_ACCINV_OFFSET 0x001c /* Pre-fetch cache access invert register */ +#define PIC32MX_CHE_TAG_OFFSET 0x0020 /* Pre-fetch cache tag register */ +#define PIC32MX_CHE_TAGCLR_OFFSET 0x0024 /* Pre-fetch cache tag clear register */ +#define PIC32MX_CHE_TAGSET_OFFSET 0x0028 /* Pre-fetch cache tag set register */ +#define PIC32MX_CHE_TAGINV_OFFSET 0x002c /* Pre-fetch cache tag invert register */ +#define PIC32MX_CHE_MSK_OFFSET 0x0030 /* Pre-fetch cache tag mask register */ +#define PIC32MX_CHE_MSKCLR_OFFSET 0x0034 /* Pre-fetch cache tag mask clear register */ +#define PIC32MX_CHE_MSKSET_OFFSET 0x0038 /* Pre-fetch cache tag mask set register */ +#define PIC32MX_CHE_MSKINV_OFFSET 0x003c /* Pre-fetch cache tag mask invert register */ +#define PIC32MX_CHE_W0_OFFSET 0x0040 /* Cache word 0 register */ +#define PIC32MX_CHE_W1_OFFSET 0x0050 /* Cache word 1 register */ +#define PIC32MX_CHE_W2_OFFSET 0x0060 /* Cache word 2 register */ +#define PIC32MX_CHE_W3_OFFSET 0x0070 /* Cache word 3 register */ +#define PIC32MX_CHE_LRU_OFFSET 0x0080 /* Cache LRU register */ +#define PIC32MX_CHE_HIT_OFFSET 0x0090 /* Cache hit statistics register */ +#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */ +#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET) +#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET) +#define PIC32MX_CHE_CONSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONSET_OFFSET) +#define PIC32MX_CHE_CONINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONINV_OFFSET) +#define PIC32MX_CHE_ACC (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACC_OFFSET) +#define PIC32MX_CHE_ACCCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCCLR_OFFSET) +#define PIC32MX_CHE_ACCSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCSET_OFFSET) +#define PIC32MX_CHE_ACCINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCINV_OFFSET) +#define PIC32MX_CHE_TAG (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAG_OFFSET) +#define PIC32MX_CHE_TAGCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGCLR_OFFSET) +#define PIC32MX_CHE_TAGSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGSET_OFFSET) +#define PIC32MX_CHE_TAGINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGINV_OFFSET) +#define PIC32MX_CHE_MSK (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSK_OFFSET) +#define PIC32MX_CHE_MSKCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKCLR_OFFSET) +#define PIC32MX_CHE_MSKSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKSET_OFFSET) +#define PIC32MX_CHE_MSKINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKINV_OFFSET) +#define PIC32MX_CHE_W0 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W0_OFFSET) +#define PIC32MX_CHE_W1 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W1_OFFSET) +#define PIC32MX_CHE_W2 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W2_OFFSET) +#define PIC32MX_CHE_W3 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W3_OFFSET) +#define PIC32MX_CHE_LRU (PIC32MX_CHE_K1BASE+PIC32MX_CHE_LRU_OFFSET) +#define PIC32MX_CHE_HIT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_HIT_OFFSET) +#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET) +#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* Pre-fetch cache control register */ + + +#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: PFM access time (SYSCLK wait states) */ +#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT) +# define CHE_CON_PFMWS(n) ((n) << CHE_CON_PFMWS_SHIFT) /* n wait states, n=0-7 */ +#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: Predictive pre-fetch cache enable */ +#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT) +# define CHE_CON_PREFEN_DISABLE (0 << CHE_CON_PREFEN_SHIFT) /* Disable predictive pre-fetch cache */ +# define CHE_CON_PREFEN_CACHE (1 << CHE_CON_PREFEN_SHIFT) /* Enable for cacheable regions only */ +# define CHE_CON_PREFEN_NONCACHE (2 << CHE_CON_PREFEN_SHIFT) /* Enable for non-cacheable regions only */ +# define CHE_CON_PREFEN_ALL (3 << CHE_CON_PREFEN_SHIFT) /* Enable for both regions */ +#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: Data cache size (lines) */ +#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT) +# define CHE_CON_DCSZ_DISABLE (0 << CHE_CON_DCSZ_SHIFT) /* Disable data caching */ +# define CHE_CON_DCSZ_1LINE (1 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 1 line */ +# define CHE_CON_DCSZ_2LINES (2 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 2 lines */ +# define CHE_CON_DCSZ_4LINES (3 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 4 lines */ +#define CHE_CON_CHECOH (1 << 16) /* Bit 16: Cache coherency setting */ + +/* Pre-fetch cache access register */ + +#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: Cache line index */ +#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT) +#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: Cache access enable */ + +/* Pre-fetch cache tag register */ + +#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: Line type */ +#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: Line lock */ +#define CHE_TAG_LVALID (1 << 3) /* Bit 3: Line valid */ +#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: Line tag address */ +#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT) +#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: Line tag address boot */ + +/* Pre-fetch cache tag mask register */ + +#define CHE_MSK_SHIFT (5) /* Bits 5-15: Line mask */ +#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT) + +/* Cache word 0-3 register -- 32-bit cache line data */ + +/* Cache LRU register */ + +#define CHE_LRU_MASK 0x01ffffff /* Bits 0-24 */ + +/* Cache hit statistics register -- 32 bit counter value */ + +/* Cache miss statistics register -- 32 bit counter value */ + +/* Pre-fetch cache abort statistics register -- 32 bit counter value */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h b/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h index 9268089c0..de2c0216c 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-cm.h @@ -1,140 +1,140 @@ -/************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-cm.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "pic32mx-memorymap.h"
-
-#if CHIP_NCM > 0
-
-/************************************************************************************
- * Pre-Processor Definitions
- ************************************************************************************/
-/* Register Offsets *****************************************************************/
-
-#define PIC32MX_CM_CON_OFFSET 0x0000 /* Comparator control register */
-#define PIC32MX_CM_CONCLR_OFFSET 0x0004 /* Comparator control clear register */
-#define PIC32MX_CM_CONSET_OFFSET 0x0008 /* Comparator control set register */
-#define PIC32MX_CM_CONINV_OFFSET 0x000c /* Comparator control invert register */
-#define PIC32MX_CM_STAT_OFFSET 0x0060 /* Comparator status register */
-#define PIC32MX_CM_STATCLR_OFFSET 0x0064 /* Comparator status clear register */
-#define PIC32MX_CM_STATSET_OFFSET 0x0068 /* Comparator status set register */
-#define PIC32MX_CM_STATINV_OFFSET 0x006c /* Comparator status invert register */
-
-/* Register Addresses ***************************************************************/
-
-#define PIC32MX_CM1_CON (PIC32MX_CM1_K1BASE+PIC32MX_CM_CON_OFFSET)
-#define PIC32MX_CM1_CONCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONCLR_OFFSET)
-#define PIC32MX_CM1_CONSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONSET_OFFSET)
-#define PIC32MX_CM1_CONINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONINV_OFFSET)
-
-#if CHIP_NCM > 0
-# define PIC32MX_CM2_CON (PIC32MX_CM2_K1BASE+PIC32MX_CM_CON_OFFSET)
-# define PIC32MX_CM2_CONCLR (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONCLR_OFFSET)
-# define PIC32MX_CM2_CONSET (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONSET_OFFSET)
-# define PIC32MX_CM2_CONINV (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONINV_OFFSET)
-#endif
-
-#define PIC32MX_CM_STAT (PIC32MX_CM_K1BASE+PIC32MX_CM_STAT_OFFSET)
-#define PIC32MX_CM_STATCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATCLR_OFFSET)
-#define PIC32MX_CM_STATSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATSET_OFFSET)
-#define PIC32MX_CM_STATINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATINV_OFFSET)
-
-/* Register Bit-Field Definitions ***************************************************/
-
-/* Comparator control register */
-
-#define CM_CON_CCH_SHIFT (0) /* Bits 0-1: Comparator negative input select */
-#define CM_CON_CCH_MASK (3 << CM_CON_CCH_SHIFT)
-# define CM_CON_CCH_CXINM (0 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN- */
-# define CM_CON_CCH_CXINP (1 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN+ */
-# define CM_CON_CCH_CYINP (2 << CM_CON_CCH_SHIFT) /* Inverting input connected to CyIN+ */
-# define CM_CON_CCH_IVREF (3 << CM_CON_CCH_SHIFT) /* Inverting input connected to IVREF */
-#define CM_CON_CREF (1 << 4) /* Bit 4: Comparator positive input configure */
-#define CM_CON_EVPOL_SHIFT (6) /* Bits 6-7: Interrupt event polarity select */
-#define CM_CON_EVPOL_MASK (3 << CM_CON_EVPOL_SHIFT)
-# define CM_CON_EVPOL_DISABLED (0 << CM_CON_EVPOL_SHIFT) /* Interrupt disabled */
-# define CM_CON_EVPOL_RISING (1 << CM_CON_EVPOL_SHIFT) /* Interrupt on low-to-high transition */
-# define CM_CON_EVPOL_FALLING (2 << CM_CON_EVPOL_SHIFT) /* Interrupt on high-to-low transition */
-# define CM_CON_EVPOL_BOTH (3 << CM_CON_EVPOL_SHIFT) /* Interrupt on a both transitions */
-#define CM_CON_COUT (1 << 8) /* Bit 8: Comparator output */
-#define CM_CON_CPOL (1 << 13) /* Bit 13: Comparator output inversion */
-#define CM_CON_COE (1 << 14) /* Bit 14: Comparator output enable */
-#define CM_CON_ON (1 << 15) /* Bit 15: Comparator ON */
-
-/* Comparator status register */
-
-#define CM_STAT_C1OUT (1 << 0) /* Bit 0: Comparator 1 output */
-#define CM_STAT_C2OUT (1 << 1) /* Bit 1: Comparator 2 output */
-#define CM_STAT_SIDL (1 << 13) /* Bit 13: Stop in idle control */
-#define CM_STAT_FRZ (1 << 14) /* Bit 14: Freeze control */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* CHIP_NCM > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H */
+/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-cm.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "pic32mx-memorymap.h" + +#if CHIP_NCM > 0 + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_CM_CON_OFFSET 0x0000 /* Comparator control register */ +#define PIC32MX_CM_CONCLR_OFFSET 0x0004 /* Comparator control clear register */ +#define PIC32MX_CM_CONSET_OFFSET 0x0008 /* Comparator control set register */ +#define PIC32MX_CM_CONINV_OFFSET 0x000c /* Comparator control invert register */ +#define PIC32MX_CM_STAT_OFFSET 0x0060 /* Comparator status register */ +#define PIC32MX_CM_STATCLR_OFFSET 0x0064 /* Comparator status clear register */ +#define PIC32MX_CM_STATSET_OFFSET 0x0068 /* Comparator status set register */ +#define PIC32MX_CM_STATINV_OFFSET 0x006c /* Comparator status invert register */ + +/* Register Addresses ***************************************************************/ + +#define PIC32MX_CM1_CON (PIC32MX_CM1_K1BASE+PIC32MX_CM_CON_OFFSET) +#define PIC32MX_CM1_CONCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONCLR_OFFSET) +#define PIC32MX_CM1_CONSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONSET_OFFSET) +#define PIC32MX_CM1_CONINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONINV_OFFSET) + +#if CHIP_NCM > 0 +# define PIC32MX_CM2_CON (PIC32MX_CM2_K1BASE+PIC32MX_CM_CON_OFFSET) +# define PIC32MX_CM2_CONCLR (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONCLR_OFFSET) +# define PIC32MX_CM2_CONSET (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONSET_OFFSET) +# define PIC32MX_CM2_CONINV (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONINV_OFFSET) +#endif + +#define PIC32MX_CM_STAT (PIC32MX_CM_K1BASE+PIC32MX_CM_STAT_OFFSET) +#define PIC32MX_CM_STATCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATCLR_OFFSET) +#define PIC32MX_CM_STATSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATSET_OFFSET) +#define PIC32MX_CM_STATINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATINV_OFFSET) + +/* Register Bit-Field Definitions ***************************************************/ + +/* Comparator control register */ + +#define CM_CON_CCH_SHIFT (0) /* Bits 0-1: Comparator negative input select */ +#define CM_CON_CCH_MASK (3 << CM_CON_CCH_SHIFT) +# define CM_CON_CCH_CXINM (0 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN- */ +# define CM_CON_CCH_CXINP (1 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN+ */ +# define CM_CON_CCH_CYINP (2 << CM_CON_CCH_SHIFT) /* Inverting input connected to CyIN+ */ +# define CM_CON_CCH_IVREF (3 << CM_CON_CCH_SHIFT) /* Inverting input connected to IVREF */ +#define CM_CON_CREF (1 << 4) /* Bit 4: Comparator positive input configure */ +#define CM_CON_EVPOL_SHIFT (6) /* Bits 6-7: Interrupt event polarity select */ +#define CM_CON_EVPOL_MASK (3 << CM_CON_EVPOL_SHIFT) +# define CM_CON_EVPOL_DISABLED (0 << CM_CON_EVPOL_SHIFT) /* Interrupt disabled */ +# define CM_CON_EVPOL_RISING (1 << CM_CON_EVPOL_SHIFT) /* Interrupt on low-to-high transition */ +# define CM_CON_EVPOL_FALLING (2 << CM_CON_EVPOL_SHIFT) /* Interrupt on high-to-low transition */ +# define CM_CON_EVPOL_BOTH (3 << CM_CON_EVPOL_SHIFT) /* Interrupt on a both transitions */ +#define CM_CON_COUT (1 << 8) /* Bit 8: Comparator output */ +#define CM_CON_CPOL (1 << 13) /* Bit 13: Comparator output inversion */ +#define CM_CON_COE (1 << 14) /* Bit 14: Comparator output enable */ +#define CM_CON_ON (1 << 15) /* Bit 15: Comparator ON */ + +/* Comparator status register */ + +#define CM_STAT_C1OUT (1 << 0) /* Bit 0: Comparator 1 output */ +#define CM_STAT_C2OUT (1 << 1) /* Bit 1: Comparator 2 output */ +#define CM_STAT_SIDL (1 << 13) /* Bit 13: Stop in idle control */ +#define CM_STAT_FRZ (1 << 14) /* Bit 14: Freeze control */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CHIP_NCM > 0 */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h b/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h index 8c8b8d787..c23cbb9c3 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-ddp.h @@ -1,94 +1,94 @@ -/************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-ddp.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/************************************************************************************
- * Pre-Processor Definitions
- ************************************************************************************/
-/* Register Offsets *****************************************************************/
-
-#define PIC32MX_DDP_CON_OFFSET 0x0000 /* Control Register for the Diagnostic Module */
-
-/* Register Addresses ***************************************************************/
-
-#define PIC32MX_DDP_CON (PIC32MX_DDP_K1BASE+PIC32MX_DDP_CON_OFFSET)
-
-/* See also the ICESEL, DEBUG, and DEBUG0 in the DEVCFG0 register */
-
-/* Register Bit-Field Definitions ***************************************************/
-
-/* Control Register for the Diagnostic Module */
-
-#define DDP_CON_TROEN (1 << 2) /* Bit 2: Trace output enable */
-#define DDP_CON_JTAGEN (1 << 3) /* Bit 3: JTAG port enable */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H */
+/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-ddp.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_DDP_CON_OFFSET 0x0000 /* Control Register for the Diagnostic Module */ + +/* Register Addresses ***************************************************************/ + +#define PIC32MX_DDP_CON (PIC32MX_DDP_K1BASE+PIC32MX_DDP_CON_OFFSET) + +/* See also the ICESEL, DEBUG, and DEBUG0 in the DEVCFG0 register */ + +/* Register Bit-Field Definitions ***************************************************/ + +/* Control Register for the Diagnostic Module */ + +#define DDP_CON_TROEN (1 << 2) /* Bit 2: Trace output enable */ +#define DDP_CON_JTAGEN (1 << 3) /* Bit 3: JTAG port enable */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-flash.h b/nuttx/arch/mips/src/pic32mx/pic32mx-flash.h index 8ef9f3186..604f66c46 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-flash.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-flash.h @@ -1,130 +1,130 @@ - /********************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-flash.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H
-
- /********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
- /********************************************************************************************
- * Pre-Processor Definitions
- ********************************************************************************************/
-/* Register Offsets *************************************************************************/
-
-#define PIC32MX_FLASH_NVMCON_OFFSET 0x0000 /* Programming Control Register */
-#define PIC32MX_FLASH_NVMCONCLR_OFFSET 0x0004 /* Programming Control Clear Register */
-#define PIC32MX_FLASH_NVMCONSET_OFFSET 0x0008 /* Programming Control Set Register */
-#define PIC32MX_FLASH_NVMCONINV_OFFSET 0x000c /* Programming Control Invert Register */
-#define PIC32MX_FLASH_NVMKEY_OFFSET 0x0010 /* Programming Unlock Register */
-#define PIC32MX_FLASH_NVMADDR_OFFSET 0x0020 /* Flash Address Register */
-#define PIC32MX_FLASH_NVMADDRCLR_OFFSET 0x0024 /* Flash Address Clear Register */
-#define PIC32MX_FLASH_NVMADDRSET_OFFSET 0x0028 /* Flash Address Set Register */
-#define PIC32MX_FLASH_NVMADDRINV_OFFSET 0x002c /* Flash Address Invert Register */
-#define PIC32MX_FLASH_NVMDATA_OFFSET 0x0030 /* Flash Program Data Register */
-#define PIC32MX_FLASH_NVMSRCADDR_OFFSET 0x0040 /* Source Data Address Register */
-
-/* Register Addresses ***********************************************************************/
-
-#define PIC32MX_FLASH_NVMCON (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCON_OFFSET)
-#define PIC32MX_FLASH_NVMCONCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONCLR_OFFSET)
-#define PIC32MX_FLASH_NVMCONSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONSET_OFFSET)
-#define PIC32MX_FLASH_NVMCONINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONINV_OFFSET)
-#define PIC32MX_FLASH_NVMKEY (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMKEY_OFFSET)
-#define PIC32MX_FLASH_NVMADDRCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRCLR_OFFSET)
-#define PIC32MX_FLASH_NVMADDRSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRSET_OFFSET)
-#define PIC32MX_FLASH_NVMADDRINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRINV_OFFSET)
-#define PIC32MX_FLASH_NVMADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDR_OFFSET)
-#define PIC32MX_FLASH_NVMDATA (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMDATA_OFFSET)
-#define PIC32MX_FLASH_NVMSRCADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMSRCADDR_OFFSET)
-
-/* Register Bit-Field Definitions ***********************************************************/
-
-/* Programming Control Register */
-
-#define FLASH_NVMCON_NVMOP_SHIFT (0) /* Bits 0-3: NVM operation */
-#define FLASH_NVMCON_NVMOP_MASK (15 << FLASH_NVMCON_NVMOP_SHIFT)
-# define FLASH_NVMCON_NVMOP_NOP (0 << FLASH_NVMCON_NVMOP_SHIFT) /* No operation */
-# define FLASH_NVMCON_NVMOP_WDPROG (1 << FLASH_NVMCON_NVMOP_SHIFT) /* Word program operation */
-# define FLASH_NVMCON_NVMOP_ROWPROG (3 << FLASH_NVMCON_NVMOP_SHIFT) /* Row program operation */
-# define FLASH_NVMCON_NVMOP_PFMERASE (4 << FLASH_NVMCON_NVMOP_SHIFT) /* Page erase operation */
-# define FLASH_NVMCON_NVMOP_PFMERASE (5 << FLASH_NVMCON_NVMOP_SHIFT) /* PFM erase operationxx */
-#define FLASH_NVMCON_LVDSTAT (1 << 11) /* Bit nn: Low-voltage detect status */
-#define FLASH_NVMCON_LVDERR (1 << 12) /* Bit nn: Low-voltage detect error */
-#define FLASH_NVMCON_WRERR (1 << 13) /* Bit nn: Write error */
-#define FLASH_NVMCON_WREN (1 << 14) /* Bit nn: Write enable */
-#define FLASH_NVMCON_WR (1 << 15) /* Bit nn: Write control */
-
-/* Programming Unlock Register -- 32 Bits of data */
-
-/* Flash Address Register -- 32 Bits of data */
-
-/* Flash Program Data Register -- 32 Bits of data */
-
-/* Source Data Address Register -- 32 Bits of data */
-
- /********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
- /********************************************************************************************
- * Inline Functions
- ********************************************************************************************/
-
- /********************************************************************************************
- * Public Function Prototypes
- ********************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H */
+ /******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-flash.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H + + /******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + + /******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_FLASH_NVMCON_OFFSET 0x0000 /* Programming Control Register */ +#define PIC32MX_FLASH_NVMCONCLR_OFFSET 0x0004 /* Programming Control Clear Register */ +#define PIC32MX_FLASH_NVMCONSET_OFFSET 0x0008 /* Programming Control Set Register */ +#define PIC32MX_FLASH_NVMCONINV_OFFSET 0x000c /* Programming Control Invert Register */ +#define PIC32MX_FLASH_NVMKEY_OFFSET 0x0010 /* Programming Unlock Register */ +#define PIC32MX_FLASH_NVMADDR_OFFSET 0x0020 /* Flash Address Register */ +#define PIC32MX_FLASH_NVMADDRCLR_OFFSET 0x0024 /* Flash Address Clear Register */ +#define PIC32MX_FLASH_NVMADDRSET_OFFSET 0x0028 /* Flash Address Set Register */ +#define PIC32MX_FLASH_NVMADDRINV_OFFSET 0x002c /* Flash Address Invert Register */ +#define PIC32MX_FLASH_NVMDATA_OFFSET 0x0030 /* Flash Program Data Register */ +#define PIC32MX_FLASH_NVMSRCADDR_OFFSET 0x0040 /* Source Data Address Register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_FLASH_NVMCON (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCON_OFFSET) +#define PIC32MX_FLASH_NVMCONCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONCLR_OFFSET) +#define PIC32MX_FLASH_NVMCONSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONSET_OFFSET) +#define PIC32MX_FLASH_NVMCONINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONINV_OFFSET) +#define PIC32MX_FLASH_NVMKEY (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMKEY_OFFSET) +#define PIC32MX_FLASH_NVMADDRCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRCLR_OFFSET) +#define PIC32MX_FLASH_NVMADDRSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRSET_OFFSET) +#define PIC32MX_FLASH_NVMADDRINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRINV_OFFSET) +#define PIC32MX_FLASH_NVMADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDR_OFFSET) +#define PIC32MX_FLASH_NVMDATA (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMDATA_OFFSET) +#define PIC32MX_FLASH_NVMSRCADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMSRCADDR_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* Programming Control Register */ + +#define FLASH_NVMCON_NVMOP_SHIFT (0) /* Bits 0-3: NVM operation */ +#define FLASH_NVMCON_NVMOP_MASK (15 << FLASH_NVMCON_NVMOP_SHIFT) +# define FLASH_NVMCON_NVMOP_NOP (0 << FLASH_NVMCON_NVMOP_SHIFT) /* No operation */ +# define FLASH_NVMCON_NVMOP_WDPROG (1 << FLASH_NVMCON_NVMOP_SHIFT) /* Word program operation */ +# define FLASH_NVMCON_NVMOP_ROWPROG (3 << FLASH_NVMCON_NVMOP_SHIFT) /* Row program operation */ +# define FLASH_NVMCON_NVMOP_PFMERASE (4 << FLASH_NVMCON_NVMOP_SHIFT) /* Page erase operation */ +# define FLASH_NVMCON_NVMOP_PFMERASE (5 << FLASH_NVMCON_NVMOP_SHIFT) /* PFM erase operationxx */ +#define FLASH_NVMCON_LVDSTAT (1 << 11) /* Bit nn: Low-voltage detect status */ +#define FLASH_NVMCON_LVDERR (1 << 12) /* Bit nn: Low-voltage detect error */ +#define FLASH_NVMCON_WRERR (1 << 13) /* Bit nn: Write error */ +#define FLASH_NVMCON_WREN (1 << 14) /* Bit nn: Write enable */ +#define FLASH_NVMCON_WR (1 << 15) /* Bit nn: Write control */ + +/* Programming Unlock Register -- 32 Bits of data */ + +/* Flash Address Register -- 32 Bits of data */ + +/* Flash Program Data Register -- 32 Bits of data */ + +/* Source Data Address Register -- 32 Bits of data */ + + /******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + + /******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + + /******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-osc.h b/nuttx/arch/mips/src/pic32mx/pic32mx-osc.h index 9142b19a2..69c00329d 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-osc.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-osc.h @@ -1,165 +1,165 @@ -/****************************************************************************
- * arch/mips/src/pic32mx/pic32mx-osc.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
-/* Register Offsets *********************************************************/
-
-#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */
-#define PIC32MX_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */
-
-/* Register Addresses *******************************************************/
-
-#define PIC32MX_OSCCON (PIC32MX_OSC_K1BASE+PIC32MX_OSCCON_OFFSET)
-#define PIC32MX_OSCTUN (PIC32MX_OSC_K1BASE+PIC32MX_OSCTUN_OFFSET)
-
-/* Register Bit-Field Definitions *******************************************/
-
-/* Oscillator control register offset */
-
-#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */
-#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */
-#define OSCCON_UFRCEN (1 << 2) /* Bit 2: USB FRC clock enable */
-#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */
-#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */
-#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */
-#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */
-#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */
-#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */
-#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT)
-# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* FRC oscillator */
-# define OSCCON_NOSC_FRCPLL (1 << OSCCON_NOSC_SHIFT) /* FRC w/PLL postscaler */
-# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator */
-# define OSCCON_NOSC_POSCPLL (3 << OSCCON_NOSC_SHIFT) /* Primary oscillator with PLL */
-# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */
-# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */
-# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */
-# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */
-#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */
-#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT)
-# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */
-# define OSCCON_COSC_FRCPLL (1 << OSCCON_COSC_SHIFT) /* FRC w/PLL postscaler */
-# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator */
-# define OSCCON_COSC_POSCPLL (3 << OSCCON_COSC_SHIFT) /* Primary oscillator with PLL */
-# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */
-# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */
-# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */
-# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */
-#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */
-#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL16 (1 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL17 (2 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL18 (3 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL19 (4 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL20 (5 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL21 (6 << OSCCON_PLLMULT_SHIFT)
-# define OSCCON_PLLMULT_MUL24 (7 << OSCCON_PLLMULT_SHIFT)
-#define OSCCON_PBDIV_SHIFT (19) /* Bits 19-20: PBVLK divisor */
-#define OSCCON_PBDIV_SMASK (3 << OSCCON_PBDIV_SHIFT)
-# define OSCCON_PBDIV_DIV1 (0 << OSCCON_PBDIV_SHIFT)
-# define OSCCON_PBDIV_DIV2 (1 << OSCCON_PBDIV_SHIFT)
-# define OSCCON_PBDIV_DIV4 (2 << OSCCON_PBDIV_SHIFT)
-# define OSCCON_PBDIV_DIV8 (3 << OSCCON_PBDIV_SHIFT)
-#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */
-#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */
-#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT)
-# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT)
-#define OSCCON_PLL0DIV_SHIFT (27) /* Bits 27-29: Output divider for PLL */
-#define OSCCON_PLL0DIV_MASK (7 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV1 (0 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV2 (1 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV4 (2 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV8 (3 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV16 (4 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV32 (5 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV64 (6 << OSCCON_PLL0DIV_SHIFT)
-# define OSCCON_PLL0DIV_DIV256 (7 << OSCCON_PLL0DIV_SHIFT)
-
-/* FRC tuning register offset (6-bit, signed twos complement) */
-
-#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */
-#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT)
-# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT)
-# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT)
-# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT)
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H */
+/**************************************************************************** + * arch/mips/src/pic32mx/pic32mx-osc.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Register Offsets *********************************************************/ + +#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */ +#define PIC32MX_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */ + +/* Register Addresses *******************************************************/ + +#define PIC32MX_OSCCON (PIC32MX_OSC_K1BASE+PIC32MX_OSCCON_OFFSET) +#define PIC32MX_OSCTUN (PIC32MX_OSC_K1BASE+PIC32MX_OSCTUN_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Oscillator control register offset */ + +#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */ +#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */ +#define OSCCON_UFRCEN (1 << 2) /* Bit 2: USB FRC clock enable */ +#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */ +#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */ +#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */ +#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */ +#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */ +#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */ +#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT) +# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* FRC oscillator */ +# define OSCCON_NOSC_FRCPLL (1 << OSCCON_NOSC_SHIFT) /* FRC w/PLL postscaler */ +# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator */ +# define OSCCON_NOSC_POSCPLL (3 << OSCCON_NOSC_SHIFT) /* Primary oscillator with PLL */ +# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */ +# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */ +# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */ +# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */ +#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */ +#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT) +# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */ +# define OSCCON_COSC_FRCPLL (1 << OSCCON_COSC_SHIFT) /* FRC w/PLL postscaler */ +# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator */ +# define OSCCON_COSC_POSCPLL (3 << OSCCON_COSC_SHIFT) /* Primary oscillator with PLL */ +# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */ +# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */ +# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */ +# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */ +#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */ +#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL16 (1 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL17 (2 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL18 (3 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL19 (4 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL20 (5 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL21 (6 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL24 (7 << OSCCON_PLLMULT_SHIFT) +#define OSCCON_PBDIV_SHIFT (19) /* Bits 19-20: PBVLK divisor */ +#define OSCCON_PBDIV_SMASK (3 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV1 (0 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV2 (1 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV4 (2 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV8 (3 << OSCCON_PBDIV_SHIFT) +#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */ +#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */ +#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT) +#define OSCCON_PLL0DIV_SHIFT (27) /* Bits 27-29: Output divider for PLL */ +#define OSCCON_PLL0DIV_MASK (7 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV1 (0 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV2 (1 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV4 (2 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV8 (3 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV16 (4 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV32 (5 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV64 (6 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV256 (7 << OSCCON_PLL0DIV_SHIFT) + +/* FRC tuning register offset (6-bit, signed twos complement) */ + +#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */ +#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT) +# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT) +# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT) +# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h b/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h index d3ed74627..745c56a3d 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h @@ -2,7 +2,7 @@ * arch/mips/src/pic32mx/pic32mx-pmp.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h b/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h index 5e1721796..22fc62e4e 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-reset.h @@ -1,117 +1,117 @@ -/************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-reset.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/************************************************************************************
- * Pre-Processor Definitions
- ************************************************************************************/
-/* Register Offsets *****************************************************************/
-
-#define PIC32MX_RESET_RCON_OFFSET 0x0000 /* Reset control register */
-#define PIC32MX_RESET_RCONCLR_OFFSET 0x0004 /* RCON clear register */
-#define PIC32MX_RESET_RCONSET_OFFSET 0x0008 /* RCON set register */
-#define PIC32MX_RESET_RCONINV_OFFSET 0x000c /* RCON invert register */
-#define PIC32MX_RESET_RSWRST_OFFSET 0x0010 /* Software reset register */
-#define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */
-#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */
-#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */
-
-/* Register Addresses ***************************************************************/
-
-#define PIC32MX_RESET_RCON (PIC32MX_RESET_K1BASE+PIC32MX_RCON_OFFSET)
-#define PIC32MX_RESET_RCONCLR (PIC32MX_RESET_K1BASE+PIC32MX_RCONCLR_OFFSET)
-#define PIC32MX_RESET_RCONSET (PIC32MX_RESET_K1BASE+PIC32MX_RCONSET_OFFSET)
-#define PIC32MX_RESET_RCONINV (PIC32MX_RESET_K1BASE+PIC32MX_RCONINV_OFFSET)
-#define PIC32MX_RESET_RSWRST (PIC32MX_RESET_K1BASE+PIC32MX_RSWRST_OFFSET)
-#define PIC32MX_RESET_RSWRSTCLR (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTCLR_OFFSET)
-#define PIC32MX_RESET_RSWRSTSET (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTSET_OFFSET)
-#define PIC32MX_RESET_RSWRSTINV (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTINV_OFFSET)
-
-/* Register Bit-Field Definitions ***************************************************/
-
-/* Reset control register */
-
-#define RESET_RCON_POR (1 << 0) /* Bit 0: Power on reset */
-#define RESET_RCON_BOR (1 << 1) /* Bit 1: Brown out reset */
-#define RESET_RCON_IDLE (1 << 2) /* Bit 2: Wake from idle */
-#define RESET_RCON_SLEEP (1 << 3) /* Bit 3: Wake from sleep */
-#define RESET_RCON_WDTO (1 << 4) /* Bit 4: Watchdog timer time-out */
-#define RESET_RCON_SWR (1 << 6) /* Bit 6: Software reset */
-#define RESET_RCON_EXTR (1 << 7) /* Bit 7: External reset pin */
-#define RESET_RCON_VREGS (1 << 8) /* Bit 8: Voltage regulator standby enable */
-#define RESET_RCON_CMR (1 << 9) /* Bit 9: Configuration mismatch reset */
-
-/* Software reset register */
-
-#define RESET_RSWRST_TRIGGER (1 << 0) /* Bit 0: Software reset trigger */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H */
+/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-reset.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_RESET_RCON_OFFSET 0x0000 /* Reset control register */ +#define PIC32MX_RESET_RCONCLR_OFFSET 0x0004 /* RCON clear register */ +#define PIC32MX_RESET_RCONSET_OFFSET 0x0008 /* RCON set register */ +#define PIC32MX_RESET_RCONINV_OFFSET 0x000c /* RCON invert register */ +#define PIC32MX_RESET_RSWRST_OFFSET 0x0010 /* Software reset register */ +#define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */ +#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */ +#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */ + +/* Register Addresses ***************************************************************/ + +#define PIC32MX_RESET_RCON (PIC32MX_RESET_K1BASE+PIC32MX_RCON_OFFSET) +#define PIC32MX_RESET_RCONCLR (PIC32MX_RESET_K1BASE+PIC32MX_RCONCLR_OFFSET) +#define PIC32MX_RESET_RCONSET (PIC32MX_RESET_K1BASE+PIC32MX_RCONSET_OFFSET) +#define PIC32MX_RESET_RCONINV (PIC32MX_RESET_K1BASE+PIC32MX_RCONINV_OFFSET) +#define PIC32MX_RESET_RSWRST (PIC32MX_RESET_K1BASE+PIC32MX_RSWRST_OFFSET) +#define PIC32MX_RESET_RSWRSTCLR (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTCLR_OFFSET) +#define PIC32MX_RESET_RSWRSTSET (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTSET_OFFSET) +#define PIC32MX_RESET_RSWRSTINV (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTINV_OFFSET) + +/* Register Bit-Field Definitions ***************************************************/ + +/* Reset control register */ + +#define RESET_RCON_POR (1 << 0) /* Bit 0: Power on reset */ +#define RESET_RCON_BOR (1 << 1) /* Bit 1: Brown out reset */ +#define RESET_RCON_IDLE (1 << 2) /* Bit 2: Wake from idle */ +#define RESET_RCON_SLEEP (1 << 3) /* Bit 3: Wake from sleep */ +#define RESET_RCON_WDTO (1 << 4) /* Bit 4: Watchdog timer time-out */ +#define RESET_RCON_SWR (1 << 6) /* Bit 6: Software reset */ +#define RESET_RCON_EXTR (1 << 7) /* Bit 7: External reset pin */ +#define RESET_RCON_VREGS (1 << 8) /* Bit 8: Voltage regulator standby enable */ +#define RESET_RCON_CMR (1 << 9) /* Bit 9: Configuration mismatch reset */ + +/* Software reset register */ + +#define RESET_RSWRST_TRIGGER (1 << 0) /* Bit 0: Software reset trigger */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-rtcc.h b/nuttx/arch/mips/src/pic32mx/pic32mx-rtcc.h index 4a3c2a31d..5ecb9090c 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-rtcc.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-rtcc.h @@ -1,219 +1,219 @@ -/********************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-rtcc.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H
-
-/********************************************************************************************
- * Included Files
- ********************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "pic32mx-memorymap.h"
-
-/********************************************************************************************
- * Pre-Processor Definitions
- ********************************************************************************************/
-/* Register Offsets *************************************************************************/
-
-#define PIC32MX_RTCC_CON_OFFSET 0x0000 /* RTC Control Register */
-#define PIC32MX_RTCC_CONCLR_OFFSET 0x0004 /* RTC Control Clear Register */
-#define PIC32MX_RTCC_CONSET_OFFSET 0x0008 /* RTC Control Set Register */
-#define PIC32MX_RTCC_CONINV_OFFSET 0x000c /* RTC Control Invert Register */
-#define PIC32MX_RTCC_ALRM_OFFSET 0x0010 /* RTC ALARM Control Register */
-#define PIC32MX_RTCC_ALRMCLR_OFFSET 0x0014 /* RTC ALARM Control Clear Register */
-#define PIC32MX_RTCC_ALRMSET_OFFSET 0x0018 /* RTC ALARM Control Set Register */
-#define PIC32MX_RTCC_ALRMINV_OFFSET 0x001c /* RTC ALARM Control Invert Register */
-#define PIC32MX_RTCC_TIME_OFFSET 0x0020 /* RTC Time Value Register */
-#define PIC32MX_RTCC_TIMECLR_OFFSET 0x0024 /* RTC Time Value Clear Register */
-#define PIC32MX_RTCC_TIMESET_OFFSET 0x0028 /* RTC Time Value Set Register */
-#define PIC32MX_RTCC_TIMEINV_OFFSET 0x002c /* RTC Time Value Invert Register */
-#define PIC32MX_RTCC_DATE_OFFSET 0x0030 /* RTC Date Value Register */
-#define PIC32MX_RTCC_DATECLR_OFFSET 0x0034 /* RTC Date Value Clear Register */
-#define PIC32MX_RTCC_DATESET_OFFSET 0x0038 /* RTC Date Value Set Register */
-#define PIC32MX_RTCC_DATEINV_OFFSET 0x003c /* RTC Date Value Invert Register */
-#define PIC32MX_RTCC_ALRMTIME_OFFSET 0x0040 /* Alarm Time Value Register */
-#define PIC32MX_RTCC_ALRMTIMECLR_OFFSET 0x0044 /* Alarm Time Value Clear Register */
-#define PIC32MX_RTCC_ALRMTIMESET_OFFSET 0x0048 /* Alarm Time Value Set Register */
-#define PIC32MX_RTCC_ALRMTIMEINV_OFFSET 0x004c /* Alarm Time Value Invert Register */
-#define PIC32MX_RTCC_ALRMDATE_OFFSET 0x0050 /* Alarm Date Value Register */
-#define PIC32MX_RTCC_ALRMDATECLR_OFFSET 0x0054 /* Alarm Date Value Clear Register */
-#define PIC32MX_RTCC_ALRMDATESET_OFFSET 0x0058 /* Alarm Date Value Set Register */
-#define PIC32MX_RTCC_ALRMDATEINV_OFFSET 0x005c /* Alarm Date Value Invert Register */
-
-/* Register Addresses ***********************************************************************/
-
-#define PIC32MX_RTCC_CON (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CON_OFFSET)
-#define PIC32MX_RTCC_CONCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONCLR_OFFSET)
-#define PIC32MX_RTCC_CONSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONSET_OFFSET)
-#define PIC32MX_RTCC_CONINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONINV_OFFSET)
-#define PIC32MX_RTCC_ALRM (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRM_OFFSET)
-#define PIC32MX_RTCC_ALRMCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMCLR_OFFSET)
-#define PIC32MX_RTCC_ALRMSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMSET_OFFSET)
-#define PIC32MX_RTCC_ALRMINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMINV_OFFSET)
-#define PIC32MX_RTCC_TIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIME_OFFSET)
-#define PIC32MX_RTCC_TIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMECLR_OFFSET)
-#define PIC32MX_RTCC_TIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMESET_OFFSET)
-#define PIC32MX_RTCC_TIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMEINV_OFFSET)
-#define PIC32MX_RTCC_DATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATE_OFFSET)
-#define PIC32MX_RTCC_DATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATECLR_OFFSET)
-#define PIC32MX_RTCC_DATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATESET_OFFSET)
-#define PIC32MX_RTCC_DATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATEINV_OFFSET)
-#define PIC32MX_RTCC_ALRMTIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIME_OFFSET)
-#define PIC32MX_RTCC_ALRMTIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMECLR_OFFSET)
-#define PIC32MX_RTCC_ALRMTIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMESET_OFFSET)
-#define PIC32MX_RTCC_ALRMTIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMEINV_OFFSET)
-#define PIC32MX_RTCC_ALRMDATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATE_OFFSET)
-#define PIC32MX_RTCC_ALRMDATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATECLR_OFFSET)
-#define PIC32MX_RTCC_ALRMDATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATESET_OFFSET)
-#define PIC32MX_RTCC_ALRMDATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATEINV_OFFSET)
-
-/* Register Bit-Field Definitions ***********************************************************/
-
-/* RTC Control Register */
-
-#define RTCC_CON_CAL_SHIFT (16) /* Bits 16-25: RTC drift calibration */
-#define RTCC_CON_CAL_MASK (0x3ff << RTCC_CON_CAL_SHIFT) /* 10-bit 2's complement */
-# define RTCC_CON_CAL_MAX (0x1ff << RTCC_CON_CAL_SHIFT)
-# define RTCC_CON_CAL_CENTER (0x000 << RTCC_CON_CAL_SHIFT)
-# define RTCC_CON_CAL_MIN (0x200 << RTCC_CON_CAL_SHIFT)
-#define RTCC_CON_ON (1 << 15) /* Bit 15: RTCC on */
-#define RTCC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode */
-#define RTCC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
-#define RTCC_CON_RTSECSEL (1 << 9) /* Bit 7: RTCC seconds clock output select */
-#define RTCC_CON_RTCCLKON (1 << 8) /* Bit 6: RTCC clock enable status */
-#define RTCC_CON_RTCWREN (1 << 3) /* Bit 3: RTC value registers write enable */
-#define RTCC_CON_RTCSYNC (1 << 2) /* Bit 2: RTCC value registers read synchronization */
-#define RTCC_CON_HALFSEC (1 << 1) /* Bit 1: Half-second status */
-#define RTCC_CON_RTCOE (1 << 0) /* Bit 0: RTCC output enable */
-
-/* RTC ALARM Control Register */
-
-#define RTCC_ALRM_ARPT_SHIFT (0) /* Bits 0-7: Alarm repeat counter value */
-#define RTCC_ALRM_ARPT_MASK (0xff << RTCC_ALRM_ARPT_SHIFT)
-#define RTCC_ALRM_AMASK_SHIFT (8) /* Bits 8-11: Alarm mask configuration */
-#define RTCC_ALRM_AMASK_MASK (15 << RTCC_ALRM_AMASK_SHIFT)
-#define RTCC_ALRM_ALRMSYNC (1 << 12) /* Bit 12: Alarm sync */
-#define RTCC_ALRM_PIV (1 << 13) /* Bit 13: Alarm pulse initial value */
-#define RTCC_ALRM_CHIME (1 << 14) /* Bit 14: Chime enable */
-#define RTCC_ALRM_ALRMEN (1 << 15) /* Bit 15: Alarm enable */
-
-/* RTC Time Value Register */
-
-#define RTCC_TIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */
-#define RTCC_TIME_SEC01_MASK (15 << RTCC_TIME_SEC01_SHIFT)
-#define RTCC_TIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 10 digits */
-#define RTCC_TIME_SEC10_MASK (7 << RTCC_TIME_SEC10_SHIFT)
-#define RTCC_TIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */
-#define RTCC_TIME_MIN01_MASK (15 << RTCC_TIME_MIN01_SHIFT)
-#define RTCC_TIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 10 digits */
-#define RTCC_TIME_MIN10_MASK (7 << RTCC_TIME_MIN10_SHIFT)
-#define RTCC_TIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */
-#define RTCC_TIME_HR01_MASK (15 << RTCC_TIME_HR01_SHIFT)
-#define RTCC_TIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 10 digits */
-#define RTCC_TIME_HR10_MASK (3 << RTCC_TIME_HR10_SHIFT)
-
-/* RTC Date Value Register */
-
-#define RTCC_DATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */
-#define RTCC_DATE_WDAY01_MASK (7 << RTCC_DATE_WDAY01_SHIFT)
-#define RTCC_DATE_DAY01_SHIFT (8) /* Bits 8-11: BCD day, 1 digit */
-#define RTCC_DATE_DAY01_MASK (15 << RTCC_DATE_DAY01_SHIFT)
-#define RTCC_DATE_DAY10_SHIFT (12) /* Bits 12-13: BCD day, 10 digits */
-#define RTCC_DATE_DAY10_MASK (3 << RTCC_DATE_DAY10_SHIFT)
-#define RTCC_DATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */
-#define RTCC_DATE_MONTH01_MASK (15 << RTCC_DATE_MONTH01_SHIFT)
-#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */
-#define RTCC_DATE_YEAR01_SHIFT (24) /* Bits 24-27: BCD year, 1 digit */
-#define RTCC_DATE_YEAR01_MASK (15 << RTCC_DATE_YEAR01_SHIFT)
-#define RTCC_DATE_YEAR10_SHIFT (28) /* Bits 28-31: BCD year, 10 digits */
-#define RTCC_DATE_YEAR10_MASK (15 << RTCC_DATE_YEAR10_SHIFT)
-
-/* Alarm Time Value Register */
-
-#define RTCC_ALRMTIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */
-#define RTCC_ALRMTIME_SEC01_MASK (15 << RTCC_ALRMTIME_SEC01_SHIFT)
-#define RTCC_ALRMTIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 1 digit */
-#define RTCC_ALRMTIME_SEC10_MASK (7 << RTCC_ALRMTIME_SEC10_SHIFT)
-#define RTCC_ALRMTIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */
-#define RTCC_ALRMTIME_MIN01_MASK (15 << RTCC_ALRMTIME_MIN01_SHIFT)
-#define RTCC_ALRMTIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 1 digit */
-#define RTCC_ALRMTIME_MIN10_MASK (7 << RTCC_ALRMTIME_MIN10_SHIFT)
-#define RTCC_ALRMTIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */
-#define RTCC_ALRMTIME_HR01_MASK (15 << RTCC_ALRMTIME_HR01_SHIFT)
-#define RTCC_ALRMTIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 1 digit */
-#define RTCC_ALRMTIME_HR10_MASK (3 << RTCC_ALRMTIME_HR10_SHIFT)
-
-/* Alarm Date Value Register */
-
-#define RTCC_ALRMDATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */
-#define RTCC_ALRMDATE_WDAY01_MASK (7 << RTCC_ALRMDATE_WDAY01_SHIFT)
-#define RTCC_ALRMDATE_DAY01_SHIFT (8) /* Bits 8-11: BCD days, 1 digit */
-#define RTCC_ALRMDATE_DAY01_MASK (15 << RTCC_ALRMDATE_DAY01_SHIFT)
-#define RTCC_ALRMDATE_DAY10_SHIFT (12) /* Bits 12-13: BCD days, 1 digit */
-#define RTCC_ALRMDATE_DAY10_MASK (3 << RTCC_ALRMDATE_DAY10_SHIFT)
-#define RTCC_ALRMDATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */
-#define RTCC_ALRMDATE_MONTH01_MASK (15 << RTCC_ALRMDATE_MONTH01_SHIFT)
-#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */
-
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/********************************************************************************************
- * Inline Functions
- ********************************************************************************************/
-
-/********************************************************************************************
- * Public Function Prototypes
- ********************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H */
+/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-rtcc.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "pic32mx-memorymap.h" + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_RTCC_CON_OFFSET 0x0000 /* RTC Control Register */ +#define PIC32MX_RTCC_CONCLR_OFFSET 0x0004 /* RTC Control Clear Register */ +#define PIC32MX_RTCC_CONSET_OFFSET 0x0008 /* RTC Control Set Register */ +#define PIC32MX_RTCC_CONINV_OFFSET 0x000c /* RTC Control Invert Register */ +#define PIC32MX_RTCC_ALRM_OFFSET 0x0010 /* RTC ALARM Control Register */ +#define PIC32MX_RTCC_ALRMCLR_OFFSET 0x0014 /* RTC ALARM Control Clear Register */ +#define PIC32MX_RTCC_ALRMSET_OFFSET 0x0018 /* RTC ALARM Control Set Register */ +#define PIC32MX_RTCC_ALRMINV_OFFSET 0x001c /* RTC ALARM Control Invert Register */ +#define PIC32MX_RTCC_TIME_OFFSET 0x0020 /* RTC Time Value Register */ +#define PIC32MX_RTCC_TIMECLR_OFFSET 0x0024 /* RTC Time Value Clear Register */ +#define PIC32MX_RTCC_TIMESET_OFFSET 0x0028 /* RTC Time Value Set Register */ +#define PIC32MX_RTCC_TIMEINV_OFFSET 0x002c /* RTC Time Value Invert Register */ +#define PIC32MX_RTCC_DATE_OFFSET 0x0030 /* RTC Date Value Register */ +#define PIC32MX_RTCC_DATECLR_OFFSET 0x0034 /* RTC Date Value Clear Register */ +#define PIC32MX_RTCC_DATESET_OFFSET 0x0038 /* RTC Date Value Set Register */ +#define PIC32MX_RTCC_DATEINV_OFFSET 0x003c /* RTC Date Value Invert Register */ +#define PIC32MX_RTCC_ALRMTIME_OFFSET 0x0040 /* Alarm Time Value Register */ +#define PIC32MX_RTCC_ALRMTIMECLR_OFFSET 0x0044 /* Alarm Time Value Clear Register */ +#define PIC32MX_RTCC_ALRMTIMESET_OFFSET 0x0048 /* Alarm Time Value Set Register */ +#define PIC32MX_RTCC_ALRMTIMEINV_OFFSET 0x004c /* Alarm Time Value Invert Register */ +#define PIC32MX_RTCC_ALRMDATE_OFFSET 0x0050 /* Alarm Date Value Register */ +#define PIC32MX_RTCC_ALRMDATECLR_OFFSET 0x0054 /* Alarm Date Value Clear Register */ +#define PIC32MX_RTCC_ALRMDATESET_OFFSET 0x0058 /* Alarm Date Value Set Register */ +#define PIC32MX_RTCC_ALRMDATEINV_OFFSET 0x005c /* Alarm Date Value Invert Register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_RTCC_CON (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CON_OFFSET) +#define PIC32MX_RTCC_CONCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONCLR_OFFSET) +#define PIC32MX_RTCC_CONSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONSET_OFFSET) +#define PIC32MX_RTCC_CONINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONINV_OFFSET) +#define PIC32MX_RTCC_ALRM (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRM_OFFSET) +#define PIC32MX_RTCC_ALRMCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMCLR_OFFSET) +#define PIC32MX_RTCC_ALRMSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMSET_OFFSET) +#define PIC32MX_RTCC_ALRMINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMINV_OFFSET) +#define PIC32MX_RTCC_TIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIME_OFFSET) +#define PIC32MX_RTCC_TIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMECLR_OFFSET) +#define PIC32MX_RTCC_TIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMESET_OFFSET) +#define PIC32MX_RTCC_TIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMEINV_OFFSET) +#define PIC32MX_RTCC_DATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATE_OFFSET) +#define PIC32MX_RTCC_DATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATECLR_OFFSET) +#define PIC32MX_RTCC_DATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATESET_OFFSET) +#define PIC32MX_RTCC_DATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATEINV_OFFSET) +#define PIC32MX_RTCC_ALRMTIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIME_OFFSET) +#define PIC32MX_RTCC_ALRMTIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMECLR_OFFSET) +#define PIC32MX_RTCC_ALRMTIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMESET_OFFSET) +#define PIC32MX_RTCC_ALRMTIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMEINV_OFFSET) +#define PIC32MX_RTCC_ALRMDATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATE_OFFSET) +#define PIC32MX_RTCC_ALRMDATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATECLR_OFFSET) +#define PIC32MX_RTCC_ALRMDATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATESET_OFFSET) +#define PIC32MX_RTCC_ALRMDATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATEINV_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* RTC Control Register */ + +#define RTCC_CON_CAL_SHIFT (16) /* Bits 16-25: RTC drift calibration */ +#define RTCC_CON_CAL_MASK (0x3ff << RTCC_CON_CAL_SHIFT) /* 10-bit 2's complement */ +# define RTCC_CON_CAL_MAX (0x1ff << RTCC_CON_CAL_SHIFT) +# define RTCC_CON_CAL_CENTER (0x000 << RTCC_CON_CAL_SHIFT) +# define RTCC_CON_CAL_MIN (0x200 << RTCC_CON_CAL_SHIFT) +#define RTCC_CON_ON (1 << 15) /* Bit 15: RTCC on */ +#define RTCC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode */ +#define RTCC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +#define RTCC_CON_RTSECSEL (1 << 9) /* Bit 7: RTCC seconds clock output select */ +#define RTCC_CON_RTCCLKON (1 << 8) /* Bit 6: RTCC clock enable status */ +#define RTCC_CON_RTCWREN (1 << 3) /* Bit 3: RTC value registers write enable */ +#define RTCC_CON_RTCSYNC (1 << 2) /* Bit 2: RTCC value registers read synchronization */ +#define RTCC_CON_HALFSEC (1 << 1) /* Bit 1: Half-second status */ +#define RTCC_CON_RTCOE (1 << 0) /* Bit 0: RTCC output enable */ + +/* RTC ALARM Control Register */ + +#define RTCC_ALRM_ARPT_SHIFT (0) /* Bits 0-7: Alarm repeat counter value */ +#define RTCC_ALRM_ARPT_MASK (0xff << RTCC_ALRM_ARPT_SHIFT) +#define RTCC_ALRM_AMASK_SHIFT (8) /* Bits 8-11: Alarm mask configuration */ +#define RTCC_ALRM_AMASK_MASK (15 << RTCC_ALRM_AMASK_SHIFT) +#define RTCC_ALRM_ALRMSYNC (1 << 12) /* Bit 12: Alarm sync */ +#define RTCC_ALRM_PIV (1 << 13) /* Bit 13: Alarm pulse initial value */ +#define RTCC_ALRM_CHIME (1 << 14) /* Bit 14: Chime enable */ +#define RTCC_ALRM_ALRMEN (1 << 15) /* Bit 15: Alarm enable */ + +/* RTC Time Value Register */ + +#define RTCC_TIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */ +#define RTCC_TIME_SEC01_MASK (15 << RTCC_TIME_SEC01_SHIFT) +#define RTCC_TIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 10 digits */ +#define RTCC_TIME_SEC10_MASK (7 << RTCC_TIME_SEC10_SHIFT) +#define RTCC_TIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */ +#define RTCC_TIME_MIN01_MASK (15 << RTCC_TIME_MIN01_SHIFT) +#define RTCC_TIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 10 digits */ +#define RTCC_TIME_MIN10_MASK (7 << RTCC_TIME_MIN10_SHIFT) +#define RTCC_TIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */ +#define RTCC_TIME_HR01_MASK (15 << RTCC_TIME_HR01_SHIFT) +#define RTCC_TIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 10 digits */ +#define RTCC_TIME_HR10_MASK (3 << RTCC_TIME_HR10_SHIFT) + +/* RTC Date Value Register */ + +#define RTCC_DATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */ +#define RTCC_DATE_WDAY01_MASK (7 << RTCC_DATE_WDAY01_SHIFT) +#define RTCC_DATE_DAY01_SHIFT (8) /* Bits 8-11: BCD day, 1 digit */ +#define RTCC_DATE_DAY01_MASK (15 << RTCC_DATE_DAY01_SHIFT) +#define RTCC_DATE_DAY10_SHIFT (12) /* Bits 12-13: BCD day, 10 digits */ +#define RTCC_DATE_DAY10_MASK (3 << RTCC_DATE_DAY10_SHIFT) +#define RTCC_DATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */ +#define RTCC_DATE_MONTH01_MASK (15 << RTCC_DATE_MONTH01_SHIFT) +#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */ +#define RTCC_DATE_YEAR01_SHIFT (24) /* Bits 24-27: BCD year, 1 digit */ +#define RTCC_DATE_YEAR01_MASK (15 << RTCC_DATE_YEAR01_SHIFT) +#define RTCC_DATE_YEAR10_SHIFT (28) /* Bits 28-31: BCD year, 10 digits */ +#define RTCC_DATE_YEAR10_MASK (15 << RTCC_DATE_YEAR10_SHIFT) + +/* Alarm Time Value Register */ + +#define RTCC_ALRMTIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */ +#define RTCC_ALRMTIME_SEC01_MASK (15 << RTCC_ALRMTIME_SEC01_SHIFT) +#define RTCC_ALRMTIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 1 digit */ +#define RTCC_ALRMTIME_SEC10_MASK (7 << RTCC_ALRMTIME_SEC10_SHIFT) +#define RTCC_ALRMTIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */ +#define RTCC_ALRMTIME_MIN01_MASK (15 << RTCC_ALRMTIME_MIN01_SHIFT) +#define RTCC_ALRMTIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 1 digit */ +#define RTCC_ALRMTIME_MIN10_MASK (7 << RTCC_ALRMTIME_MIN10_SHIFT) +#define RTCC_ALRMTIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */ +#define RTCC_ALRMTIME_HR01_MASK (15 << RTCC_ALRMTIME_HR01_SHIFT) +#define RTCC_ALRMTIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 1 digit */ +#define RTCC_ALRMTIME_HR10_MASK (3 << RTCC_ALRMTIME_HR10_SHIFT) + +/* Alarm Date Value Register */ + +#define RTCC_ALRMDATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */ +#define RTCC_ALRMDATE_WDAY01_MASK (7 << RTCC_ALRMDATE_WDAY01_SHIFT) +#define RTCC_ALRMDATE_DAY01_SHIFT (8) /* Bits 8-11: BCD days, 1 digit */ +#define RTCC_ALRMDATE_DAY01_MASK (15 << RTCC_ALRMDATE_DAY01_SHIFT) +#define RTCC_ALRMDATE_DAY10_SHIFT (12) /* Bits 12-13: BCD days, 1 digit */ +#define RTCC_ALRMDATE_DAY10_MASK (3 << RTCC_ALRMDATE_DAY10_SHIFT) +#define RTCC_ALRMDATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */ +#define RTCC_ALRMDATE_MONTH01_MASK (15 << RTCC_ALRMDATE_MONTH01_SHIFT) +#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H */ diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-timerisr.c b/nuttx/arch/mips/src/pic32mx/pic32mx-timerisr.c index a3273e868..126c2a7bc 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-timerisr.c +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-timerisr.c @@ -2,7 +2,7 @@ * arch/mips/src/pic32mx/pic32mx_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/mips/src/pic32mx/pic32mx-wdt.h b/nuttx/arch/mips/src/pic32mx/pic32mx-wdt.h index e6dfeea93..5da30fa05 100644 --- a/nuttx/arch/mips/src/pic32mx/pic32mx-wdt.h +++ b/nuttx/arch/mips/src/pic32mx/pic32mx-wdt.h @@ -2,7 +2,7 @@ * arch/mips/src/pic32mx/pic32mx-wdt.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions |