diff options
Diffstat (limited to 'nuttx/arch/z80')
| -rwxr-xr-x | nuttx/arch/z80/src/ez80/ez80_spi.c | 2 | ||||
| -rw-r--r-- | nuttx/arch/z80/src/ez80/ez80f91_spi.h | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/nuttx/arch/z80/src/ez80/ez80_spi.c b/nuttx/arch/z80/src/ez80/ez80_spi.c index 5af30fd06..87984bf78 100755 --- a/nuttx/arch/z80/src/ez80/ez80_spi.c +++ b/nuttx/arch/z80/src/ez80/ez80_spi.c @@ -86,7 +86,7 @@ static const struct spi_ops_s g_spiops = spi_recvblock, }; -/* This supports is only a single SPI bus/port. There you port this to an +/* This supports is only a single SPI bus/port. If you port this to an * architecture with multiple SPI busses/ports, then the following must * become an array with one 'struct spi_dev_s' instance per bus. */ diff --git a/nuttx/arch/z80/src/ez80/ez80f91_spi.h b/nuttx/arch/z80/src/ez80/ez80f91_spi.h index 3334e472b..5a0305b68 100644 --- a/nuttx/arch/z80/src/ez80/ez80f91_spi.h +++ b/nuttx/arch/z80/src/ez80/ez80f91_spi.h @@ -60,7 +60,7 @@ * No bit definitions -- These two 8-bit registers set the 16-bit BRG divider value */ -/*SPI Control (CTL} Register Definitions */ +/* SPI Control (CTL} Register Definitions */ #define SPI_CTL_IRQEN (1 << 7) /* Bit 7: 1=SPI system interrupt is enabled */ #define SPI_CTL_SPIEN (1 << 5) /* Bit 5: 1=SPI is enabled */ @@ -109,8 +109,8 @@ extern "C" { * GPIOs in the way your board is configured. * 2. Add a call to up_spiinitialize() in your low level initialization logic * 3. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitializ() - * will bind the SPI driver to the SPI MMC/SD driver. + * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SPI driver to the SPI MMC/SD driver). */ EXTERN void ez80_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, boolean selected); |