diff options
Diffstat (limited to 'nuttx/arch')
-rw-r--r-- | nuttx/arch/z80/src/ez80/ez80_emac.c | 9 | ||||
-rw-r--r-- | nuttx/arch/z80/src/ez80/ez80_lowuart.c | 8 | ||||
-rw-r--r-- | nuttx/arch/z80/src/ez80/ez80_timerisr.c | 11 | ||||
-rw-r--r-- | nuttx/arch/z80/src/ez80/ez80f91.h | 4 |
4 files changed, 12 insertions, 20 deletions
diff --git a/nuttx/arch/z80/src/ez80/ez80_emac.c b/nuttx/arch/z80/src/ez80/ez80_emac.c index 42430be8f..f7dcb7904 100644 --- a/nuttx/arch/z80/src/ez80/ez80_emac.c +++ b/nuttx/arch/z80/src/ez80/ez80_emac.c @@ -117,11 +117,6 @@ # error "Unsupported CONFIG_EZ80_PKTBUFSIZE value" #endif -/* The system clock frequency is defined in the linkcmd file */ - -extern unsigned long SYS_CLK_FREQ; -#define _DEFCLK ((unsigned long)&SYS_CLK_FREQ) - /* Select the fastest MDC clock that does not exceed 25MHz. The MDC * clock derives from the SCLK divided by 4, 6, 8, 10, 14, 20, or 28. */ @@ -152,10 +147,10 @@ extern unsigned long SYS_CLK_FREQ; #define EMAC_RETRY 0x0f /* CFG3: Maximum number of retry default value */ /* Poll timer setting. The transmit poll timer is set in increments of - * SYSCLCK / 256 + * SYSCLCK / 256. NOTE: The system clock frequency is defined in the board.h file. */ -#define EMAC_PTMR ((CONFIG_EZ80_TXPOLLTIMERMS * (_DEFCLK / 1000) >> 8)) +#define EMAC_PTMR ((CONFIG_EZ80_TXPOLLTIMERMS * (ez80_systemclock / 1000) >> 8)) /* EMAC system interrupts : * diff --git a/nuttx/arch/z80/src/ez80/ez80_lowuart.c b/nuttx/arch/z80/src/ez80/ez80_lowuart.c index 32d08e875..a89c8089b 100644 --- a/nuttx/arch/z80/src/ez80/ez80_lowuart.c +++ b/nuttx/arch/z80/src/ez80/ez80_lowuart.c @@ -55,8 +55,6 @@ * Private Definitions ****************************************************************************/ -/* The system clock frequency is defined in the board.h file */ - /* Is there any serial support? This might be the case if the board does * not have serial ports but supports stdout through, say, an LCD. */ @@ -148,11 +146,13 @@ static void ez80_setbaud(void) /* The resulting BAUD and depends on the system clock frequency and the * BRG divisor as follows: * - * BAUD = SYSTEM_CLOCK_FREQUENCY / (16 * BRG_Divisor) + * BAUD = SYSTEM_CLOCK_FREQUENCY / (16 * BRG_Divisor) * * Or * - * BRG_Divisor = SYSTEM_CLOCK_FREQUENCY / 16 / BAUD + * BRG_Divisor = SYSTEM_CLOCK_FREQUENCY / 16 / BAUD + * + * NOTE: The system clock frequency value is defined in the board.h file */ brg_divisor = (ez80_systemclock + (CONFIG_UART_BAUD << 3)) / (CONFIG_UART_BAUD << 4); diff --git a/nuttx/arch/z80/src/ez80/ez80_timerisr.c b/nuttx/arch/z80/src/ez80/ez80_timerisr.c index 60e46322b..65e728f48 100644 --- a/nuttx/arch/z80/src/ez80/ez80_timerisr.c +++ b/nuttx/arch/z80/src/ez80/ez80_timerisr.c @@ -1,7 +1,7 @@ /*************************************************************************** * arch/z80/src/ez80/ez80_timerisr.c * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -53,11 +53,6 @@ * Definitions ***************************************************************************/ -/* The system clock frequency is defined in the linkcmd file */ - -extern unsigned long SYS_CLK_FREQ; -#define _DEFCLK ((unsigned long)&SYS_CLK_FREQ) - /*************************************************************************** * Private Types ***************************************************************************/ @@ -143,9 +138,11 @@ void up_timerinit(void) * * For a system timer of 50,000,000 that would result in a reload value of * 31,250 + * + * NOTE: The system clock frequency value is defined in the board.h file */ - reload = (uint16)(_DEFCLK / 1600); + reload = (uint16)(ez80_systemclock / 1600); outp(EZ80_TMR0_RRH, (ubyte)(reload >> 8)); outp(EZ80_TMR0_RRL, (ubyte)(reload)); diff --git a/nuttx/arch/z80/src/ez80/ez80f91.h b/nuttx/arch/z80/src/ez80/ez80f91.h index eeab61164..a554d12de 100644 --- a/nuttx/arch/z80/src/ez80/ez80f91.h +++ b/nuttx/arch/z80/src/ez80/ez80f91.h @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80f91.h * arch/z80/src/chip/ez80f91.h * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -206,7 +206,7 @@ # define EZ80_TMRCLKDIV_16 0x08 /* 01: 16 */ # define EZ80_TMRCLKDIV_64 0x10 /* 10: 64 */ # define EZ80_TMRCLKDIV_256 0x18 /* 11: 256 */ -#define EZ80_TMRCTL_TIMCONT 0x04 /* Bit 2: Continusous mode */ +#define EZ80_TMRCTL_TIMCONT 0x04 /* Bit 2: Continuous mode */ #define EZ80_TMRCTL_RLD 0x02 /* Bit 1: Force reload */ #define EZ80_TMRCTL_TIMEN 0x01 /* Bit 0: Programmable reload timer enabled */ |