diff options
Diffstat (limited to 'nuttx/arch')
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/Make.defs | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/chip.h | 0 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kinetis/kinetis_aips.h | 208 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_axbs.h | 2 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_gpio.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_internal.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_llwu.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_mcm.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_memorymap.h | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kinetis/kinetis_mpu.h | 398 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_pmc.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_port.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_sim.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_smc.h | 0 | ||||
-rw-r--r--[-rwxr-xr-x] | nuttx/arch/arm/src/kinetis/kinetis_uart.h | 0 |
15 files changed, 611 insertions, 5 deletions
diff --git a/nuttx/arch/arm/src/kinetis/Make.defs b/nuttx/arch/arm/src/kinetis/Make.defs index 3bf914308..3bf914308 100755..100644 --- a/nuttx/arch/arm/src/kinetis/Make.defs +++ b/nuttx/arch/arm/src/kinetis/Make.defs diff --git a/nuttx/arch/arm/src/kinetis/chip.h b/nuttx/arch/arm/src/kinetis/chip.h index 704f343e8..704f343e8 100755..100644 --- a/nuttx/arch/arm/src/kinetis/chip.h +++ b/nuttx/arch/arm/src/kinetis/chip.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_aips.h b/nuttx/arch/arm/src/kinetis/kinetis_aips.h new file mode 100644 index 000000000..6e0440147 --- /dev/null +++ b/nuttx/arch/arm/src/kinetis/kinetis_aips.h @@ -0,0 +1,208 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_aips.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define KINETIS_AIPS_MPRA_OFFSET 0x0000 /* Master Privilege Register A */ + +#define KINETIS_AIPS_PACRA_OFFSET 0x0020 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRB_OFFSET 0x0024 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRC_OFFSET 0x0028 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRD_OFFSET 0x002c /* Peripheral Access Control Register */ + +#define KINETIS_AIPS_PACRE_OFFSET 0x0040 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRF_OFFSET 0x0044 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRG_OFFSET 0x0048 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRH_OFFSET 0x004c /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRI_OFFSET 0x0050 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRJ_OFFSET 0x0054 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRK_OFFSET 0x0058 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRL_OFFSET 0x005c /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRM_OFFSET 0x0060 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRN_OFFSET 0x0064 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRO_OFFSET 0x0068 /* Peripheral Access Control Register */ +#define KINETIS_AIPS_PACRP_OFFSET 0x006c /* Peripheral Access Control Register */ + +/* Register Addresses ***************************************************************/ + +#define KINETIS_AIPS0_MPRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_MPRA_OFFSET) +#define KINETIS_AIPS0_PACRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRA_OFFSET) +#define KINETIS_AIPS0_PACRB (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRB_OFFSET) +#define KINETIS_AIPS0_PACRC (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRC_OFFSET) +#define KINETIS_AIPS0_PACRD (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRD_OFFSET) +#define KINETIS_AIPS0_PACRE (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRE_OFFSET) +#define KINETIS_AIPS0_PACRF (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRF_OFFSET) +#define KINETIS_AIPS0_PACRG (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRG_OFFSET) +#define KINETIS_AIPS0_PACRH (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRH_OFFSET) +#define KINETIS_AIPS0_PACRI (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRI_OFFSET) +#define KINETIS_AIPS0_PACRJ (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRJ_OFFSET) +#define KINETIS_AIPS0_PACRK (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRK_OFFSET) +#define KINETIS_AIPS0_PACRL (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRL_OFFSET) +#define KINETIS_AIPS0_PACRM (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRM_OFFSET) +#define KINETIS_AIPS0_PACRN (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRN_OFFSET) +#define KINETIS_AIPS0_PACRO (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRO_OFFSET) +#define KINETIS_AIPS0_PACRP (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRP_OFFSET) + +#define KINETIS_AIPS1_MPRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_MPRA_OFFSET) +#define KINETIS_AIPS1_PACRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRA_OFFSET) +#define KINETIS_AIPS1_PACRB (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRB_OFFSET) +#define KINETIS_AIPS1_PACRC (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRC_OFFSET) +#define KINETIS_AIPS1_PACRD (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRD_OFFSET) +#define KINETIS_AIPS1_PACRE (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRE_OFFSET) +#define KINETIS_AIPS1_PACRF (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRF_OFFSET) +#define KINETIS_AIPS1_PACRG (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRG_OFFSET) +#define KINETIS_AIPS1_PACRH (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRH_OFFSET) +#define KINETIS_AIPS1_PACRI (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRI_OFFSET) +#define KINETIS_AIPS1_PACRJ (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRJ_OFFSET) +#define KINETIS_AIPS1_PACRK (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRK_OFFSET) +#define KINETIS_AIPS1_PACRL (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRL_OFFSET) +#define KINETIS_AIPS1_PACRM (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRM_OFFSET) +#define KINETIS_AIPS1_PACRN (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRN_OFFSET) +#define KINETIS_AIPS1_PACRO (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRO_OFFSET) +#define KINETIS_AIPS1_PACRP (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRP_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Master Privilege Register A */ + + /* Bits 0-7: Reserved */ +#define AIPS_MPRA_MPL5 (1 << 8) /* Bit 8: Master privilege level */ +#define AIPS_MPRA_MTW5 (1 << 9) /* Bit 9: Master trusted for writes */ +#define AIPS_MPRA_MTR5 (1 << 10) /* Bit 10: Master trusted for read */ + /* Bit 11 Reserved */ +#define AIPS_MPRA_MPL4 (1 << 12) /* Bit 12: Master privilege level */ +#define AIPS_MPRA_MTW4 (1 << 13) /* Bit 13: Master trusted for writes */ +#define AIPS_MPRA_MTR4 (1 << 14) /* Bit 14: Master trusted for read */ + /* Bit 15: Reserved */ +#define AIPS_MPRA_MPL3 (1 << 16) /* Bit 16: Master privilege level */ +#define AIPS_MPRA_MTW3 (1 << 17) /* Bit 17: Master trusted for writes */ +#define AIPS_MPRA_MTR3 (1 << 18) /* Bit 18: Master trusted for read */ + /* Bit 19: Reserved */ +#define AIPS_MPRA_MPL2 (1 << 20) /* Bit 20: Master privilege level */ +#define AIPS_MPRA_MTW2 (1 << 21) /* Bit 21: Master trusted for writes */ +#define AIPS_MPRA_MTR2 (1 << 22) /* Bit 22: Master trusted for read */ + /* Bit 23: Reserved */ +#define AIPS_MPRA_MPL1 (1 << 24) /* Bit 24: Master privilege level */ +#define AIPS_MPRA_MTW1 (1 << 25) /* Bit 25: Master trusted for writes */ +#define AIPS_MPRA_MTR1 (1 << 26) /* Bit 26: Master trusted for read */ + /* Bit 27: Reserved */ +#define AIPS_MPRA_MPL0 (1 << 28) /* Bit 28: Master privilege level */ +#define AIPS_MPRA_MTW0 (1 << 29) /* Bit 29: Master trusted for writes */ +#define AIPS_MPRA_MTR0 (1 << 30) /* Bit 30: Master trusted for read */ + /* Bit 31: Reserved */ + +/* Peripheral Access Control Register. Naming here is only accurate for PACRA. + * PACRA: PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 + * PACRB: PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 + * PACRC: PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 + * PACRD: PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 + * PACRE: PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 PACR39 + * PACRF: PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 + * PACRG: PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 + * PACRH: PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 + * PACRI: PACR64 PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 + * PACRJ: PACR72 PACR73 PACR74 PACR75 PACR76 PACR77 PACR78 PACR79 + * PACRK: PACR80 PACR81 PACR82 PACR83 PACR84 PACR85 PACR86 PACR87 + * PACRL: PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 PACR95 + * PACRM: PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 + * PACRN: PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 + * PACRO: PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 + * PACRP: PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 + */ + +#define AIPS_PACR_TP(n) (1 << ((7 - ((n) & 7)) << 2)) +#define AIPS_PACR_WP(n) (2 << ((7 - ((n) & 7)) << 2)) +#define AIPS_PACR_SP(n) (4 << ((7 - ((n) & 7)) << 2)) + +#define AIPS_PACR_TP7 (1 << 0) /* Bit 0: Trusted protect */ +#define AIPS_PACR_WP7 (1 << 1) /* Bit 1: Write protect */ +#define AIPS_PACR_SP7 (1 << 2) /* Bit 2: Supervisor protect */ + /* Bit 3: Reserved */ +#define AIPS_PACR_TP6 (1 << 4) /* Bit 4: Trusted protect */ +#define AIPS_PACR_WP6 (1 << 5) /* Bit 5: Write protect */ +#define AIPS_PACR_SP6 (1 << 6) /* Bit 6: Supervisor protect */ + /* Bit 7: Reserved */ +#define AIPS_PACR_TP5 (1 << 8) /* Bit 8: Trusted protect */ +#define AIPS_PACR_WP5 (1 << 9) /* Bit 9: Write protect */ +#define AIPS_PACR_SP5 (1 << 10) /* Bit 10: Supervisor protect */ + /* Bit 11: Reserved */ +#define AIPS_PACR_TP4 (1 << 12) /* Bit 12: Trusted protect */ +#define AIPS_PACR_WP4 (1 << 13) /* Bit 13: Write protect */ +#define AIPS_PACR_SP4 (1 << 14) /* Bit 14: Supervisor protect */ + /* Bit 15: Reserved */ +#define AIPS_PACR_TP3 (1 << 16) /* Bit 16: Trusted protect */ +#define AIPS_PACR_WP3 (1 << 17) /* Bit 17: Write protect */ +#define AIPS_PACR_SP3 (1 << 18) /* Bit 18: Supervisor protect */ + /* Bit 19: Reserved */ +#define AIPS_PACR_TP2 (1 << 20) /* Bit 20: Trusted protect */ +#define AIPS_PACR_WP2 (1 << 21) /* Bit 21: Write protect */ +#define AIPS_PACR_SP2 (1 << 22) /* Bit 22: Supervisor protect */ + /* Bit 23: Reserved */ +#define AIPS_PACR_TP1 (1 << 24) /* Bit 24: Trusted protect */ +#define AIPS_PACR_WP1 (1 << 25) /* Bit 25: Write protect */ +#define AIPS_PACR_SP1 (1 << 26) /* Bit 26: Supervisor protect */ + /* Bit 27: Reserved */ +#define AIPS_PACR_TP0 (1 << 28) /* Bit 28: Trusted protect */ +#define AIPS_PACR_WP0 (1 << 29) /* Bit 29: Write protect */ +#define AIPS_PACR_SP0 (1 << 30) /* Bit 30: Supervisor protect */ + /* Bit 31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H */ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_axbs.h b/nuttx/arch/arm/src/kinetis/kinetis_axbs.h index 5459042de..4a5136005 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_axbs.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_axbs.h @@ -222,7 +222,7 @@ # define AXBS_CRS_ARB_FIXED (0 << AXBS_CRS_ARB_SHIFT) /* Fixed priority */ # define AXBS_CRS_ARB_MASK (1 << AXBS_CRS_ARB_SHIFT) /* Round-robin (rotating) priority */ /* Bits 10-29: Reserved */ -#define AXBS_CRS_HLP (1 < 30) /* Bit 30: Halt low priority */ +#define AXBS_CRS_HLP (1 < 30) /* Bit 30: Halt low priority */ #define AXBS_CRS_RO (1 < 31) /* Bit 31: Read only */ /* Master General Purpose Control Register */ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_gpio.h b/nuttx/arch/arm/src/kinetis/kinetis_gpio.h index 8a87aa72a..8a87aa72a 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_gpio.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_gpio.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_internal.h b/nuttx/arch/arm/src/kinetis/kinetis_internal.h index 3691dccde..3691dccde 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_internal.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_internal.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_llwu.h b/nuttx/arch/arm/src/kinetis/kinetis_llwu.h index 60fa2fed7..60fa2fed7 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_llwu.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_llwu.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_mcm.h b/nuttx/arch/arm/src/kinetis/kinetis_mcm.h index 8424587aa..8424587aa 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_mcm.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_mcm.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h index bcc5e73e8..957b7b7e1 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_memorymap.h @@ -95,7 +95,7 @@ /* Peripheral Bridge 0 Memory Map ***************************************************/ -# define KINETIS_PBRIDGE0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ # define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ # define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ @@ -150,7 +150,7 @@ /* Peripheral Bridge 1 Memory Map ***************************************************/ -# define KINETIS_PBRIDGE1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ # define KINETIS_FLEXCAN1_BASE 0x400a4000 /* FlexCAN 1 */ # define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */ # define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ @@ -226,7 +226,7 @@ /* Peripheral Bridge 0 Memory Map ***************************************************/ -# define KINETIS_PBRIDGE0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ # define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ # define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ @@ -281,7 +281,7 @@ /* Peripheral Bridge 1 Memory Map ***************************************************/ -# define KINETIS_PBRIDGE1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ # define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ # define KINETIS_FLEXCAN1_BASE 0x400a4000 /* FlexCAN 1 */ # define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_mpu.h b/nuttx/arch/arm/src/kinetis/kinetis_mpu.h new file mode 100644 index 000000000..9db2570b9 --- /dev/null +++ b/nuttx/arch/arm/src/kinetis/kinetis_mpu.h @@ -0,0 +1,398 @@ +/**************************************************************************************************** + * arch/arm/src/kinetis/kinetis_mpu.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */ + +#define KINETIS_MPU_EAR_OFFSET(n) (0x0010+((n)<<3)) /* Error Address Register, Slave Port n */ +#define KINETIS_MPU_EDR_OFFSET(n) (0x0014+((n)<<3)) /* Error Detail Register, Slave Port n */ + +#define KINETIS_MPU_EAR0_OFFSET 0x0010 /* Error Address Register, Slave Port 0 */ +#define KINETIS_MPU_EDR0_OFFSET 0x0014 /* Error Detail Register, Slave Port 0 */ +#define KINETIS_MPU_EAR1_OFFSET 0x0018 /* Error Address Register, Slave Port 1 */ +#define KINETIS_MPU_EDR1_OFFSET 0x001c /* Error Detail Register, Slave Port 1 */ +#define KINETIS_MPU_EAR2_OFFSET 0x0020 /* Error Address Register, Slave Port 2 */ +#define KINETIS_MPU_EDR2_OFFSET 0x0024 /* Error Detail Register, Slave Port 2 */ +#define KINETIS_MPU_EAR3_OFFSET 0x0028 /* Error Address Register, Slave Port 3 */ +#define KINETIS_MPU_EDR3_OFFSET 0x002c /* Error Detail Register, Slave Port 3 */ +#define KINETIS_MPU_EAR4_OFFSET 0x0030 /* Error Address Register, Slave Port 4 */ +#define KINETIS_MPU_EDR4_OFFSET 0x0034 /* Error Detail Register, Slave Port 4 */ + +#define KINETIS_MPU_RGD_WORD_OFFSET(n,m) (x0400+((n)<<4)+((m)<< 2) /* Region Descriptor n, Word m */ + +#define KINETIS_MPU_RGD0_WORD0_OFFSET 0x0400 /* Region Descriptor 0, Word 0 */ +#define KINETIS_MPU_RGD0_WORD1_OFFSET 0x0404 /* Region Descriptor 0, Word 1 */ +#define KINETIS_MPU_RGD0_WORD2_OFFSET 0x0408 /* Region Descriptor 0, Word 2 */ +#define KINETIS_MPU_RGD0_WORD3_OFFSET 0x040c /* Region Descriptor 0, Word 3 */ +#define KINETIS_MPU_RGD1_WORD0_OFFSET 0x0410 /* Region Descriptor 1, Word 0 */ +#define KINETIS_MPU_RGD1_WORD1_OFFSET 0x0414 /* Region Descriptor 1, Word 1 */ +#define KINETIS_MPU_RGD1_WORD2_OFFSET 0x0418 /* Region Descriptor 1, Word 2 */ +#define KINETIS_MPU_RGD1_WORD3_OFFSET 0x041c /* Region Descriptor 1, Word 3 */ +#define KINETIS_MPU_RGD2_WORD0_OFFSET 0x0420 /* Region Descriptor 2, Word 0 */ +#define KINETIS_MPU_RGD2_WORD1_OFFSET 0x0424 /* Region Descriptor 2, Word 1 */ +#define KINETIS_MPU_RGD2_WORD2_OFFSET 0x0428 /* Region Descriptor 2, Word 2 */ +#define KINETIS_MPU_RGD2_WORD3_OFFSET 0x042c /* Region Descriptor 2, Word 3 */ +#define KINETIS_MPU_RGD3_WORD0_OFFSET 0x0430 /* Region Descriptor 3, Word 0 */ +#define KINETIS_MPU_RGD3_WORD1_OFFSET 0x0434 /* Region Descriptor 3, Word 1 */ +#define KINETIS_MPU_RGD3_WORD2_OFFSET 0x0438 /* Region Descriptor 3, Word 2 */ +#define KINETIS_MPU_RGD3_WORD3_OFFSET 0x043c /* Region Descriptor 3, Word 3 */ +#define KINETIS_MPU_RGD4_WORD0_OFFSET 0x0440 /* Region Descriptor 4, Word 0 */ +#define KINETIS_MPU_RGD4_WORD1_OFFSET 0x0444 /* Region Descriptor 4, Word 1 */ +#define KINETIS_MPU_RGD4_WORD2_OFFSET 0x0448 /* Region Descriptor 4, Word 2 */ +#define KINETIS_MPU_RGD4_WORD3_OFFSET 0x044c /* Region Descriptor 4, Word 3 */ +#define KINETIS_MPU_RGD5_WORD0_OFFSET 0x0450 /* Region Descriptor 5, Word 0 */ +#define KINETIS_MPU_RGD5_WORD1_OFFSET 0x0454 /* Region Descriptor 5, Word 1 */ +#define KINETIS_MPU_RGD5_WORD2_OFFSET 0x0458 /* Region Descriptor 5, Word 2 */ +#define KINETIS_MPU_RGD5_WORD3_OFFSET 0x045c /* Region Descriptor 5, Word 3 */ +#define KINETIS_MPU_RGD6_WORD0_OFFSET 0x0460 /* Region Descriptor 6, Word 0 */ +#define KINETIS_MPU_RGD6_WORD1_OFFSET 0x0464 /* Region Descriptor 6, Word 1 */ +#define KINETIS_MPU_RGD6_WORD2_OFFSET 0x0468 /* Region Descriptor 6, Word 2 */ +#define KINETIS_MPU_RGD6_WORD3_OFFSET 0x046c /* Region Descriptor 6, Word 3 */ +#define KINETIS_MPU_RGD7_WORD0_OFFSET 0x0470 /* Region Descriptor 7, Word 0 */ +#define KINETIS_MPU_RGD7_WORD1_OFFSET 0x0474 /* Region Descriptor 7, Word 1 */ +#define KINETIS_MPU_RGD7_WORD2_OFFSET 0x0478 /* Region Descriptor 7, Word 2 */ +#define KINETIS_MPU_RGD7_WORD3_OFFSET 0x047c /* Region Descriptor 7, Word 3 */ +#define KINETIS_MPU_RGD8_WORD0_OFFSET 0x0480 /* Region Descriptor 8, Word 0 */ +#define KINETIS_MPU_RGD8_WORD1_OFFSET 0x0484 /* Region Descriptor 8, Word 1 */ +#define KINETIS_MPU_RGD8_WORD2_OFFSET 0x0488 /* Region Descriptor 8, Word 2 */ +#define KINETIS_MPU_RGD8_WORD3_OFFSET 0x048c /* Region Descriptor 8, Word 3 */ +#define KINETIS_MPU_RGD9_WORD0_OFFSET 0x0490 /* Region Descriptor 9, Word 0 */ +#define KINETIS_MPU_RGD9_WORD1_OFFSET 0x0494 /* Region Descriptor 9, Word 1 */ +#define KINETIS_MPU_RGD9_WORD2_OFFSET 0x0498 /* Region Descriptor 9, Word 2 */ +#define KINETIS_MPU_RGD9_WORD3_OFFSET 0x049c /* Region Descriptor 9, Word 3 */ +#define KINETIS_MPU_RGD10_WORD0_OFFSET 0x04a0 /* Region Descriptor 10, Word 0 */ +#define KINETIS_MPU_RGD10_WORD1_OFFSET 0x04a4 /* Region Descriptor 10, Word 1 */ +#define KINETIS_MPU_RGD10_WORD2_OFFSET 0x04a8 /* Region Descriptor 10, Word 2 */ +#define KINETIS_MPU_RGD10_WORD3_OFFSET 0x04ac /* Region Descriptor 10, Word 3 */ +#define KINETIS_MPU_RGD11_WORD0_OFFSET 0x04b0 /* Region Descriptor 11, Word 0 */ +#define KINETIS_MPU_RGD11_WORD1_OFFSET 0x04b4 /* Region Descriptor 11, Word 1 */ +#define KINETIS_MPU_RGD11_WORD2_OFFSET 0x04b8 /* Region Descriptor 11, Word 2 */ +#define KINETIS_MPU_RGD11_WORD3_OFFSET 0x04bc /* Region Descriptor 11, Word 3 */ +#define KINETIS_MPU_RGD12_WORD0_OFFSET 0x04c0 /* Region Descriptor 12, Word 0 */ +#define KINETIS_MPU_RGD12_WORD1_OFFSET 0x04c4 /* Region Descriptor 12, Word 1 */ +#define KINETIS_MPU_RGD12_WORD2_OFFSET 0x04c8 /* Region Descriptor 12, Word 2 */ +#define KINETIS_MPU_RGD12_WORD3_OFFSET 0x04cc /* Region Descriptor 12, Word 3 */ +#define KINETIS_MPU_RGD13_WORD0_OFFSET 0x04d0 /* Region Descriptor 13, Word 0 */ +#define KINETIS_MPU_RGD13_WORD1_OFFSET 0x04d4 /* Region Descriptor 13, Word 1 */ +#define KINETIS_MPU_RGD13_WORD2_OFFSET 0x04d8 /* Region Descriptor 13, Word 2 */ +#define KINETIS_MPU_RGD13_WORD3_OFFSET 0x04dc /* Region Descriptor 13, Word 3 */ +#define KINETIS_MPU_RGD14_WORD0_OFFSET 0x04e0 /* Region Descriptor 14, Word 0 */ +#define KINETIS_MPU_RGD14_WORD1_OFFSET 0x04e4 /* Region Descriptor 14, Word 1 */ +#define KINETIS_MPU_RGD14_WORD2_OFFSET 0x04e8 /* Region Descriptor 14, Word 2 */ +#define KINETIS_MPU_RGD14_WORD3_OFFSET 0x04ec /* Region Descriptor 14, Word 3 */ +#define KINETIS_MPU_RGD15_WORD0_OFFSET 0x04f0 /* Region Descriptor 15, Word 0 */ +#define KINETIS_MPU_RGD15_WORD1_OFFSET 0x04f4 /* Region Descriptor 15, Word 1 */ +#define KINETIS_MPU_RGD15_WORD2_OFFSET 0x04f8 /* Region Descriptor 15, Word 2 */ +#define KINETIS_MPU_RGD15_WORD3_OFFSET 0x04fc /* Region Descriptor 15, Word 3 */ + +#define KINETIS_MPU_RGDAAC_OFFSET(n) (0x0800+((n)<<2)) /* Region Descriptor Alternate Access Control n */ + +#define KINETIS_MPU_RGDAAC0_OFFSET 0x0800 /* Region Descriptor Alternate Access Control 0 */ +#define KINETIS_MPU_RGDAAC1_OFFSET 0x0804 /* Region Descriptor Alternate Access Control 1 */ +#define KINETIS_MPU_RGDAAC2_OFFSET 0x0808 /* Region Descriptor Alternate Access Control 2 */ +#define KINETIS_MPU_RGDAAC3_OFFSET 0x080c /* Region Descriptor Alternate Access Control 3 */ +#define KINETIS_MPU_RGDAAC4_OFFSET 0x0810 /* Region Descriptor Alternate Access Control 4 */ +#define KINETIS_MPU_RGDAAC5_OFFSET 0x0814 /* Region Descriptor Alternate Access Control 5 */ +#define KINETIS_MPU_RGDAAC6_OFFSET 0x0818 /* Region Descriptor Alternate Access Control 6 */ +#define KINETIS_MPU_RGDAAC7_OFFSET 0x081c /* Region Descriptor Alternate Access Control 7 */ +#define KINETIS_MPU_RGDAAC8_OFFSET 0x0820 /* Region Descriptor Alternate Access Control 8 */ +#define KINETIS_MPU_RGDAAC9_OFFSET 0x0824 /* Region Descriptor Alternate Access Control 9 */ +#define KINETIS_MPU_RGDAAC10_OFFSET 0x0828 /* Region Descriptor Alternate Access Control 10 */ +#define KINETIS_MPU_RGDAAC11_OFFSET 0x082c /* Region Descriptor Alternate Access Control 11 */ +#define KINETIS_MPU_RGDAAC12_OFFSET 0x0830 /* Region Descriptor Alternate Access Control 12 */ +#define KINETIS_MPU_RGDAAC13_OFFSET 0x0834 /* Region Descriptor Alternate Access Control 13 */ +#define KINETIS_MPU_RGDAAC14_OFFSET 0x0838 /* Region Descriptor Alternate Access Control 14 */ +#define KINETIS_MPU_RGDAAC15_OFFSET 0x083c /* Region Descriptor Alternate Access Control 15 */ + +/* Register Addresses *******************************************************************************/ + +#define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET) + +#define KINETIS_MPU_EAR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EAR_OFFSET(n)) +#define KINETIS_MPU_EDR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EDR_OFFSET(n)) + +#define KINETIS_MPU_EAR0 (KINETIS_MPU_BASE+KINETIS_MPU_EAR0_OFFSET) +#define KINETIS_MPU_EDR0 (KINETIS_MPU_BASE+KINETIS_MPU_EDR0_OFFSET) +#define KINETIS_MPU_EAR1 (KINETIS_MPU_BASE+KINETIS_MPU_EAR1_OFFSET) +#define KINETIS_MPU_EDR1 (KINETIS_MPU_BASE+KINETIS_MPU_EDR1_OFFSET) +#define KINETIS_MPU_EAR2 (KINETIS_MPU_BASE+KINETIS_MPU_EAR2_OFFSET) +#define KINETIS_MPU_EDR2 (KINETIS_MPU_BASE+KINETIS_MPU_EDR2_OFFSET) +#define KINETIS_MPU_EAR3 (KINETIS_MPU_BASE+KINETIS_MPU_EAR3_OFFSET) +#define KINETIS_MPU_EDR3 (KINETIS_MPU_BASE+KINETIS_MPU_EDR3_OFFSET) +#define KINETIS_MPU_EAR4 (KINETIS_MPU_BASE+KINETIS_MPU_EAR4_OFFSET) +#define KINETIS_MPU_EDR4 (KINETIS_MPU_BASE+KINETIS_MPU_EDR4_OFFSET) + +#define KINETIS_MPU_RGD_WORD(n,m) (KINETIS_MPU_BASE+KINETIS_MPU_RGD_WORD_OFFSET(n,m)) + +#define KINETIS_MPU_RGD0_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD0_OFFSET) +#define KINETIS_MPU_RGD0_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD1_OFFSET) +#define KINETIS_MPU_RGD0_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD2_OFFSET) +#define KINETIS_MPU_RGD0_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD3_OFFSET) +#define KINETIS_MPU_RGD1_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD0_OFFSET) +#define KINETIS_MPU_RGD1_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD1_OFFSET) +#define KINETIS_MPU_RGD1_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD2_OFFSET) +#define KINETIS_MPU_RGD1_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD3_OFFSET) +#define KINETIS_MPU_RGD2_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD0_OFFSET) +#define KINETIS_MPU_RGD2_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD1_OFFSET) +#define KINETIS_MPU_RGD2_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD2_OFFSET) +#define KINETIS_MPU_RGD2_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD3_OFFSET) +#define KINETIS_MPU_RGD3_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD0_OFFSET) +#define KINETIS_MPU_RGD3_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD1_OFFSET) +#define KINETIS_MPU_RGD3_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD2_OFFSET) +#define KINETIS_MPU_RGD3_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD3_OFFSET) +#define KINETIS_MPU_RGD4_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD0_OFFSET) +#define KINETIS_MPU_RGD4_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD1_OFFSET) +#define KINETIS_MPU_RGD4_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD2_OFFSET) +#define KINETIS_MPU_RGD4_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD3_OFFSET) +#define KINETIS_MPU_RGD5_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD0_OFFSET) +#define KINETIS_MPU_RGD5_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD1_OFFSET) +#define KINETIS_MPU_RGD5_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD2_OFFSET) +#define KINETIS_MPU_RGD5_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD3_OFFSET) +#define KINETIS_MPU_RGD6_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD0_OFFSET) +#define KINETIS_MPU_RGD6_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD1_OFFSET) +#define KINETIS_MPU_RGD6_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD2_OFFSET) +#define KINETIS_MPU_RGD6_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD3_OFFSET) +#define KINETIS_MPU_RGD7_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD0_OFFSET) +#define KINETIS_MPU_RGD7_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD1_OFFSET) +#define KINETIS_MPU_RGD7_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD2_OFFSET) +#define KINETIS_MPU_RGD7_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD3_OFFSET) +#define KINETIS_MPU_RGD8_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD0_OFFSET) +#define KINETIS_MPU_RGD8_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD1_OFFSET) +#define KINETIS_MPU_RGD8_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD2_OFFSET) +#define KINETIS_MPU_RGD8_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD3_OFFSET) +#define KINETIS_MPU_RGD9_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD0_OFFSET) +#define KINETIS_MPU_RGD9_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD1_OFFSET) +#define KINETIS_MPU_RGD9_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD2_OFFSET) +#define KINETIS_MPU_RGD9_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD3_OFFSET) +#define KINETIS_MPU_RGD10_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD0_OFFSET) +#define KINETIS_MPU_RGD10_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD1_OFFSET) +#define KINETIS_MPU_RGD10_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD2_OFFSET) +#define KINETIS_MPU_RGD10_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD3_OFFSET) +#define KINETIS_MPU_RGD11_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD0_OFFSET) +#define KINETIS_MPU_RGD11_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD1_OFFSET) +#define KINETIS_MPU_RGD11_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD2_OFFSET) +#define KINETIS_MPU_RGD11_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD3_OFFSET) +#define KINETIS_MPU_RGD12_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD12_WORD0_OFFSET) +#define KINETIS_MPU_RGD12_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD12_WORD1_OFFSET) +#define KINETIS_MPU_RGD12_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD12_WORD2_OFFSET) +#define KINETIS_MPU_RGD12_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD12_WORD3_OFFSET) +#define KINETIS_MPU_RGD13_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD13_WORD0_OFFSET) +#define KINETIS_MPU_RGD13_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD13_WORD1_OFFSET) +#define KINETIS_MPU_RGD13_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD13_WORD2_OFFSET) +#define KINETIS_MPU_RGD13_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD13_WORD3_OFFSET) +#define KINETIS_MPU_RGD14_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD14_WORD0_OFFSET) +#define KINETIS_MPU_RGD14_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD14_WORD1_OFFSET) +#define KINETIS_MPU_RGD14_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD14_WORD2_OFFSET) +#define KINETIS_MPU_RGD14_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD14_WORD3_OFFSET) +#define KINETIS_MPU_RGD15_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD15_WORD0_OFFSET) +#define KINETIS_MPU_RGD15_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD15_WORD1_OFFSET) +#define KINETIS_MPU_RGD15_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD15_WORD2_OFFSET) +#define KINETIS_MPU_RGD15_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD15_WORD3_OFFSET) + +#define KINETIS_MPU_RGDAAC(n) (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC_OFFSET(n)) + +#define KINETIS_MPU_RGDAAC0 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC0_OFFSET) +#define KINETIS_MPU_RGDAAC1 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC1_OFFSET) +#define KINETIS_MPU_RGDAAC2 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC2_OFFSET) +#define KINETIS_MPU_RGDAAC3 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC3_OFFSET) +#define KINETIS_MPU_RGDAAC4 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC4_OFFSET) +#define KINETIS_MPU_RGDAAC5 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC5_OFFSET) +#define KINETIS_MPU_RGDAAC6 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC6_OFFSET) +#define KINETIS_MPU_RGDAAC7 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC7_OFFSET) +#define KINETIS_MPU_RGDAAC8 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC8_OFFSET) +#define KINETIS_MPU_RGDAAC9 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC9_OFFSET) +#define KINETIS_MPU_RGDAAC10 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC10_OFFSET) +#define KINETIS_MPU_RGDAAC11 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC11_OFFSET) +#define KINETIS_MPU_RGDAAC12 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC12_OFFSET) +#define KINETIS_MPU_RGDAAC13 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC13_OFFSET) +#define KINETIS_MPU_RGDAAC14 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC14_OFFSET) +#define KINETIS_MPU_RGDAAC15 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC15_OFFSET) + +/* Register Bit Definitions *************************************************************************/ + +/* Control/Error Status Register */ + +#define MPU_CESR_VLD (1 << 0) /* Bit 0: Valid (global enable/disable for the MPU) */ + /* Bits 1-7: Reserved */ +#define MPU_CESR_NRGD_SHIFT (8) /* Bits 8-11: Number of region descriptors */ +#define MPU_CESR_NRGD_MASK (15 << MPU_CESR_NRGD_SHIFT) +# define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */ +# define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */ +# define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */ +#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */ +#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT) +#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */ +#define MPU_CESR_HRL_MASK (15 << MPU_CESR_HRL_SHIFT) + /* Bits 20-26: Reserved */ +#define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */ +#define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT) +# define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */ +# define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */ +# define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */ +# define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */ +# define MPU_CESR_SPERR_SPORT3 (2 << MPU_CESR_SPERR_SHIFT) /* Slave port 3 */ +# define MPU_CESR_SPERR_SPORT4 (1 << MPU_CESR_SPERR_SHIFT) /* Slave port 4 */ + +/* Error Address Register, Slave Port n. 32-bit error address. */ + +/* Error Detail Register, Slave Port n */ + +#define MPU_EDR_ERW (1 << 0) /* Bit 0: Error read/write */ +#define MPU_EDR_EATTR_SHIFT (1) /* Bits 1-3: Error attributes */ +#define MPU_EDR_EATTR_MASK (7 << MPU_EDR_EATTR_SHIFT) +# define MPU_EDR_EATTR_USRINST (0 << MPU_EDR_EATTR_SHIFT) /* User mode, instruction access */ +# define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */ +# define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */ +# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */ +#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */ +#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT) + /* Bits 8-15: Reserved */ +#define MPU_EDR_EACD_SHIFT (26) /* Bits 16-31: Error access control detail */ +#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT) + +/* Region Descriptor n, Word 0 */ + /* Bits 0-4: Reserved */ +#define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */ +#define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0) + +/* Region Descriptor n, Word 1 */ + /* Bits 0-4: Reserved */ +#define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */ +#define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0) + +/* Region Descriptor n, Word 2 */ + +#define MPU_RGD_MSM_RWX 0 /* R/W/X; read, write and execute allowed */ +#define MPU_RGD_MSM_RX 1 /* R/X; read and execute allowed, but no write */ +#define MPU_RGD_MSM_RW 2 /* R/W; read and write allowed, but no execute */ +#define MPU_RGD_MSM_UM 3 /* Same as user mode defined in MUM */ + +#define MPU_RGD_MUM_R 4 /* Read allowed */ +#define MPU_RGD_MUM_W 2 /* Write allowed */ +#define MPU_RGD_MUM_X 1 /* Execute allocated */ + +#define MPU_RGD_WORD2_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */ +#define MPU_RGD_WORD2_M0UM_MASK (7 << MPU_RGD_WORD2_M0UM_SHIFT) +#define MPU_RGD_WORD2_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */ +#define MPU_RGD_WORD2_M0SM_MASK (3 << MPU_RGD_WORD2_M0SM_SHIFT) + /* Bit 5: Reserved */ +#define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */ +#define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT) +#define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */ +#define MPU_RGD_WORD2_M1SM_MASK (3 << MPU_RGD_WORD2_M1SM_SHIFT) + /* Bit 11: Reserved */ +#define MPU_RGD_WORD2_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */ +#define MPU_RGD_WORD2_M2UM_MASK (7 << MPU_RGD_WORD2_M2UM_SHIFT) +#define MPU_RGD_WORD2_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */ +#define MPU_RGD_WORD2_M2SM_MASK (3 << MPU_RGD_WORD2_M2SM_SHIFT) + /* Bit 17: Reserved */ +#define MPU_RGD_WORD2_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */ +#define MPU_RGD_WORD2_M3UM_MASK (7 << MPU_RGD_WORD2_M3UM_SHIFT) +#define MPU_RGD_WORD2_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */ +#define MPU_RGD_WORD2_M3SM_MASK (3 << MPU_RGD_WORD2_M3SM_SHIFT) + /* Bit 23: Reserved */ +#define MPU_RGD_WORD2_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */ +#define MPU_RGD_WORD2_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */ +#define MPU_RGD_WORD2_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */ +#define MPU_RGD_WORD2_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */ +#define MPU_RGD_WORD2_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */ +#define MPU_RGD_WORD2_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */ +#define MPU_RGD_WORD2_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */ +#define MPU_RGD_WORD2_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */ + +/* Region Descriptor n, Word 3 */ + +#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */ + /* Bits 1-31: Reserved */ +/* Region Descriptor Alternate Access Control n */ + +#define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */ +#define MPU_RGD_RBDACC_M0UM_MASK (7 << MPU_RGD_RBDACC_M0UM_SHIFT) +#define MPU_RGD_RBDACC_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */ +#define MPU_RGD_RBDACC_M0SM_MASK (3 << MPU_RGD_RBDACC_M0SM_SHIFT) + /* Bit 5: Reserved */ +#define MPU_RGD_RBDACC_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */ +#define MPU_RGD_RBDACC_M1UM_MASK (7 << MPU_RGD_RBDACC_M1UM_SHIFT) +#define MPU_RGD_RBDACC_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */ +#define MPU_RGD_RBDACC_M1SM_MASK (3 << MPU_RGD_RBDACC_M1SM_SHIFT) + /* Bit 11: Reserved */ +#define MPU_RGD_RBDACC_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */ +#define MPU_RGD_RBDACC_M2UM_MASK (7 << MPU_RGD_RBDACC_M2UM_SHIFT) +#define MPU_RGD_RBDACC_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */ +#define MPU_RGD_RBDACC_M2SM_MASK (3 << MPU_RGD_RBDACC_M2SM_SHIFT) + /* Bit 17: Reserved */ +#define MPU_RGD_RBDACC_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */ +#define MPU_RGD_RBDACC_M3UM_MASK (7 << MPU_RGD_RBDACC_M3UM_SHIFT) +#define MPU_RGD_RBDACC_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */ +#define MPU_RGD_RBDACC_M3SM_MASK (3 << MPU_RGD_RBDACC_M3SM_SHIFT) + /* Bit 23: Reserved */ +#define MPU_RGD_RBDACC_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */ +#define MPU_RGD_RBDACC_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */ +#define MPU_RGD_RBDACC_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */ +#define MPU_RGD_RBDACC_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */ +#define MPU_RGD_RBDACC_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */ +#define MPU_RGD_RBDACC_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */ +#define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */ +#define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H */ diff --git a/nuttx/arch/arm/src/kinetis/kinetis_pmc.h b/nuttx/arch/arm/src/kinetis/kinetis_pmc.h index 2525a936c..2525a936c 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_pmc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_pmc.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_port.h b/nuttx/arch/arm/src/kinetis/kinetis_port.h index 7472af8bc..7472af8bc 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_port.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_port.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_sim.h b/nuttx/arch/arm/src/kinetis/kinetis_sim.h index 47dcf6320..47dcf6320 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_sim.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_sim.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_smc.h b/nuttx/arch/arm/src/kinetis/kinetis_smc.h index b596164b0..b596164b0 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_smc.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_smc.h diff --git a/nuttx/arch/arm/src/kinetis/kinetis_uart.h b/nuttx/arch/arm/src/kinetis/kinetis_uart.h index af28dcbfc..af28dcbfc 100755..100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_uart.h +++ b/nuttx/arch/arm/src/kinetis/kinetis_uart.h |