diff options
Diffstat (limited to 'nuttx/configs/stm3220g-eval/dhcpd')
-rw-r--r-- | nuttx/configs/stm3220g-eval/dhcpd/defconfig | 12 | ||||
-rw-r--r-- | nuttx/configs/stm3220g-eval/dhcpd/ld.script | 3 |
2 files changed, 2 insertions, 13 deletions
diff --git a/nuttx/configs/stm3220g-eval/dhcpd/defconfig b/nuttx/configs/stm3220g-eval/dhcpd/defconfig index a054711c6..192628a5d 100644 --- a/nuttx/configs/stm3220g-eval/dhcpd/defconfig +++ b/nuttx/configs/stm3220g-eval/dhcpd/defconfig @@ -64,7 +64,7 @@ # CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that # cause a 100 second delay during boot-up. This 100 second delay # serves no purpose other than it allows you to calibrate -# CONFIG_BOARD_LOOPSPERMSEC. You simply use a stop watch to measure +# CONFIG_BOARD_LOOPSPERMSEC. You simply use a stop watch to measure # the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until # the delay actually is 100 seconds. # CONFIG_ARCH_DMA - Support DMA initialization @@ -118,15 +118,6 @@ CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n CONFIG_STM32_JTAG_SW_ENABLE=n # -# On-chip CCM SRAM configuration -# -# CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP. You would need -# to do this if DMA is enabled to prevent non-DMA-able CCM memory from -# being a part of the stack. -# -CONFIG_STM32_CCMEXCLUDE=y - -# # On-board FSMC SRAM configuration # # CONFIG_STM32_FSMC - Required. See below @@ -148,7 +139,6 @@ CONFIG_HEAP2_END=(0x64000000+(2*1024*1024)) # AHB1: CONFIG_STM32_CRC=n CONFIG_STM32_BKPSRAM=n -CONFIG_STM32_CCMDATARAM=n CONFIG_STM32_DMA1=n CONFIG_STM32_DMA2=n CONFIG_STM32_ETHMAC=y diff --git a/nuttx/configs/stm3220g-eval/dhcpd/ld.script b/nuttx/configs/stm3220g-eval/dhcpd/ld.script index 2603253c8..a264f2442 100644 --- a/nuttx/configs/stm3220g-eval/dhcpd/ld.script +++ b/nuttx/configs/stm3220g-eval/dhcpd/ld.script @@ -34,11 +34,10 @@ ****************************************************************************/ /* The STM32F207IGH6U has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: + * 128Kb of SRAM. SRAM is split up into two blocks: * * 1) 112Kb of SRAM beginning at address 0x2000:0000 * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 * * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 * where the code expects to begin execution by jumping to the entry point in |