diff options
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/ChangeLog | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/chip/k25z128_pinmux.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_gpio.h | 628 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_memorymap.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_clockconfig.c | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_clockconfig.h | 87 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_dma.h | 231 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_gpio.c | 392 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_gpio.h | 342 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_internal.h | 775 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_irq.h | 16 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_lowputc.c | 3 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_lowputc.h | 44 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_serial.c | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_spi.h | 142 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/kl/kl_start.c | 3 | ||||
| -rw-r--r-- | nuttx/configs/freedom-kl25z/src/freedom-kl25z.h | 6 | ||||
| -rw-r--r-- | nuttx/configs/freedom-kl25z/src/kl_led.c | 8 |
18 files changed, 1038 insertions, 1649 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 119d77280..8b8c3152d 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4661,3 +4661,5 @@ (2013-5-2). * drivers/mtd/mtd_partition.c: Fix a few bugs and add support for the (option) byte write method (2013-5-3). + * arch/arm/src/kl: Repartitioning of definitions in headef files + from Alan Carvalho de Assis (2013-5-3). diff --git a/nuttx/arch/arm/src/kl/chip/k25z128_pinmux.h b/nuttx/arch/arm/src/kl/chip/k25z128_pinmux.h index e11e0c8a6..597b55581 100644 --- a/nuttx/arch/arm/src/kl/chip/k25z128_pinmux.h +++ b/nuttx/arch/arm/src/kl/chip/k25z128_pinmux.h @@ -312,7 +312,7 @@ #define PIN_I2C0_SDA_4 (PIN_ALT5 | PIN_PORTE | PIN25) #define PIN_CMP0_IN5 (PIN_ANALOG | PIN_PORTE | PIN29) -#define PIN_ADC0_SE4A (PIN_ANALOG | PIN_PORTE | PIN29) +#define PIN_ADC0_SE4B (PIN_ANALOG | PIN_PORTE | PIN29) #define PIN_TPM0_CH2_4 (PIN_ALT3 | PIN_PORTE | PIN29) #define PIN_TPM_CLKIN0_4 (PIN_ALT4 | PIN_PORTE | PIN29) diff --git a/nuttx/arch/arm/src/kl/chip/kl_gpio.h b/nuttx/arch/arm/src/kl/chip/kl_gpio.h index 64b1cad4b..997e1d1ce 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_gpio.h +++ b/nuttx/arch/arm/src/kl/chip/kl_gpio.h @@ -1,5 +1,5 @@ -/******************************************************************************************** - * arch/arm/src/nuc1xx/chip/nuc_gpio.h +/************************************************************************************ + * arch/arm/src/kl/chip/kl_gpio.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -31,526 +31,130 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ************************************************************************************/ #ifndef __ARCH_ARM_SRC_KL_CHIP_KL_GPIO_H #define __ARCH_ARM_SRC_KL_CHIP_KL_GPIO_H -/******************************************************************************************** +/************************************************************************************ * Included Files - ********************************************************************************************/ - -#include <nuttx/config.h> + ************************************************************************************/ #include "chip.h" -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ -/* Register offsets *************************************************************************/ - -#define KL_GPIO_PORTA 0 -#define KL_GPIO_PORTB 1 -#define KL_GPIO_PORTC 2 -#define KL_GPIO_PORTD 3 -#define KL_GPIO_PORTE 4 - -#define KL_GPIO_NPORTS 5 - -/* GPIO control registers */ - -#define KL_GPIO_CTRL_OFFSET(n) (0x0000 + ((n) << 6)) -#define KL_GPIOA_CTRL_OFFSET (0x0000 + ((KL_GPIO_PORTA) << 6)) -#define KL_GPIOB_CTRL_OFFSET (0x0000 + ((KL_GPIO_PORTB) << 6)) -#define KL_GPIOC_CTRL_OFFSET (0x0000 + ((KL_GPIO_PORTC) << 6)) -#define KL_GPIOD_CTRL_OFFSET (0x0000 + ((KL_GPIO_PORTD) << 6)) -#define KL_GPIOE_CTRL_OFFSET (0x0000 + ((KL_GPIO_PORTE) << 6)) - -#define KL_GPIO_PMD_OFFSET 0x0000 /* GPIO port pin I/O mode control */ -#define KL_GPIO_OFFD_OFFSET 0x0004 /* GPIO port pin digital input path disable control */ -#define KL_GPIO_DOUT_OFFSET 0x0008 /* GPIO port data output value */ -#define KL_GPIO_DMASK_OFFSET 0x000c /* GPIO port data output write mask */ -#define KL_GPIO_PIN_OFFSET 0x0010 /* GPIO port pin value */ -#define KL_GPIO_DBEN_OFFSET 0x0014 /* GPIO port de-bounce enable */ -#define KL_GPIO_IMD_OFFSET 0x0018 /* GPIO port interrupt mode control */ -#define KL_GPIO_IEN_OFFSET 0x001c /* GPIO port interrupt enable */ -#define KL_GPIO_ISRC_OFFSET 0x0020 /* GPIO port interrupt source flag */ - -/* GPIO port A control registers */ - -#define KL_GPIOA_PMD_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_PMD_OFFSET) -#define KL_GPIOA_OFFD_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_OFFD_OFFSET) -#define KL_GPIOA_DOUT_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_DOUT_OFFSET) -#define KL_GPIOA_DMASK_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_DMASK_OFFSET) -#define KL_GPIOA_PIN_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_PIN_OFFSET) -#define KL_GPIOA_DBEN_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_DBEN_OFFSET) -#define KL_GPIOA_IMD_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_IMD_OFFSET) -#define KL_GPIOA_IEN_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_IEN_OFFSET) -#define KL_GPIOA_ISRC_OFFSET (KL_GPIOA_CTRL_OFFSET+KL_GPIO_ISRC_OFFSET) - -/* GPIO port B control registers */ - -#define KL_GPIOB_PMD_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_PMD_OFFSET) -#define KL_GPIOB_OFFD_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_OFFD_OFFSET) -#define KL_GPIOB_DOUT_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_DOUT_OFFSET) -#define KL_GPIOB_DMASK_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_DMASK_OFFSET) -#define KL_GPIOB_PIN_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_PIN_OFFSET) -#define KL_GPIOB_DBEN_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_DBEN_OFFSET) -#define KL_GPIOB_IMD_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_IMD_OFFSET) -#define KL_GPIOB_IEN_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_IEN_OFFSET) -#define KL_GPIOB_ISRC_OFFSET (KL_GPIOB_CTRL_OFFSET+KL_GPIO_ISRC_OFFSET) - -/* GPIO port C control registers */ - -#define KL_GPIOC_PMD_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_PMD_OFFSET) -#define KL_GPIOC_OFFD_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_OFFD_OFFSET) -#define KL_GPIOC_DOUT_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_DOUT_OFFSET) -#define KL_GPIOC_DMASK_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_DMASK_OFFSET) -#define KL_GPIOC_PIN_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_PIN_OFFSET) -#define KL_GPIOC_DBEN_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_DBEN_OFFSET) -#define KL_GPIOC_IMD_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_IMD_OFFSET) -#define KL_GPIOC_IEN_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_IEN_OFFSET) -#define KL_GPIOC_ISRC_OFFSET (KL_GPIOC_CTRL_OFFSET+KL_GPIO_ISRC_OFFSET) - -/* GPIO port D control registers */ - -#define KL_GPIOD_PMD_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_PMD_OFFSET) -#define KL_GPIOD_OFFD_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_OFFD_OFFSET) -#define KL_GPIOD_DOUT_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_DOUT_OFFSET) -#define KL_GPIOD_DMASK_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_DMASK_OFFSET) -#define KL_GPIOD_PIN_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_PIN_OFFSET) -#define KL_GPIOD_DBEN_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_DBEN_OFFSET) -#define KL_GPIOD_IMD_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_IMD_OFFSET) -#define KL_GPIOD_IEN_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_IEN_OFFSET) -#define KL_GPIOD_ISRC_OFFSET (KL_GPIOD_CTRL_OFFSET+KL_GPIO_ISRC_OFFSET) - -/* GPIO port E control registers */ - -#define KL_GPIOE_PMD_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_PMD_OFFSET) -#define KL_GPIOE_OFFD_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_OFFD_OFFSET) -#define KL_GPIOE_DOUT_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_DOUT_OFFSET) -#define KL_GPIOE_DMASK_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_DMASK_OFFSET) -#define KL_GPIOE_PIN_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_PIN_OFFSET) -#define KL_GPIOE_DBEN_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_DBEN_OFFSET) -#define KL_GPIOE_IMD_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_IMD_OFFSET) -#define KL_GPIOE_IEN_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_IEN_OFFSET) -#define KL_GPIOE_ISRC_OFFSET (KL_GPIOE_CTRL_OFFSET+KL_GPIO_ISRC_OFFSET) - -/* Debounce control registers */ - -#define KL_GPIO_DBNCECON_OFFSEt 0x0180 /* De-bounce cycle control register */ - -/* GPIO port data I/O register offsets */ - -#define KL_PORT_DATAIO_OFFSET(p) (0x0200 + ((p)<< 6)) -# define KL_PORTA_DATAIO_OFFSET (0x0200 + ((KL_GPIO_PORTA) << 6)) -# define KL_PORTB_DATAIO_OFFSET (0x0200 + ((KL_GPIO_PORTB) << 6)) -# define KL_PORTC_DATAIO_OFFSET (0x0200 + ((KL_GPIO_PORTC) << 6)) -# define KL_PORTD_DATAIO_OFFSET (0x0200 + ((KL_GPIO_PORTD) << 6)) -# define KL_PORTE_DATAIO_OFFSET (0x0200 + ((KL_GPIO_PORTE) << 6)) - -/* GPIO port pin data I/O register offsets */ - -#define KL_PORT_PIN_OFFSET(n) ((n) << 2) -# define KL_PORT_PIN0_OFFSET (0 << 2) -# define KL_PORT_PIN1_OFFSET (1 << 2) -# define KL_PORT_PIN2_OFFSET (2 << 2) -# define KL_PORT_PIN3_OFFSET (3 << 2) -# define KL_PORT_PIN4_OFFSET (4 << 2) -# define KL_PORT_PIN5_OFFSET (5 << 2) -# define KL_PORT_PIN6_OFFSET (16 << 2) -# define KL_PORT_PIN7_OFFSET (17 << 2) -# define KL_PORT_PIN8_OFFSET (18 << 2) -# define KL_PORT_PIN9_OFFSET (19 << 2) -# define KL_PORT_PIN10_OFFSET (10 << 2) -# define KL_PORT_PIN11_OFFSET (11 << 2) -# define KL_PORT_PIN12_OFFSET (12 << 2) -# define KL_PORT_PIN13_OFFSET (13 << 2) -# define KL_PORT_PIN14_OFFSET (14 << 2) -# define KL_PORT_PIN15_OFFSET (15 << 2) - -#define KL_PORT_PDIO_OFFSET(p,n) (KL_PORT_DATAIO_OFFSET(p)+KL_PORT_PIN_OFFSET(n)) - -/* GPIO PA Pin Data Input/Output */ - -#define KL_PORTA_PDIO_OFFSET(n) (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN_OFFSET(n)) -# define KL_PA1_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA2_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA3_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA4_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA5_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA6_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA7_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA8_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA9_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA10_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA11_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA12_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA13_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA14_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PA15_PDIO_OFFSET (KL_PORTA_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) - -/* GPIO PB Pin Data Input/Output */ - -#define KL_PORTB_PDIO_OFFSET(n) (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN_OFFSET(n)) -# define KL_PB1_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB2_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB3_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB4_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB5_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB6_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB7_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB8_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB9_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB10_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB11_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB12_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB13_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB14_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PB15_PDIO_OFFSET (KL_PORTB_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) - -/* GPIO PC Pin Data Input/Output */ - -#define KL_PORTC_PDIO_OFFSET(n) (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN_OFFSET(n)) -# define KL_PC1_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC2_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC3_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC4_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC5_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC6_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC7_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC8_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC9_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC10_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC11_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC12_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC13_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC14_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PC15_PDIO_OFFSET (KL_PORTC_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) - -/* GPIO PD Pin Data Input/Output */ - -#define KL_PORTD_PDIO_OFFSET(n) (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN_OFFSET(n)) -# define KL_PD1_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD2_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD3_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD4_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD5_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD6_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD7_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD8_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD9_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD10_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD11_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD12_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD13_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD14_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) -# define KL_PD15_PDIO_OFFSET (KL_PORTD_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) - -/* GPIO PE Pin Data Input/Output */ - -#define KL_PORTE_PDIO_OFFSET(n) (KL_PORTE_DATAIO_OFFSET+KL_PORT_PIN_OFFSET(n)) -# define KL_PE5_PDIO_OFFSET (KL_PORTE_DATAIO_OFFSET+KL_PORT_PIN0_OFFSET) - -/* Register addresses ***********************************************************************/ - -/* GPIO control registers */ - -#define KL_GPIO_CTRL_BASE(n) (KL_GPIO_BASE+KL_GPIO_CTRL_OFFSET(n)) -#define KL_GPIOA_CTRL_BASE (KL_GPIO_BASE+KL_GPIOA_CTRL_OFFSET) -#define KL_GPIOB_CTRL_BASE (KL_GPIO_BASE+KL_GPIOB_CTRL_OFFSET) -#define KL_GPIOC_CTRL_BASE (KL_GPIO_BASE+KL_GPIOC_CTRL_OFFSET) -#define KL_GPIOD_CTRL_BASE (KL_GPIO_BASE+KL_GPIOD_CTRL_OFFSET) -#define KL_GPIOE_CTRL_BASE (KL_GPIO_BASE+KL_GPIOE_CTRL_OFFSET) - -/* GPIO port A control registers */ - -#define KL_GPIOA_PMD (KL_GPIO_BASE+KL_GPIOA_PMD_OFFSET) -#define KL_GPIOA_OFFD (KL_GPIO_BASE+KL_GPIOA_OFFD_OFFSET) -#define KL_GPIOA_DOUT (KL_GPIO_BASE+KL_GPIOA_DOUT_OFFSET) -#define KL_GPIOA_DMASK (KL_GPIO_BASE+KL_GPIOA_DMASK_OFFSET) -#define KL_GPIOA_PIN (KL_GPIO_BASE+KL_GPIOA_PIN_OFFSET) -#define KL_GPIOA_DBEN (KL_GPIO_BASE+KL_GPIOA_DBEN_OFFSET) -#define KL_GPIOA_IMD (KL_GPIO_BASE+KL_GPIOA_IMD_OFFSET) -#define KL_GPIOA_IEN (KL_GPIO_BASE+KL_GPIOA_IEN_OFFSET) -#define KL_GPIOA_ISRC (KL_GPIO_BASE+KL_GPIOA_ISRC_OFFSET) - -/* GPIO port B control registers */ - -#define KL_GPIOB_PMD (KL_GPIO_BASE+KL_GPIOB_PMD_OFFSET) -#define KL_GPIOB_OFFD (KL_GPIO_BASE+KL_GPIOB_OFFD_OFFSET) -#define KL_GPIOB_DOUT (KL_GPIO_BASE+KL_GPIOB_DOUT_OFFSET) -#define KL_GPIOB_DMASK (KL_GPIO_BASE+KL_GPIOB_DMASK_OFFSET) -#define KL_GPIOB_PIN (KL_GPIO_BASE+KL_GPIOB_PIN_OFFSET) -#define KL_GPIOB_DBEN (KL_GPIO_BASE+KL_GPIOB_DBEN_OFFSET) -#define KL_GPIOB_IMD (KL_GPIO_BASE+KL_GPIOB_IMD_OFFSET) -#define KL_GPIOB_IEN (KL_GPIO_BASE+KL_GPIOB_IEN_OFFSET) -#define KL_GPIOB_ISRC (KL_GPIO_BASE+KL_GPIOB_ISRC_OFFSET) - -/* GPIO port C control registers */ - -#define KL_GPIOC_PMD (KL_GPIO_BASE+KL_GPIOC_PMD_OFFSET) -#define KL_GPIOC_OFFD (KL_GPIO_BASE+KL_GPIOC_OFFD_OFFSET) -#define KL_GPIOC_DOUT (KL_GPIO_BASE+KL_GPIOC_DOUT_OFFSET) -#define KL_GPIOC_DMASK (KL_GPIO_BASE+KL_GPIOC_DMASK_OFFSET) -#define KL_GPIOC_PIN (KL_GPIO_BASE+KL_GPIOC_PIN_OFFSET) -#define KL_GPIOC_DBEN (KL_GPIO_BASE+KL_GPIOC_DBEN_OFFSET) -#define KL_GPIOC_IMD (KL_GPIO_BASE+KL_GPIOC_IMD_OFFSET) -#define KL_GPIOC_IEN (KL_GPIO_BASE+KL_GPIOC_IEN_OFFSET) -#define KL_GPIOC_ISRC (KL_GPIO_BASE+KL_GPIOC_ISRC_OFFSET) - -/* GPIO port D control registers */ - -#define KL_GPIOD_PMD (KL_GPIO_BASE+KL_GPIOD_PMD_OFFSET) -#define KL_GPIOD_OFFD (KL_GPIO_BASE+KL_GPIOD_OFFD_OFFSET) -#define KL_GPIOD_DOUT (KL_GPIO_BASE+KL_GPIOD_DOUT_OFFSET) -#define KL_GPIOD_DMASK (KL_GPIO_BASE+KL_GPIOD_DMASK_OFFSET) -#define KL_GPIOD_PIN (KL_GPIO_BASE+KL_GPIOD_PIN_OFFSET) -#define KL_GPIOD_DBEN (KL_GPIO_BASE+KL_GPIOD_DBEN_OFFSET) -#define KL_GPIOD_IMD (KL_GPIO_BASE+KL_GPIOD_IMD_OFFSET) -#define KL_GPIOD_IEN (KL_GPIO_BASE+KL_GPIOD_IEN_OFFSET) -#define KL_GPIOD_ISRC (KL_GPIO_BASE+KL_GPIOD_ISRC_OFFSET) - -/* GPIO port E control registers */ - -#define KL_GPIOE_PMD (KL_GPIO_BASE+KL_GPIOE_PMD_OFFSET) -#define KL_GPIOE_OFFD (KL_GPIO_BASE+KL_GPIOE_OFFD_OFFSET) -#define KL_GPIOE_DOUT (KL_GPIO_BASE+KL_GPIOE_DOUT_OFFSET) -#define KL_GPIOE_DMASK (KL_GPIO_BASE+KL_GPIOE_DMASK_OFFSET) -#define KL_GPIOE_PIN (KL_GPIO_BASE+KL_GPIOE_PIN_OFFSET) -#define KL_GPIOE_DBEN (KL_GPIO_BASE+KL_GPIOE_DBEN_OFFSET) -#define KL_GPIOE_IMD (KL_GPIO_BASE+KL_GPIOE_IMD_OFFSET) -#define KL_GPIOE_IEN (KL_GPIO_BASE+KL_GPIOE_IEN_OFFSET) -#define KL_GPIOE_ISRC (KL_GPIO_BASE+KL_GPIOE_ISRC_OFFSET) - -/* Debounce control registers */ - -#define KL_GPIO_DBNCECON (KL_GPIO_BASE+KL_GPIO_DBNCECON_OFFSET) - -/* GPIO port data I/O register offsets */ - -#define KL_PORT_DATAIO_BASE(p) (KL_GPIO_BASE+KL_PORT_DATAIO_OFFSET(p)) -# define KL_PORTA_DATAIO_BASE (KL_GPIO_BASE+KL_PORTA_DATAIO_OFFSET) -# define KL_PORTB_DATAIO_BASE (KL_GPIO_BASE+KL_PORTB_DATAIO_OFFSET) -# define KL_PORTC_DATAIO_BASE (KL_GPIO_BASE+KL_PORTC_DATAIO_OFFSET) -# define KL_PORTD_DATAIO_BASE (KL_GPIO_BASE+KL_PORTD_DATAIO_OFFSET) -# define KL_PORTE_DATAIO_BASE (KL_GPIO_BASE+KL_PORTE_DATAIO_OFFSET) - -#define KL_PORT_PDIO(p,n) (KL_GPIO_BASE+KL_PORT_PDIO_OFFSET(p,n)) - -/* GPIO PA Pin Data Input/Output */ - -#define KL_PORTA_PDIO(n) (KL_GPIO_BASE+KL_PORTA_PDIO_OFFSET(n)) -# define KL_PA1_PDIO (KL_GPIO_BASE+KL_PA1_PDIO_OFFSET) -# define KL_PA2_PDIO (KL_GPIO_BASE+KL_PA2_PDIO_OFFSET) -# define KL_PA3_PDIO (KL_GPIO_BASE+KL_PA3_PDIO_OFFSET) -# define KL_PA4_PDIO (KL_GPIO_BASE+KL_PA4_PDIO_OFFSET) -# define KL_PA5_PDIO (KL_GPIO_BASE+KL_PA5_PDIO_OFFSET) -# define KL_PA6_PDIO (KL_GPIO_BASE+KL_PA6_PDIO_OFFSET) -# define KL_PA7_PDIO (KL_GPIO_BASE+KL_PA7_PDIO_OFFSET) -# define KL_PA8_PDIO (KL_GPIO_BASE+KL_PA8_PDIO_OFFSET) -# define KL_PA9_PDIO (KL_GPIO_BASE+KL_PA9_PDIO_OFFSET) -# define KL_PA10_PDIO (KL_GPIO_BASE+KL_PA10_PDIO_OFFSET) -# define KL_PA11_PDIO (KL_GPIO_BASE+KL_PA11_PDIO_OFFSET) -# define KL_PA12_PDIO (KL_GPIO_BASE+KL_PA12_PDIO_OFFSET) -# define KL_PA13_PDIO (KL_GPIO_BASE+KL_PA13_PDIO_OFFSET) -# define KL_PA14_PDIO (KL_GPIO_BASE+KL_PA14_PDIO_OFFSET) -# define KL_PA15_PDIO (KL_GPIO_BASE+KL_PA15_PDIO_OFFSET) - -/* GPIO PB Pin Data Input/Output */ - -#define KL_PORTB_PDIO(n) (KL_GPIO_BASE+KL_PORTB_PDIO_OFFSET(n)) -# define KL_PB1_PDIO (KL_GPIO_BASE+KL_PB1_PDIO_OFFSET) -# define KL_PB2_PDIO (KL_GPIO_BASE+KL_PB2_PDIO_OFFSET) -# define KL_PB3_PDIO (KL_GPIO_BASE+KL_PB3_PDIO_OFFSET) -# define KL_PB4_PDIO (KL_GPIO_BASE+KL_PB4_PDIO_OFFSET) -# define KL_PB5_PDIO (KL_GPIO_BASE+KL_PB5_PDIO_OFFSET) -# define KL_PB6_PDIO (KL_GPIO_BASE+KL_PB6_PDIO_OFFSET) -# define KL_PB7_PDIO (KL_GPIO_BASE+KL_PB7_PDIO_OFFSET) -# define KL_PB8_PDIO (KL_GPIO_BASE+KL_PB8_PDIO_OFFSET) -# define KL_PB9_PDIO (KL_GPIO_BASE+KL_PB9_PDIO_OFFSET) -# define KL_PB10_PDIO (KL_GPIO_BASE+KL_PB10_PDIO_OFFSET) -# define KL_PB11_PDIO (KL_GPIO_BASE+KL_PB11_PDIO_OFFSET) -# define KL_PB12_PDIO (KL_GPIO_BASE+KL_PB12_PDIO_OFFSET) -# define KL_PB13_PDIO (KL_GPIO_BASE+KL_PB13_PDIO_OFFSET) -# define KL_PB14_PDIO (KL_GPIO_BASE+KL_PB14_PDIO_OFFSET) -# define KL_PB15_PDIO (KL_GPIO_BASE+KL_PB15_PDIO_OFFSET) - -/* GPIO PC Pin Data Input/Output */ - -#define KL_PORTC_PDIO(n) (KL_GPIO_BASE+KL_PORTC_PDIO_OFFSET(n)) -# define KL_PC1_PDIO (KL_GPIO_BASE+KL_PC1_PDIO_OFFSET) -# define KL_PC2_PDIO (KL_GPIO_BASE+KL_PC2_PDIO_OFFSET) -# define KL_PC3_PDIO (KL_GPIO_BASE+KL_PC3_PDIO_OFFSET) -# define KL_PC4_PDIO (KL_GPIO_BASE+KL_PC4_PDIO_OFFSET) -# define KL_PC5_PDIO (KL_GPIO_BASE+KL_PC5_PDIO_OFFSET) -# define KL_PC6_PDIO (KL_GPIO_BASE+KL_PC6_PDIO_OFFSET) -# define KL_PC7_PDIO (KL_GPIO_BASE+KL_PC7_PDIO_OFFSET) -# define KL_PC8_PDIO (KL_GPIO_BASE+KL_PC8_PDIO_OFFSET) -# define KL_PC9_PDIO (KL_GPIO_BASE+KL_PC9_PDIO_OFFSET) -# define KL_PC10_PDIO (KL_GPIO_BASE+KL_PC10_PDIO_OFFSET) -# define KL_PC11_PDIO (KL_GPIO_BASE+KL_PC11_PDIO_OFFSET) -# define KL_PC12_PDIO (KL_GPIO_BASE+KL_PC12_PDIO_OFFSET) -# define KL_PC13_PDIO (KL_GPIO_BASE+KL_PC13_PDIO_OFFSET) -# define KL_PC14_PDIO (KL_GPIO_BASE+KL_PC14_PDIO_OFFSET) -# define KL_PC15_PDIO (KL_GPIO_BASE+KL_PC15_PDIO_OFFSET) - -/* GPIO PD Pin Data Input/Output */ - -#define KL_PORTD_PDIO(n) (KL_GPIO_BASE+KL_PORTD_PDIO_OFFSET(n)) -# define KL_PD1_PDIO (KL_GPIO_BASE+KL_PD1_PDIO_OFFSET) -# define KL_PD2_PDIO (KL_GPIO_BASE+KL_PD2_PDIO_OFFSET) -# define KL_PD3_PDIO (KL_GPIO_BASE+KL_PD3_PDIO_OFFSET) -# define KL_PD4_PDIO (KL_GPIO_BASE+KL_PD4_PDIO_OFFSET) -# define KL_PD5_PDIO (KL_GPIO_BASE+KL_PD5_PDIO_OFFSET) -# define KL_PD6_PDIO (KL_GPIO_BASE+KL_PD6_PDIO_OFFSET) -# define KL_PD7_PDIO (KL_GPIO_BASE+KL_PD7_PDIO_OFFSET) -# define KL_PD8_PDIO (KL_GPIO_BASE+KL_PD8_PDIO_OFFSET) -# define KL_PD9_PDIO (KL_GPIO_BASE+KL_PD9_PDIO_OFFSET) -# define KL_PD10_PDIO (KL_GPIO_BASE+KL_PD10_PDIO_OFFSET) -# define KL_PD11_PDIO (KL_GPIO_BASE+KL_PD11_PDIO_OFFSET) -# define KL_PD12_PDIO (KL_GPIO_BASE+KL_PD12_PDIO_OFFSET) -# define KL_PD13_PDIO (KL_GPIO_BASE+KL_PD13_PDIO_OFFSET) -# define KL_PD14_PDIO (KL_GPIO_BASE+KL_PD14_PDIO_OFFSET) -# define KL_PD15_PDIO (KL_GPIO_BASE+KL_PD15_PDIO_OFFSET) - -/* GPIO PE Pin Data Input/Output */ - -#define KL_PORTE_PDIO(n) (KL_GPIO_BASE+KL_PORTE_PDIO_OFFSET(n)) -# define KL_PE5_PDIO (KL_GPIO_BASE+KL_PE5_PDIO_OFFSET) - -/* Register bit-field definitions ***********************************************************/ - -/* GPIO port pin I/O mode control */ - -#define GPIO_PMD_INPUT 0 /* Input */ -#define GPIO_PMD_OUTPUT 1 /* Push-pull output */ -#define GPIO_PMD_OPENDRAIN 2 /* Open drain output */ -#define GPIO_PMD_BIDI 3 /* Quasi bi-directional */ - -#define GPIO_PMD_SHIFT(n) ((n) << 1) /* Bits 2n-2n+1: GPIOx Pin[n] mode control */ -#define GPIO_PMD_MASK(n) (3 << GPIO_PMD_SHIFT(n)) -# define GPIO_PMD(n,v) ((v) << GPIO_PMD_SHIFT(n)) - -#define GPIO_PMD0_SHIFT (0) /* Bits 0-1: GPIOx Pin0 mode control */ -#define GPIO_PMD0_MASK (3 << GPIO_PMD0_SHIFT) -# define GPIO_PMD0(v) ((v) << GPIO_PMD0_SHIFT) -#define GPIO_PMD1_SHIFT (2) /* Bits 2-3: GPIOx Pin1 mode control */ -#define GPIO_PMD1_MASK (3 << GPIO_PMD1_SHIFT) -# define GPIO_PMD1(v) ((v) << GPIO_PMD1_SHIFT) -#define GPIO_PMD2_SHIFT (4) /* Bits 4-5: GPIOx Pin2 mode control */ -#define GPIO_PMD2_MASK (3 << GPIO_PMD2_SHIFT) -# define GPIO_PMD2(v) ((v) << GPIO_PMD2_SHIFT) -#define GPIO_PMD3_SHIFT (6) /* Bits 6-7: GPIOx Pin3 mode control */ -#define GPIO_PMD3_MASK (3 << GPIO_PMD3_SHIFT) -# define GPIO_PMD3(v) ((v) << GPIO_PMD3_SHIFT) -#define GPIO_PMD4_SHIFT (8) /* Bits 8-9: GPIOx Pin4 mode control */ -#define GPIO_PMD4_MASK (3 << GPIO_PMD4_SHIFT) -# define GPIO_PMD4(v) ((v) << GPIO_PMD4_SHIFT) -#define GPIO_PMD5_SHIFT (10) /* Bits 10-11: GPIOx Pin5 mode control */ -#define GPIO_PMD5_MASK (3 << GPIO_PMD5_SHIFT) -# define GPIO_PMD5(v) ((v) << GPIO_PMD5_SHIFT) -#define GPIO_PMD6_SHIFT (12) /* Bits 12-13: GPIOx Pin6 mode control */ -#define GPIO_PMD6_MASK (3 << GPIO_PMD6_SHIFT) -# define GPIO_PMD6(v) ((v) << GPIO_PMD6_SHIFT) -#define GPIO_PMD7_SHIFT (14) /* Bits 14-15: GPIOx Pin7 mode control */ -#define GPIO_PMD7_MASK (3 << GPIO_PMD7_SHIFT) -# define GPIO_PMD7(v) ((v) << GPIO_PMD7_SHIFT) -#define GPIO_PMD8_SHIFT (16) /* Bits 16-17: GPIOx Pin8 mode control */ -#define GPIO_PMD8_MASK (3 << GPIO_PMD8_SHIFT) -# define GPIO_PMD8(v) ((v) << GPIO_PMD8_SHIFT) -#define GPIO_PMD9_SHIFT (18) /* Bits 18-19: GPIOx Pin9 mode control */ -#define GPIO_PMD9_MASK (3 << GPIO_PMD9_SHIFT) -# define GPIO_PMD9(v) ((v) << GPIO_PMD9_SHIFT) -#define GPIO_PMD10_SHIFT (20) /* Bits 20-21: GPIOx Pin0 mode control */ -#define GPIO_PMD10_MASK (3 << GPIO_PMD10_SHIFT) -# define GPIO_PMD10(v) ((v) << GPIO_PMD10_SHIFT) -#define GPIO_PMD11_SHIFT (22) /* Bits 22-23: GPIOx Pin1 mode control */ -#define GPIO_PMD11_MASK (3 << GPIO_PMD11_SHIFT) -# define GPIO_PMD11(v) ((v) << GPIO_PMD11_SHIFT) -#define GPIO_PMD12_SHIFT (24) /* Bits 24-25: GPIOx Pin2 mode control */ -#define GPIO_PMD12_MASK (3 << GPIO_PMD12_SHIFT) -# define GPIO_PMD12(v) ((v) << GPIO_PMD12_SHIFT) -#define GPIO_PMD13_SHIFT (26) /* Bits 26-27: GPIOx Pin3 mode control */ -#define GPIO_PMD13_MASK (3 << GPIO_PMD13_SHIFT) -# define GPIO_PMD13(v) ((v) << GPIO_PMD13_SHIFT) -#define GPIO_PMD14_SHIFT (28) /* Bits 28-29: GPIOx Pin4 mode control */ -#define GPIO_PMD14_MASK (3 << GPIO_PMD14_SHIFT) -# define GPIO_PMD14(v) ((v) << GPIO_PMD14_SHIFT) -#define GPIO_PMD15_SHIFT (30) /* Bits 30-31: GPIOx Pin5 mode control */ -#define GPIO_PMD15_MASK (3 << GPIO_PMD15_SHIFT) -# define GPIO_PMD15(v) ((v) << GPIO_PMD15_SHIFT) - -/* GPIO port pin digital input path disable control */ - -#define GPIO_OFFD(n) (1 << (n)) /* Bit n: GPIOx Pin[n] digital input path disable control */ - -/* GPIO port data output value */ - -#define GPIO_DOUT(n) (1 << (n)) /* Bit n: GPIOx Pin[n] output value */ - -/* GPIO port data output write mask */ - -#define GPIO_DMASK(n) (1 << (n)) /* Bit n: GPIOx Pin[n] data output write mask */ - -/* GPIO port pin value */ - -#define GPIO_PIN(n) (1 << (n)) /* Bit n: GPIOx Pin[n] pin value */ - -/* GPIO port de-bounce enable */ - -#define GPIO_DBEN(n) (1 << (n)) /* Bit n: GPIOx Pin[n] input signal de-bounce enable */ - -/* GPIO port interrupt mode control */ - -#define GPIO_IMD(n) (1 << (n)) /* Bit n: GPIOx Pin[n] edge/level detection interrupt control */ - -/* GPIO port interrupt enable */ - -#define GPIO_IF_EN(n) (1 << (n)) /* Bit n: GPIOx Pin[n] interrupt enable low/falling */ -#define GPIO_IR_EN(n) (1 << ((n)+16)) /* Bit n: GPIOx Pin[n] interrupt enable high/rising */ - -/* GPIO port interrupt source flag */ - -#define GPIO_ISRC(n) (1 << (n)) /* Bit n: GPIOx Pin[n] interrupt source flag */ - -/* De-bounce cycle control register */ - -#define GPIO_DBNCECON_DBCLKSEL_SHIFT (0) /* Bits 0-3: De-bounce cycling count selection */ -#define GPIO_DBNCECON_DBCLKSEL_MASK (15 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_1 (0 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_2 (1 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_4 (2 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_8 (3 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_16 (4 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_32 (5 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_64 (6 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_128 (7 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_256 (8 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_512 (9 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_1024 (10 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_2048 (11 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_4096 (12 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_8102 (13 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_16384 (14 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -# define GPIO_DBNCECON_DBCLKSEL_32768 (15 << GPIO_DBNCECON_DBCLKSEL_SHIFT) -#define GPIO_DBNCECON_DBCLKSRC (1 << 4) /* Bit 4: De-bounce counter clock source selection */ -#define GPIO_DBNCECON_ICLK_ON (1 << 5) /* Bit 5: Interrupt clock on mode */ - -/* GPIO port data I/O registers */ - -#define PORT_MASK (1) /* Bit 0: GPIOx Pin[n] data I/O */ - -/******************************************************************************************** +/************************************************************************************ + * Pre-processorDefinitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define KL_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output Register */ +#define KL_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output Register */ +#define KL_GPIO_PCOR_OFFSET 0x0008 /* Port Clear Output Register */ +#define KL_GPIO_PTOR_OFFSET 0x000c /* Port Toggle Output Register */ +#define KL_GPIO_PDIR_OFFSET 0x0010 /* Port Data Input Register */ +#define KL_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction Register */ + +/* Register Addresses ***************************************************************/ + +#define KL_GPIO_PDOR(n) (KL_GPIO_BASE(n)+KL_GPIO_PDOR_OFFSET) +#define KL_GPIO_PSOR(n) (KL_GPIO_BASE(n)+KL_GPIO_PSOR_OFFSET) +#define KL_GPIO_PCOR(n) (KL_GPIO_BASE(n)+KL_GPIO_PCOR_OFFSET) +#define KL_GPIO_PTOR(n) (KL_GPIO_BASE(n)+KL_GPIO_PTOR_OFFSET) +#define KL_GPIO_PDIR(n) (KL_GPIO_BASE(n)+KL_GPIO_PDIR_OFFSET) +#define KL_GPIO_PDDR(n) (KL_GPIO_BASE(n)+KL_GPIO_PDDR_OFFSET) + +#define KL_GPIOA_PDOR (KL_GPIOA_BASE+KL_GPIO_PDOR_OFFSET) +#define KL_GPIOA_PSOR (KL_GPIOA_BASE+KL_GPIO_PSOR_OFFSET) +#define KL_GPIOA_PCOR (KL_GPIOA_BASE+KL_GPIO_PCOR_OFFSET) +#define KL_GPIOA_PTOR (KL_GPIOA_BASE+KL_GPIO_PTOR_OFFSET) +#define KL_GPIOA_PDIR (KL_GPIOA_BASE+KL_GPIO_PDIR_OFFSET) +#define KL_GPIOA_PDDR (KL_GPIOA_BASE+KL_GPIO_PDDR_OFFSET) + +#define KL_GPIOB_PDOR (KL_GPIOB_BASE+KL_GPIO_PDOR_OFFSET) +#define KL_GPIOB_PSOR (KL_GPIOB_BASE+KL_GPIO_PSOR_OFFSET) +#define KL_GPIOB_PCOR (KL_GPIOB_BASE+KL_GPIO_PCOR_OFFSET) +#define KL_GPIOB_PTOR (KL_GPIOB_BASE+KL_GPIO_PTOR_OFFSET) +#define KL_GPIOB_PDIR (KL_GPIOB_BASE+KL_GPIO_PDIR_OFFSET) +#define KL_GPIOB_PDDR (KL_GPIOB_BASE+KL_GPIO_PDDR_OFFSET) + +#define KL_GPIOC_PDOR (KL_GPIOC_BASE+KL_GPIO_PDOR_OFFSET) +#define KL_GPIOC_PSOR (KL_GPIOC_BASE+KL_GPIO_PSOR_OFFSET) +#define KL_GPIOC_PCOR (KL_GPIOC_BASE+KL_GPIO_PCOR_OFFSET) +#define KL_GPIOC_PTOR (KL_GPIOC_BASE+KL_GPIO_PTOR_OFFSET) +#define KL_GPIOC_PDIR (KL_GPIOC_BASE+KL_GPIO_PDIR_OFFSET) +#define KL_GPIOC_PDDR (KL_GPIOC_BASE+KL_GPIO_PDDR_OFFSET) + +#define KL_GPIOD_PDOR (KL_GPIOD_BASE+KL_GPIO_PDOR_OFFSET) +#define KL_GPIOD_PSOR (KL_GPIOD_BASE+KL_GPIO_PSOR_OFFSET) +#define KL_GPIOD_PCOR (KL_GPIOD_BASE+KL_GPIO_PCOR_OFFSET) +#define KL_GPIOD_PTOR (KL_GPIOD_BASE+KL_GPIO_PTOR_OFFSET) +#define KL_GPIOD_PDIR (KL_GPIOD_BASE+KL_GPIO_PDIR_OFFSET) +#define KL_GPIOD_PDDR (KL_GPIOD_BASE+KL_GPIO_PDDR_OFFSET) + +#define KL_GPIOE_PDOR (KL_GPIOE_BASE+KL_GPIO_PDOR_OFFSET) +#define KL_GPIOE_PSOR (KL_GPIOE_BASE+KL_GPIO_PSOR_OFFSET) +#define KL_GPIOE_PCOR (KL_GPIOE_BASE+KL_GPIO_PCOR_OFFSET) +#define KL_GPIOE_PTOR (KL_GPIOE_BASE+KL_GPIO_PTOR_OFFSET) +#define KL_GPIOE_PDIR (KL_GPIOE_BASE+KL_GPIO_PDIR_OFFSET) +#define KL_GPIOE_PDDR (KL_GPIOE_BASE+KL_GPIO_PDDR_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Port Data Output Register */ + +#define GPIO_PDOR(n) (1 << (n)) + +/* Port Set Output Register */ + +#define GPIO_PSOR(n) (1 << (n)) + +/* Port Clear Output Register */ + +#define GPIO_PCOR(n) (1 << (n)) + +/* Port Toggle Output Register */ + +#define GPIO_PTOR(n) (1 << (n)) + +/* Port Data Input Register */ + +#define GPIO_PDIR(n) (1 << (n)) + +/* Port Data Direction Register */ + +#define GPIO_PDDR(n) (1 << (n)) + +/************************************************************************************ * Public Types - ********************************************************************************************/ + ************************************************************************************/ -/******************************************************************************************** - * Public Data - ********************************************************************************************/ +/************************************************************************************ + * Inline Functions + ************************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +#ifndef __ASSEMBLY__ +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_KL_CHIP_KL_GPIO_H */ diff --git a/nuttx/arch/arm/src/kl/chip/kl_memorymap.h b/nuttx/arch/arm/src/kl/chip/kl_memorymap.h index 6978ae975..60e4542c7 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_memorymap.h +++ b/nuttx/arch/arm/src/kl/chip/kl_memorymap.h @@ -65,7 +65,7 @@ /* 0x20100000 * -0x3fffffff Reserved */ # define KIP_AIPS_BASE 0x40000000 /* -0x4007ffff AIPS Peripherals */ /* 0x40080000 * -0x400fffff Reserved */ -# define KL_GPIO_BASE 0x400ff000 /* -0x400fffff General purpose input/output (GPIO) */ +# define KL_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) /* 0x40100000 * -0x43ffffff Reserved */ # define KL_BME_BASE 0x44000000 /* -0x5fffffff Bit Manipulation Engine (BME) access * to AIPS Peripherals for slots 0-127 */ diff --git a/nuttx/arch/arm/src/kl/kl_clockconfig.c b/nuttx/arch/arm/src/kl/kl_clockconfig.c index b28c20ac2..700e87aa6 100644 --- a/nuttx/arch/arm/src/kl/kl_clockconfig.c +++ b/nuttx/arch/arm/src/kl/kl_clockconfig.c @@ -46,7 +46,7 @@ #include "up_arch.h" #include "chip.h" -#include "kl_internal.h" +#include "kl_gpio.h" #include "chip/kl_mcg.h" #include "chip/kl_sim.h" #include "chip/kl_osc.h" diff --git a/nuttx/arch/arm/src/kl/kl_clockconfig.h b/nuttx/arch/arm/src/kl/kl_clockconfig.h new file mode 100644 index 000000000..1de60d07a --- /dev/null +++ b/nuttx/arch/arm/src/kl/kl_clockconfig.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/kl/kl_gpio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KL_KL_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_KL_KL_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "kl_config.h" + +/**************************************************************************** + * Pre-processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: kl_clockconfig + * + * Description: + * Called to initialize the Kinetis chip. This does whatever setup is + * needed to put the MCU in a usable state. This includes the + * initialization of clocking using the settings in board.h. + * + ****************************************************************************/ + +void kl_clockconfig(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_KL_KL_CLOCKCONFIG_H */ diff --git a/nuttx/arch/arm/src/kl/kl_dma.h b/nuttx/arch/arm/src/kl/kl_dma.h new file mode 100644 index 000000000..1e4860bd3 --- /dev/null +++ b/nuttx/arch/arm/src/kl/kl_dma.h @@ -0,0 +1,231 @@ +/**************************************************************************** + * arch/arm/src/kl/kl_gpio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KL_KL_DMA_H +#define __ARCH_ARM_SRC_KL_KL_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "kl_config.h" + +/**************************************************************************** + * Pre-processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef FAR void *DMA_HANDLE; +typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ + +#ifdef CONFIG_DEBUG_DMA +struct kl_dmaglobalregs_s +{ +#warning "Missing logic" + /* Global Registers */ +}; + +struct kl_dmachanregs_s +{ +#warning "Missing logic" + /* Channel Registers */ +}; + +struct kl_dmaregs_s +{ + /* Global Registers */ + + struct kl_dmaglobalregs_s gbl; + + /* Channel Registers */ + + struct kl_dmachanregs_s ch; +}; +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: kl_dmainitialize + * + * Description: + * Initialize the GPDMA subsystem. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +void kl_dmainitilaize(void); +#endif + +/**************************************************************************** + * Name: kl_dmachannel + * + * Description: + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. + * + * Returned Value: + * One success, this function returns a non-NULL, void* DMA channel + * handle. NULL is returned on any failure. This function can fail only + * if no DMA channel is available. + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +DMA_HANDLE kl_dmachannel(void); +#endif + +/**************************************************************************** + * Name: kl_dmafree + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until kl_dmachannel() is called again to re-gain + * a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +void kl_dmafree(DMA_HANDLE handle); +#endif + +/**************************************************************************** + * Name: kl_dmasetup + * + * Description: + * Configure DMA for one transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +int kl_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, + uint32_t srcaddr, uint32_t destaddr, size_t nbytes); +#endif + +/**************************************************************************** + * Name: kl_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +int kl_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); +#endif + +/**************************************************************************** + * Name: kl_dmastop + * + * Description: + * Cancel the DMA. After kl_dmastop() is called, the DMA channel is + * reset and kl_dmasetup() must be called before kl_dmastart() can be + * called again + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +void kl_dmastop(DMA_HANDLE handle); +#endif + +/**************************************************************************** + * Name: kl_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +#ifdef CONFIG_DEBUG_DMA +void kl_dmasample(DMA_HANDLE handle, struct kl_dmaregs_s *regs); +#else +# define kl_dmasample(handle,regs) +#endif +#endif + +/**************************************************************************** + * Name: kl_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_KL_DMA +#ifdef CONFIG_DEBUG_DMA +void kl_dmadump(DMA_HANDLE handle, const struct kl_dmaregs_s *regs, + const char *msg); +#else +# define kl_dmadump(handle,regs,msg) +#endif +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_KL_KL_DMA_H */ diff --git a/nuttx/arch/arm/src/kl/kl_gpio.c b/nuttx/arch/arm/src/kl/kl_gpio.c index 4062bd6d9..78d49e0c9 100644 --- a/nuttx/arch/arm/src/kl/kl_gpio.c +++ b/nuttx/arch/arm/src/kl/kl_gpio.c @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/arm/src/kl/kl_gpio.c + * arch/arm/src/kl/kl_pin.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -38,17 +38,15 @@ ****************************************************************************/ #include <nuttx/config.h> +#include <arch/board/board.h> -#include <stdint.h> #include <assert.h> -#include <debug.h> +#include <errno.h> -#include <arch/kl/chip.h> +#include <nuttx/arch.h> #include "up_arch.h" - -#include "chip.h" -#include "chip/kl_gpio.h" +#include "up_internal.h" #include "kl_gpio.h" @@ -57,6 +55,10 @@ ****************************************************************************/ /**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** * Private Functions ****************************************************************************/ @@ -68,150 +70,150 @@ * Name: kl_configgpio * * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with kl_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returns: - * OK on success - * ERROR on invalid port, or when pin is locked as ALT function. + * Configure a PIN based on bit-encoded description of the pin. NOTE that + * DMA/interrupts are disabled at the initial PIN configuratin. * ****************************************************************************/ -int kl_configgpio(gpio_cfgset_t cfgset) +int kl_configgpio(uint32_t cfgset) { - uintptr_t base; - uint32_t regaddr; - uint32_t regval; - uint32_t isrc; - uint32_t imd; - uint32_t ien; - uint32_t value; - int port; - int pin; - - /* Decode the port and pin. Use the port number to get the GPIO base - * address. - */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE); - base = KL_GPIO_CTRL_BASE(port); - - /* Set the the GPIO PMD register */ - - regaddr = base + KL_GPIO_PMD_OFFSET; - regval = getreg32(regaddr); - regval &= ~GPIO_PMD_MASK(pin); - - switch (cfgset & GPIO_MODE_MASK) - { - default: - case GPIO_INPUT: /* Input */ - value = GPIO_PMD_INPUT; - break; - - case GPIO_OUTPUT: /* Push-pull output */ - value = GPIO_PMD_OUTPUT; - break; - - case GPIO_OPENDRAIN: /* Open drain output */ - value = GPIO_PMD_OPENDRAIN; - break; - - case GPIO_BIDI: /* Quasi bi-directional */ - value = GPIO_PMD_BIDI; - break; - } - - regval |= GPIO_PMD(pin, value); - putreg32(regval, regaddr); + uintptr_t base; + uint32_t regval; + unsigned int port; + unsigned int pin; + unsigned int mode; - /* Check if we need to disable the digital input path */ + /* Get the port number and pin number */ - regaddr = base + KL_GPIO_OFFD_OFFSET; - regval = getreg32(regaddr); - regval &= ~GPIO_OFFD(pin); + port = (cfgset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; + pin = (cfgset & _PIN_MASK) >> _PIN_SHIFT; - if ((cfgset & GPIO_ANALOG) != 0) + DEBUGASSERT(port < KL_NPORTS); + if (port < KL_NPORTS) { - regval |= GPIO_OFFD(pin); + /* Get the base address of PORT block for this port */ + + base = KL_PORT_BASE(port); + + /* Get the port mode */ + + mode = (cfgset & _PIN_MODE_MASK) >> _PIN_MODE_SHIFT; + + /* Special case analog port mode. In this case, not of the digital + * options are applicable. + */ + + if (mode == _PIN_MODE_ANALOG) + { + /* Set the analog mode with all digital options zeroed */ + + regval = PORT_PCR_MUX_ANALOG | PORT_PCR_IRQC_DISABLED; + putreg32(regval, base + KL_PORT_PCR_OFFSET(pin)); + } + else + { + /* Configure the digital pin options */ + + regval = (mode << PORT_PCR_MUX_SHIFT); + if ((cfgset & _PIN_IO_MASK) == _PIN_INPUT) + { + /* Handle input-only digital options */ + /* Check for pull-up or pull-down */ + + if ((cfgset & _PIN_INPUT_PULLMASK) == _PIN_INPUT_PULLDOWN) + { + regval |= PORT_PCR_PE; + } + else if ((cfgset & _PIN_INPUT_PULLMASK) == _PIN_INPUT_PULLUP) + { + regval |= (PORT_PCR_PE | PORT_PCR_PS); + } + } + else + { + /* Handle output-only digital options */ + /* Check for slow slew rate setting */ + + if ((cfgset & _PIN_OUTPUT_SLEW_MASK) == _PIN_OUTPUT_SLOW) + { + regval |= PORT_PCR_SRE; + } + + /* Check for open drain output */ + + if ((cfgset & _PIN_OUTPUT_OD_MASK) == _PIN_OUTPUT_OPENDRAIN) + { + regval |= PORT_PCR_ODE; + } + + /* Check for high drive output */ + + if ((cfgset & _PIN_OUTPUT_DRIVE_MASK) == _PIN_OUTPUT_HIGHDRIVE) + { + regval |= PORT_PCR_DSE; + } + } + + /* Check for passive filter enable. Passive Filter configuration + * is valid in all digital pin muxing modes. + */ + + if ((cfgset & PIN_PASV_FILTER) != 0) + { + regval |= PORT_PCR_PFE; + } + + /* Set the digital mode with all of the selected options */ + + putreg32(regval, base + KL_PORT_PCR_OFFSET(pin)); + + /* Check for digital filter enable. Digital Filter configuration + * is valid in all digital pin muxing modes. + */ + + regval = getreg32(base + KL_PORT_DFER_OFFSET); + if ((cfgset & PIN_DIG_FILTER) != 0) + { + regval |= (1 << pin); + } + else + { + regval &= ~(1 << pin); + } + putreg32(regval, base + KL_PORT_DFER_OFFSET); + + /* Additional configuration for the case of Alternative 1 (GPIO) modes */ + + if (mode == _PIN_MODE_GPIO) + { + /* Set the GPIO port direction */ + + base = KL_GPIO_BASE(port); + regval = getreg32(base + KL_GPIO_PDDR_OFFSET); + if ((cfgset & _PIN_IO_MASK) == _PIN_INPUT) + { + /* Select GPIO input */ + + regval &= ~(1 << pin); + putreg32(regval, base + KL_GPIO_PDDR_OFFSET); + } + else /* if ((cfgset & _PIN_IO_MASK) == _PIN_OUTPUT) */ + { + /* Select GPIO input */ + + regval |= (1 << pin); + putreg32(regval, base + KL_GPIO_PDDR_OFFSET); + + /* Set the initial value of the GPIO output */ + + kl_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_ONE) != 0)); + } + } + } + + return OK; } - - putreg32(regval, regaddr); - - /* Check if we need to enable debouncing */ - - regaddr = base + KL_GPIO_DBEN_OFFSET; - regval = getreg32(regaddr); - regval &= ~GPIO_DBEN(pin); - - if ((cfgset & GPIO_DEBOUNCE) != 0) - { - regval |= GPIO_DBEN(pin); - } - - putreg32(regval, regaddr); - - /* Configure interrupting pins */ - - isrc = getreg32(base + KL_GPIO_ISRC_OFFSET); - isrc &= ~GPIO_ISRC(pin); - - imd = getreg32(base + KL_GPIO_IMD_OFFSET); - imd &= ~GPIO_IMD(pin); - - ien = getreg32(base + KL_GPIO_IEN_OFFSET); - ien &= ~(GPIO_IF_EN(pin) | GPIO_IR_EN(pin)); - - switch (cfgset & GPIO_INTERRUPT_MASK) - { - case GPIO_INTERRUPT_RISING_EDGE: - isrc |= GPIO_ISRC(pin); - ien |= GPIO_IR_EN(pin); - break; - - case GPIO_INTERRUPT_FALLING_EDGE: - isrc |= GPIO_ISRC(pin); - ien |= GPIO_IF_EN(pin); - break; - - case GPIO_INTERRUPT_BOTH_EDGES: - isrc |= GPIO_ISRC(pin); - ien |= (GPIO_IF_EN(pin) | GPIO_IR_EN(pin)); - break; - - case GPIO_INTERRUPT_HIGH_LEVEL: - isrc |= GPIO_ISRC(pin); - imd |= GPIO_IMD(pin); - ien |= GPIO_IR_EN(pin); - break; - - case GPIO_INTERRUPT_LOW_LEVEL: - isrc |= GPIO_ISRC(pin); - imd |= GPIO_IMD(pin); - ien |= GPIO_IF_EN(pin); - break; - - default: - break; - } - - putreg32(ien, base + KL_GPIO_IEN_OFFSET); - putreg32(imd, base + KL_GPIO_IMD_OFFSET); - putreg32(isrc, base + KL_GPIO_ISRC_OFFSET); - - /* If the pin is an output, set the initial output value */ - - if ((cfgset & GPIO_MODE_MASK) == GPIO_OUTPUT) - { - kl_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); - } - - return 0; + return -EINVAL; } /**************************************************************************** @@ -222,48 +224,38 @@ int kl_configgpio(gpio_cfgset_t cfgset) * ****************************************************************************/ -void kl_gpiowrite(gpio_cfgset_t pinset, bool value) +void kl_gpiowrite(uint32_t pinset, bool value) { -#ifndef KL_LOW - irqstate_t flags; - uintptr_t base; -#endif - int port; - int pin; - - /* Decode the port and pin. Use the port number to get the GPIO base - * address. - */ + uintptr_t base; + unsigned int port; + unsigned int pin; - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + DEBUGASSERT((pinset & _PIN_MODE_MASK) == _PIN_MODE_GPIO); + DEBUGASSERT((pinset & _PIN_IO_MASK) == _PIN_OUTPUT); - DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE); + /* Get the port number and pin number */ - /* Only the low density K25Z100/120 chips support bit-band access to GPIO - * pins. - */ + port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; + pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; -#ifdef KL_LOW - putreg32((uint32_t)value, KL_PORT_PDIO(port, pin)); -#else - /* Get the base address of the GPIO port registers */ - - base = KL_GPIO_CTRL_BASE(port); - - /* Disable interrupts -- the following operations must be atomic */ - - flags = irqsave(); - - /* Allow writing only to the selected pin in the DOUT register */ + DEBUGASSERT(port < KL_NPORTS); + if (port < KL_NPORTS) + { + /* Get the base address of GPIO block for this port */ - putreg32(~(1 << pin), base + KL_GPIO_DMASK_OFFSET); + base = KL_GPIO_BASE(port); - /* Set the pin to the selected value and re-enable interrupts */ + /* Set or clear the output */ - putreg32(((uint32_t)value << pin), base + KL_GPIO_DOUT_OFFSET); - irqrestore(flags); -#endif + if (value) + { + putreg32((1 << pin), base + KL_GPIO_PSOR_OFFSET); + } + else + { + putreg32((1 << pin), base + KL_GPIO_PCOR_OFFSET); + } + } } /**************************************************************************** @@ -274,36 +266,34 @@ void kl_gpiowrite(gpio_cfgset_t pinset, bool value) * ****************************************************************************/ -bool kl_gpioread(gpio_cfgset_t pinset) +bool kl_gpioread(uint32_t pinset) { -#ifndef KL_LOW - uintptr_t base; -#endif - int port; - int pin; - - /* Decode the port and pin. Use the port number to get the GPIO base - * address. - */ + uintptr_t base; + uint32_t regval; + unsigned int port; + unsigned int pin; + bool ret = false; - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + DEBUGASSERT((pinset & _PIN_MODE_MASK) == _PIN_MODE_GPIO); + DEBUGASSERT((pinset & _PIN_IO_MASK) == _PIN_INPUT); - DEBUGASSERT((unsigned)port <= KL_GPIO_PORTE); + /* Get the port number and pin number */ - /* Only the low density K25Z100/120 chips support bit-band access to GPIO - * pins. - */ + port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; + pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; -#ifdef KL_LOW - return (getreg32(KL_PORT_PDIO(port, pin)) & PORT_MASK) != 0; -#else - /* Get the base address of the GPIO port registers */ + DEBUGASSERT(port < KL_NPORTS); + if (port < KL_NPORTS) + { + /* Get the base address of GPIO block for this port */ - base = KL_GPIO_CTRL_BASE(port); + base = KL_GPIO_BASE(port); - /* Return the state of the selected pin */ + /* return the state of the pin */ - return (getreg32(base + KL_GPIO_PIN_OFFSET) & (1 << pin)) != 0; -#endif + regval = getreg32(base + KL_GPIO_PDIR_OFFSET); + ret = ((regval & (1 << pin)) != 0); + } + return ret; } + diff --git a/nuttx/arch/arm/src/kl/kl_gpio.h b/nuttx/arch/arm/src/kl/kl_gpio.h index 02cb0643a..17f947a4f 100644 --- a/nuttx/arch/arm/src/kl/kl_gpio.h +++ b/nuttx/arch/arm/src/kl/kl_gpio.h @@ -42,137 +42,253 @@ #include <nuttx/config.h> -#ifndef __ASSEMBLY__ -# include <stdint.h> -# include <stdbool.h> -#endif +#include <stdbool.h> #include <nuttx/irq.h> -#include "chip.h" +#include "kl_config.h" #include "chip/kl_gpio.h" +#include "chip/kl_port.h" /**************************************************************************** * Pre-processor Declarations ****************************************************************************/ - -/* Bit-encoded input to kl_configgpio() */ - -/* 16-bit Encoding: +/* Bit-encoded input to kl_pinconfig() *****************************************/ +/* General form (32-bits, only 22 bits are unused in the encoding): * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * MMAD III. VPPP BBBB + * oooo mmmv iiii ifd- ---- -ppp ---b bbbb */ -/* GPIO mode: +/* Bits 25-31: 7 bits are used to encode the basic pin configuration: * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * MM.. .... .... .... + * oooo mmm- ---- ---- ---- ---- ---- ---- + * oooommm: + * | `--- mmm: mode + * `------- oooo: options (may be combined) */ -#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ -# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Push-pull output */ -# define GPIO_OPENDRAIN (2 << GPIO_MODE_SHIFT) /* Open drain output */ -# define GPIO_BIDI (3 << GPIO_MODE_SHIFT) /* Quasi bi-directional */ +#define _PIN_MODE_SHIFT (25) /* Bits 25-27: Pin mode */ +#define _PIN_MODE_MASK (7 << _PIN_MODE_SHIFT) +#define _PIN_OPTIONS_SHIFT (28) /* Bits 28-31: Pin mode options */ +#define _PIN_OPTIONS_MASK (15 << _PIN_OPTIONS_SHIFT) -/* GPIO analog: If the pin is an analog input, then it would be necessary to - * disable the digital input - * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * ..A. .... .... .... +/* Port Modes */ + +#define _PIN_MODE_ANALOG (0 << _PIN_MODE_SHIFT) /* 000 Pin Disabled (Analog) */ +#define _PIN_MODE_GPIO (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 (GPIO) */ +#define _PIN_MODE_ALT2 (2 << _PIN_MODE_SHIFT) /* 010 Alternative 2 */ +#define _PIN_MODE_ALT3 (3 << _PIN_MODE_SHIFT) /* 011 Alternative 3 */ +#define _PIN_MODE_ALT4 (4 << _PIN_MODE_SHIFT) /* 100 Alternative 4 */ +#define _PIN_MODE_ALT5 (5 << _PIN_MODE_SHIFT) /* 101 Alternative 5 */ +#define _PIN_MODE_ALT6 (6 << _PIN_MODE_SHIFT) /* 110 Alternative 6 */ +#define _PIN_MODE_ALT7 (7 << _PIN_MODE_SHIFT) /* 111 Alternative 7 */ + +/* Options for all digital modes (Alternatives 1-7). None of the digital + * options apply if the analog mode is selected. */ -#define GPIO_ANALOG (1 << 13) /* Bit 13: Disable digital input */ +#define _PIN_IO_MASK (1 << _PIN_OPTIONS_SHIFT) /* xxx1 Digital input/output mask */ +#define _PIN_INPUT (0 << _PIN_OPTIONS_SHIFT) /* xxx0 Digital input */ +#define _PIN_OUTPUT (1 << _PIN_OPTIONS_SHIFT) /* xxx1 Digital output */ + +#define _PIN_INPUT_PULLMASK (7 << _PIN_OPTIONS_SHIFT) /* x111 Mask for pull-up or -down bits */ +#define _PIN_INPUT_PULLDOWN (2 << _PIN_OPTIONS_SHIFT) /* x010 Input with internal pull-down resistor */ +#define _PIN_INPUT_PULLUP (6 << _PIN_OPTIONS_SHIFT) /* x110 Input with internal pull-up resistor */ + +#define _PIN_OUTPUT_SLEW_MASK (3 << _PIN_OPTIONS_SHIFT) /* xx11 Mask to test for slow slew rate */ +#define _PIN_OUTPUT_FAST (1 << _PIN_OPTIONS_SHIFT) /* xx01 Output with fast slew rate */ +#define _PIN_OUTPUT_SLOW (3 << _PIN_OPTIONS_SHIFT) /* xx11 Output with slow slew rate */ +#define _PIN_OUTPUT_OD_MASK (5 << _PIN_OPTIONS_SHIFT) /* x1x1 Mask to test for open drain */ +#define _PIN_OUTPUT_OPENDRAIN (5 << _PIN_OPTIONS_SHIFT) /* x1x1 Output with open drain enabled */ +#define _PIN_OUTPUT_DRIVE_MASK (9 << _PIN_OPTIONS_SHIFT) /* 1xx1 Mask to test for high drive strengh */ +#define _PIN_OUTPUT_LOWDRIVE (1 << _PIN_OPTIONS_SHIFT) /* 0xx1 Output with low drive strength */ +#define _PIN_OUTPUT_HIGHDRIVE (9 << _PIN_OPTIONS_SHIFT) /* 1xx1 Output with high drive strength */ + +/* End-user pin modes and configurations. Notes: (1) None of the digital options + * are available for the analog mode, (2) digital settings may be combined (OR'ed) + * provided that input-only and output-only options are not intermixed. + */ -/* De-bounce enable: +#define PIN_ANALOG _PIN_MODE_ANALOG + +#define GPIO_INPUT (_PIN_MODE_GPIO | _PIN_INPUT) +#define GPIO_PULLDOWN (_PIN_MODE_GPIO | _PIN_INPUT_PULLDOWN) +#define GPIO_PULLUP (_PIN_MODE_GPIO | _PIN_INPUT_PULLUP) +#define GPIO_OUTPUT (_PIN_MODE_GPIO | _PIN_OUTPUT) +#define GPIO_FAST (_PIN_MODE_GPIO | _PIN_OUTPUT_FAST) +#define GPIO_SLOW (_PIN_MODE_GPIO | _PIN_OUTPUT_SLOW) +#define GPIO_OPENDRAIN (_PIN_MODE_GPIO | _PIN_OUTPUT_LOWDRIVE) +#define GPIO_LOWDRIVE (_PIN_MODE_GPIO | _PIN_OUTPUT_OPENDRAIN) +#define GPIO_HIGHDRIVE (_PIN_MODE_GPIO | _PIN_OUTPUT_HIGHDRIVE) + +#define PIN_ALT2 _PIN_MODE_ALT2 +#define PIN_ALT2_INPUT (_PIN_MODE_ALT2 | _PIN_INPUT) +#define PIN_ALT2_PULLDOWN (_PIN_MODE_ALT2 | _PIN_INPUT_PULLDOWN) +#define PIN_ALT2_PULLUP (_PIN_MODE_ALT2 | _PIN_INPUT_PULLUP) +#define PIN_ALT2_OUTPUT (_PIN_MODE_ALT2 | _PIN_OUTPUT) +#define PIN_ALT2_FAST (_PIN_MODE_ALT2 | _PIN_OUTPUT_FAST) +#define PIN_ALT2_SLOW (_PIN_MODE_ALT2 | _PIN_OUTPUT_SLOW) +#define PIN_ALT2_OPENDRAIN (_PIN_MODE_ALT2 | _PIN_OUTPUT_LOWDRIVE) +#define PIN_ALT2_LOWDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT2_HIGHDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_HIGHDRIVE) + +#define PIN_ALT3 _PIN_MODE_ALT3 +#define PIN_ALT3_INPUT (_PIN_MODE_ALT3 | _PIN_INPUT) +#define PIN_ALT3_PULLDOWN (_PIN_MODE_ALT3 | _PIN_INPUT_PULLDOWN) +#define PIN_ALT3_PULLUP (_PIN_MODE_ALT3 | _PIN_INPUT_PULLUP) +#define PIN_ALT3_OUTPUT (_PIN_MODE_ALT3 | _PIN_OUTPUT) +#define PIN_ALT3_FAST (_PIN_MODE_ALT3 | _PIN_OUTPUT_FAST) +#define PIN_ALT3_SLOW (_PIN_MODE_ALT3 | _PIN_OUTPUT_SLOW) +#define PIN_ALT3_OPENDRAIN (_PIN_MODE_ALT3 | _PIN_OUTPUT_LOWDRIVE) +#define PIN_ALT3_LOWDRIVE (_PIN_MODE_ALT3 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT3_HIGHDRIVE (_PIN_MODE_ALT3 | _PIN_OUTPUT_HIGHDRIVE) + +#define PIN_ALT4 _PIN_MODE_ALT4 +#define PIN_ALT4_INPUT (_PIN_MODE_ALT4 | _PIN_INPUT) +#define PIN_ALT4_PULLDOWN (_PIN_MODE_ALT4 | _PIN_INPUT_PULLDOWN) +#define PIN_ALT4_PULLUP (_PIN_MODE_ALT4 | _PIN_INPUT_PULLUP) +#define PIN_ALT4_OUTPUT (_PIN_MODE_ALT4 | _PIN_OUTPUT) +#define PIN_ALT4_FAST (_PIN_MODE_ALT4 | _PIN_OUTPUT_FAST) +#define PIN_ALT4_SLOW (_PIN_MODE_ALT4 | _PIN_OUTPUT_SLOW) +#define PIN_ALT4_OPENDRAIN (_PIN_MODE_ALT4 | _PIN_OUTPUT_LOWDRIVE) +#define PIN_ALT4_LOWDRIVE (_PIN_MODE_ALT4 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT4_HIGHDRIVE (_PIN_MODE_ALT4 | _PIN_OUTPUT_HIGHDRIVE) + +#define PIN_ALT5 _PIN_MODE_ALT5 +#define PIN_ALT5_INPUT (_PIN_MODE_ALT5 | _PIN_INPUT) +#define PIN_ALT5_PULLDOWN (_PIN_MODE_ALT5 | _PIN_INPUT_PULLDOWN) +#define PIN_ALT5_PULLUP (_PIN_MODE_ALT5 | _PIN_INPUT_PULLUP) +#define PIN_ALT5_OUTPUT (_PIN_MODE_ALT5 | _PIN_OUTPUT) +#define PIN_ALT5_FAST (_PIN_MODE_ALT5 | _PIN_OUTPUT_FAST) +#define PIN_ALT5_SLOW (_PIN_MODE_ALT5 | _PIN_OUTPUT_SLOW) +#define PIN_ALT5_OPENDRAIN (_PIN_MODE_ALT5 | _PIN_OUTPUT_LOWDRIVE) +#define PIN_ALT5_LOWDRIVE (_PIN_MODE_ALT5 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT5_HIGHDRIVE (_PIN_MODE_ALT5 | _PIN_OUTPUT_HIGHDRIVE) + +#define PIN_ALT6 _PIN_MODE_ALT6 +#define PIN_ALT6_INPUT (_PIN_MODE_ALT6 | _PIN_INPUT) +#define PIN_ALT6_PULLDOWN (_PIN_MODE_ALT6 | _PIN_INPUT_PULLDOWN) +#define PIN_ALT6_PULLUP (_PIN_MODE_ALT6 | _PIN_INPUT_PULLUP) +#define PIN_ALT6_OUTPUT (_PIN_MODE_ALT6 | _PIN_OUTPUT) +#define PIN_ALT6_FAST (_PIN_MODE_ALT6 | _PIN_OUTPUT_FAST) +#define PIN_ALT6_SLOW (_PIN_MODE_ALT6 | _PIN_OUTPUT_SLOW) +#define PIN_ALT6_OPENDRAIN (_PIN_MODE_ALT6 | _PIN_OUTPUT_LOWDRIVE) +#define PIN_ALT6_LOWDRIVE (_PIN_MODE_ALT6 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT6_HIGHDRIVE (_PIN_MODE_ALT6 | _PIN_OUTPUT_HIGHDRIVE) + +#define PIN_ALT7 _PIN_MODE_ALT7 +#define PIN_ALT7_INPUT (_PIN_MODE_ALT7 | _PIN_INPUT) +#define PIN_ALT7_PULLDOWN (_PIN_MODE_ALT7 | _PIN_INPUT_PULLDOWN) +#define PIN_ALT7_PULLUP (_PIN_MODE_ALT7 | _PIN_INPUT_PULLUP) +#define PIN_ALT7_OUTPUT (_PIN_MODE_ALT7 | _PIN_OUTPUT) +#define PIN_ALT7_FAST (_PIN_MODE_ALT7 | _PIN_OUTPUT_FAST) +#define PIN_ALT7_SLOW (_PIN_MODE_ALT7 | _PIN_OUTPUT_SLOW) +#define PIN_ALT7_OPENDRAIN (_PIN_MODE_ALT7 | _PIN_OUTPUT_LOWDRIVE) +#define PIN_ALT7_LOWDRIVE (_PIN_MODE_ALT7 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT7_HIGHDRIVE (_PIN_MODE_ALT7 | _PIN_OUTPUT_HIGHDRIVE) + +/* The initial value for GPIO (Alternative 1 outputs): * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * ...D .... .... .... + * ---- ---v ---- ---- ---- ---- ---- ---- + * + * Passive Filter and digital filter enable are valid in all digital pin + * muxing modes. */ -#define GPIO_DEBOUNCE (1 << 12) /* Bit 12: Debounce enable */ +#define GPIO_OUTPUT_ONE (1 << 24) /* Bit 24: 1:Initial output value=1 */ +#define GPIO_OUTPUT_ZER0 (0) /* Bit 24: 0:Initial output value=0 */ -/* Interrupt Controls: +/* Five bits are used to incode DMA/interrupt options: + * + * ---- ---- iiii i--- ---- ---- ---- ---- * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... III. .... .... + * The pin interrupt configuration is valid in all digital pin muxing modes + * (restricted to inputs). */ -#define GPIO_INTERRUPT_SHIFT (9) /* Bits 9-11: Interrupt controls */ -#define GPIO_INTERRUPT_MASK (7 << GPIO_INTERRUPT_SHIFT) -# define GPIO_INTERRUPT_NONE (0 << GPIO_INTERRUPT_SHIFT) -# define GPIO_INTERRUPT_RISING_EDGE (1 << GPIO_INTERRUPT_SHIFT) -# define GPIO_INTERRUPT_FALLING_EDGE (2 << GPIO_INTERRUPT_SHIFT) -# define GPIO_INTERRUPT_BOTH_EDGES (3 << GPIO_INTERRUPT_SHIFT) -# define GPIO_INTERRUPT_HIGH_LEVEL (4 << GPIO_INTERRUPT_SHIFT) -# define GPIO_INTERRUPT_LOW_LEVEL (5 << GPIO_INTERRUPT_SHIFT) +#define _PIN_INT_SHIFT (20) +#define _PIN_INT_MASK (31 << _PIN_INT_SHIFT) + +#define _PIN_INTDMA_MASK (3 << _PIN_INT_SHIFT) +#define _PIN_INTDMA_NONE (0 << _PIN_INT_SHIFT) +#define _PIN_DMA (1 << _PIN_INT_SHIFT) +#define _PIN_INTERRUPT (2 << _PIN_INT_SHIFT) + +#define PIN_DMA_RISING (5 << _PIN_INT_SHIFT) /* 00101 DMA Request on rising edge */ +#define PIN_DMA_FALLING (9 << _PIN_INT_SHIFT) /* 01001 DMA Request on falling edge */ +#define PIN_DMA_BOTH (13 << _PIN_INT_SHIFT) /* 01101 DMA Request on either edge */ +#define PIN_INT_ZERO (2 << _PIN_INT_SHIFT) /* 00010 Interrupt when logic zero */ +#define PIN_INT_RISING (6 << _PIN_INT_SHIFT) /* 00110 Interrupt on rising edge */ +#define PIN_INT_FALLING (10 << _PIN_INT_SHIFT) /* 01010 Interrupt on falling edge */ +#define PIN_INT_BOTH (14 << _PIN_INT_SHIFT) /* 01110 Interrupt on either edge */ +#define PIN_INT_ONE (18 << _PIN_INT_SHIFT) /* 10010 Interrupt when logic one */ -/* If the pin is a GPIO digital output, then this identifies the initial output value. +/* Two bits is used to enable the filter options: * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .... V... .... + * ---- ---- ---- -fd- ---- ---- ---- ---- + * + * Passive Filter and digital filter enable are valid in all digital pin + * muxing modes. */ -#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: If output, inital value of output */ -#define GPIO_OUTPUT_CLEAR (0) - -/* This identifies the GPIO port: +#define PIN_PASV_FILTER (1 << 18) /* Bit 18: Enable passive filter */ +#define PIN_DIG_FILTER (1 << 17) /* Bit 17: Enable digital filter */ + +/* Three bits are used to define the port number: * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .... .PPP .... + * ---- ---- ---- ---- ---- -ppp ---- ---- */ -#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */ -#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) -# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -# +#define _PIN_PORT_SHIFT (8) /* Bits 8-10: port number */ +#define _PIN_PORT_MASK (7 << _PIN_PORT_SHIFT) + +#define PIN_PORTA (KL_PORTA << _PIN_PORT_SHIFT) +#define PIN_PORTB (KL_PORTB << _PIN_PORT_SHIFT) +#define PIN_PORTC (KL_PORTC << _PIN_PORT_SHIFT) +#define PIN_PORTD (KL_PORTD << _PIN_PORT_SHIFT) +#define PIN_PORTE (KL_PORTE << _PIN_PORT_SHIFT) -/* This identifies the bit in the port: +/* Five bits are used to define the pin number: * - * 1111 1100 0000 0000 - * 5432 1098 7654 3210 - * ---- ---- ---- ---- - * .... .... .... BBBB + * ---- ---- ---- ---- ---- ---- ---b bbbb */ -#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */ -#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) -# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define _PIN_SHIFT (0) /* Bits 0-4: port number */ +#define _PIN_MASK (31 << _PIN_SHIFT) + +#define PIN(n) ((n) << _PIN_SHIFT) +#define PIN0 (0 << _PIN_SHIFT) +#define PIN1 (1 << _PIN_SHIFT) +#define PIN2 (2 << _PIN_SHIFT) +#define PIN3 (3 << _PIN_SHIFT) +#define PIN4 (4 << _PIN_SHIFT) +#define PIN5 (5 << _PIN_SHIFT) +#define PIN6 (6 << _PIN_SHIFT) +#define PIN7 (7 << _PIN_SHIFT) +#define PIN8 (8 << _PIN_SHIFT) +#define PIN9 (9 << _PIN_SHIFT) +#define PIN10 (10 << _PIN_SHIFT) +#define PIN11 (11 << _PIN_SHIFT) +#define PIN12 (12 << _PIN_SHIFT) +#define PIN13 (13 << _PIN_SHIFT) +#define PIN14 (14 << _PIN_SHIFT) +#define PIN15 (15 << _PIN_SHIFT) +#define PIN16 (16 << _PIN_SHIFT) +#define PIN17 (17 << _PIN_SHIFT) +#define PIN18 (18 << _PIN_SHIFT) +#define PIN19 (19 << _PIN_SHIFT) +#define PIN20 (20 << _PIN_SHIFT) +#define PIN21 (21 << _PIN_SHIFT) +#define PIN22 (22 << _PIN_SHIFT) +#define PIN23 (23 << _PIN_SHIFT) +#define PIN24 (24 << _PIN_SHIFT) +#define PIN25 (25 << _PIN_SHIFT) +#define PIN26 (26 << _PIN_SHIFT) +#define PIN27 (27 << _PIN_SHIFT) +#define PIN28 (28 << _PIN_SHIFT) +#define PIN29 (29 << _PIN_SHIFT) +#define PIN30 (30 << _PIN_SHIFT) +#define PIN31 (31 << _PIN_SHIFT) /**************************************************************************** * Public Types @@ -202,18 +318,12 @@ extern "C" { * Name: kl_configgpio * * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with kl_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returns: - * OK on success - * ERROR on invalid port, or when pin is locked as ALT function. + * Configure a PIN based on bit-encoded description of the pin. NOTE that + * DMA/interrupts are disabled at the initial PIN configuratin. * ****************************************************************************/ -int kl_configgpio(gpio_cfgset_t cfgset); +int kl_configgpio(uint32_t cfgset); /**************************************************************************** * Name: kl_gpiowrite @@ -223,7 +333,7 @@ int kl_configgpio(gpio_cfgset_t cfgset); * ****************************************************************************/ -void kl_gpiowrite(gpio_cfgset_t pinset, bool value); +void kl_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** * Name: kl_gpioread @@ -233,27 +343,7 @@ void kl_gpiowrite(gpio_cfgset_t pinset, bool value); * ****************************************************************************/ -bool kl_gpioread(gpio_cfgset_t pinset); - -/**************************************************************************** - * Function: kl_dumpgpio - * - * Description: - * Dump all GPIO registers associated with the provided pin description - * along with a descriptive messasge. - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG -void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg); -#else -# define kl_dumpgpio(p,m) -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif +bool kl_gpioread(uint32_t pinset); #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_KL_KINETIS_GPIO_H */ diff --git a/nuttx/arch/arm/src/kl/kl_internal.h b/nuttx/arch/arm/src/kl/kl_internal.h deleted file mode 100644 index 467cb2ab6..000000000 --- a/nuttx/arch/arm/src/kl/kl_internal.h +++ /dev/null @@ -1,775 +0,0 @@ -/************************************************************************************ - * arch/arm/src/kl/kl_internal.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KL_KL_INTERNAL_H -#define __ARCH_ARM_SRC_KL_KL_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> -#include <nuttx/compiler.h> - -#include <sys/types.h> -#include <stdint.h> -#include <stdbool.h> - -#include <nuttx/irq.h> - -#include "up_internal.h" -#include "kl_config.h" -#include "chip.h" -#include "chip/kl_port.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Configuration ********************************************************************/ - -/* Bit-encoded input to kl_pinconfig() *****************************************/ -/* General form (32-bits, only 22 bits are unused in the encoding): - * - * oooo mmmv iiii ifd- ---- -ppp ---b bbbb - */ - -/* Bits 25-31: 7 bits are used to encode the basic pin configuration: - * - * oooo mmm- ---- ---- ---- ---- ---- ---- - * oooommm: - * | `--- mmm: mode - * `------- oooo: options (may be combined) - */ - -#define _PIN_MODE_SHIFT (25) /* Bits 25-27: Pin mode */ -#define _PIN_MODE_MASK (7 << _PIN_MODE_SHIFT) -#define _PIN_OPTIONS_SHIFT (28) /* Bits 28-31: Pin mode options */ -#define _PIN_OPTIONS_MASK (15 << _PIN_OPTIONS_SHIFT) - -/* Port Modes */ - -#define _PIN_MODE_ANALOG (0 << _PIN_MODE_SHIFT) /* 000 Pin Disabled (Analog) */ -#define _PIN_MODE_GPIO (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 (GPIO) */ -#define _PIN_MODE_ALT2 (2 << _PIN_MODE_SHIFT) /* 010 Alternative 2 */ -#define _PIN_MODE_ALT3 (3 << _PIN_MODE_SHIFT) /* 011 Alternative 3 */ -#define _PIN_MODE_ALT4 (4 << _PIN_MODE_SHIFT) /* 100 Alternative 4 */ -#define _PIN_MODE_ALT5 (5 << _PIN_MODE_SHIFT) /* 101 Alternative 5 */ -#define _PIN_MODE_ALT6 (6 << _PIN_MODE_SHIFT) /* 110 Alternative 6 */ -#define _PIN_MODE_ALT7 (7 << _PIN_MODE_SHIFT) /* 111 Alternative 7 */ - -/* Options for all digital modes (Alternatives 1-7). None of the digital - * options apply if the analog mode is selected. - */ - -#define _PIN_IO_MASK (1 << _PIN_OPTIONS_SHIFT) /* xxx1 Digital input/output mask */ -#define _PIN_INPUT (0 << _PIN_OPTIONS_SHIFT) /* xxx0 Digital input */ -#define _PIN_OUTPUT (1 << _PIN_OPTIONS_SHIFT) /* xxx1 Digital output */ - -#define _PIN_INPUT_PULLMASK (7 << _PIN_OPTIONS_SHIFT) /* x111 Mask for pull-up or -down bits */ -#define _PIN_INPUT_PULLDOWN (2 << _PIN_OPTIONS_SHIFT) /* x010 Input with internal pull-down resistor */ -#define _PIN_INPUT_PULLUP (6 << _PIN_OPTIONS_SHIFT) /* x110 Input with internal pull-up resistor */ - -#define _PIN_OUTPUT_SLEW_MASK (3 << _PIN_OPTIONS_SHIFT) /* xx11 Mask to test for slow slew rate */ -#define _PIN_OUTPUT_FAST (1 << _PIN_OPTIONS_SHIFT) /* xx01 Output with fast slew rate */ -#define _PIN_OUTPUT_SLOW (3 << _PIN_OPTIONS_SHIFT) /* xx11 Output with slow slew rate */ -#define _PIN_OUTPUT_OD_MASK (5 << _PIN_OPTIONS_SHIFT) /* x1x1 Mask to test for open drain */ -#define _PIN_OUTPUT_OPENDRAIN (5 << _PIN_OPTIONS_SHIFT) /* x1x1 Output with open drain enabled */ -#define _PIN_OUTPUT_DRIVE_MASK (9 << _PIN_OPTIONS_SHIFT) /* 1xx1 Mask to test for high drive strengh */ -#define _PIN_OUTPUT_LOWDRIVE (1 << _PIN_OPTIONS_SHIFT) /* 0xx1 Output with low drive strength */ -#define _PIN_OUTPUT_HIGHDRIVE (9 << _PIN_OPTIONS_SHIFT) /* 1xx1 Output with high drive strength */ - -/* End-user pin modes and configurations. Notes: (1) None of the digital options - * are available for the analog mode, (2) digital settings may be combined (OR'ed) - * provided that input-only and output-only options are not intermixed. - */ - -#define PIN_ANALOG _PIN_MODE_ANALOG - -#define GPIO_INPUT (_PIN_MODE_GPIO | _PIN_INPUT) -#define GPIO_PULLDOWN (_PIN_MODE_GPIO | _PIN_INPUT_PULLDOWN) -#define GPIO_PULLUP (_PIN_MODE_GPIO | _PIN_INPUT_PULLUP) -#define GPIO_OUTPUT (_PIN_MODE_GPIO | _PIN_OUTPUT) -#define GPIO_FAST (_PIN_MODE_GPIO | _PIN_OUTPUT_FAST) -#define GPIO_SLOW (_PIN_MODE_GPIO | _PIN_OUTPUT_SLOW) -#define GPIO_OPENDRAIN (_PIN_MODE_GPIO | _PIN_OUTPUT_LOWDRIVE) -#define GPIO_LOWDRIVE (_PIN_MODE_GPIO | _PIN_OUTPUT_OPENDRAIN) -#define GPIO_HIGHDRIVE (_PIN_MODE_GPIO | _PIN_OUTPUT_HIGHDRIVE) - -#define PIN_ALT2 _PIN_MODE_ALT2 -#define PIN_ALT2_INPUT (_PIN_MODE_ALT2 | _PIN_INPUT) -#define PIN_ALT2_PULLDOWN (_PIN_MODE_ALT2 | _PIN_INPUT_PULLDOWN) -#define PIN_ALT2_PULLUP (_PIN_MODE_ALT2 | _PIN_INPUT_PULLUP) -#define PIN_ALT2_OUTPUT (_PIN_MODE_ALT2 | _PIN_OUTPUT) -#define PIN_ALT2_FAST (_PIN_MODE_ALT2 | _PIN_OUTPUT_FAST) -#define PIN_ALT2_SLOW (_PIN_MODE_ALT2 | _PIN_OUTPUT_SLOW) -#define PIN_ALT2_OPENDRAIN (_PIN_MODE_ALT2 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT2_LOWDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_OPENDRAIN) -#define PIN_ALT2_HIGHDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_HIGHDRIVE) - -#define PIN_ALT3 _PIN_MODE_ALT3 -#define PIN_ALT3_INPUT (_PIN_MODE_ALT3 | _PIN_INPUT) -#define PIN_ALT3_PULLDOWN (_PIN_MODE_ALT3 | _PIN_INPUT_PULLDOWN) -#define PIN_ALT3_PULLUP (_PIN_MODE_ALT3 | _PIN_INPUT_PULLUP) -#define PIN_ALT3_OUTPUT (_PIN_MODE_ALT3 | _PIN_OUTPUT) -#define PIN_ALT3_FAST (_PIN_MODE_ALT3 | _PIN_OUTPUT_FAST) -#define PIN_ALT3_SLOW (_PIN_MODE_ALT3 | _PIN_OUTPUT_SLOW) -#define PIN_ALT3_OPENDRAIN (_PIN_MODE_ALT3 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT3_LOWDRIVE (_PIN_MODE_ALT3 | _PIN_OUTPUT_OPENDRAIN) -#define PIN_ALT3_HIGHDRIVE (_PIN_MODE_ALT3 | _PIN_OUTPUT_HIGHDRIVE) - -#define PIN_ALT4 _PIN_MODE_ALT4 -#define PIN_ALT4_INPUT (_PIN_MODE_ALT4 | _PIN_INPUT) -#define PIN_ALT4_PULLDOWN (_PIN_MODE_ALT4 | _PIN_INPUT_PULLDOWN) -#define PIN_ALT4_PULLUP (_PIN_MODE_ALT4 | _PIN_INPUT_PULLUP) -#define PIN_ALT4_OUTPUT (_PIN_MODE_ALT4 | _PIN_OUTPUT) -#define PIN_ALT4_FAST (_PIN_MODE_ALT4 | _PIN_OUTPUT_FAST) -#define PIN_ALT4_SLOW (_PIN_MODE_ALT4 | _PIN_OUTPUT_SLOW) -#define PIN_ALT4_OPENDRAIN (_PIN_MODE_ALT4 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT4_LOWDRIVE (_PIN_MODE_ALT4 | _PIN_OUTPUT_OPENDRAIN) -#define PIN_ALT4_HIGHDRIVE (_PIN_MODE_ALT4 | _PIN_OUTPUT_HIGHDRIVE) - -#define PIN_ALT5 _PIN_MODE_ALT5 -#define PIN_ALT5_INPUT (_PIN_MODE_ALT5 | _PIN_INPUT) -#define PIN_ALT5_PULLDOWN (_PIN_MODE_ALT5 | _PIN_INPUT_PULLDOWN) -#define PIN_ALT5_PULLUP (_PIN_MODE_ALT5 | _PIN_INPUT_PULLUP) -#define PIN_ALT5_OUTPUT (_PIN_MODE_ALT5 | _PIN_OUTPUT) -#define PIN_ALT5_FAST (_PIN_MODE_ALT5 | _PIN_OUTPUT_FAST) -#define PIN_ALT5_SLOW (_PIN_MODE_ALT5 | _PIN_OUTPUT_SLOW) -#define PIN_ALT5_OPENDRAIN (_PIN_MODE_ALT5 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT5_LOWDRIVE (_PIN_MODE_ALT5 | _PIN_OUTPUT_OPENDRAIN) -#define PIN_ALT5_HIGHDRIVE (_PIN_MODE_ALT5 | _PIN_OUTPUT_HIGHDRIVE) - -#define PIN_ALT6 _PIN_MODE_ALT6 -#define PIN_ALT6_INPUT (_PIN_MODE_ALT6 | _PIN_INPUT) -#define PIN_ALT6_PULLDOWN (_PIN_MODE_ALT6 | _PIN_INPUT_PULLDOWN) -#define PIN_ALT6_PULLUP (_PIN_MODE_ALT6 | _PIN_INPUT_PULLUP) -#define PIN_ALT6_OUTPUT (_PIN_MODE_ALT6 | _PIN_OUTPUT) -#define PIN_ALT6_FAST (_PIN_MODE_ALT6 | _PIN_OUTPUT_FAST) -#define PIN_ALT6_SLOW (_PIN_MODE_ALT6 | _PIN_OUTPUT_SLOW) -#define PIN_ALT6_OPENDRAIN (_PIN_MODE_ALT6 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT6_LOWDRIVE (_PIN_MODE_ALT6 | _PIN_OUTPUT_OPENDRAIN) -#define PIN_ALT6_HIGHDRIVE (_PIN_MODE_ALT6 | _PIN_OUTPUT_HIGHDRIVE) - -#define PIN_ALT7 _PIN_MODE_ALT7 -#define PIN_ALT7_INPUT (_PIN_MODE_ALT7 | _PIN_INPUT) -#define PIN_ALT7_PULLDOWN (_PIN_MODE_ALT7 | _PIN_INPUT_PULLDOWN) -#define PIN_ALT7_PULLUP (_PIN_MODE_ALT7 | _PIN_INPUT_PULLUP) -#define PIN_ALT7_OUTPUT (_PIN_MODE_ALT7 | _PIN_OUTPUT) -#define PIN_ALT7_FAST (_PIN_MODE_ALT7 | _PIN_OUTPUT_FAST) -#define PIN_ALT7_SLOW (_PIN_MODE_ALT7 | _PIN_OUTPUT_SLOW) -#define PIN_ALT7_OPENDRAIN (_PIN_MODE_ALT7 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT7_LOWDRIVE (_PIN_MODE_ALT7 | _PIN_OUTPUT_OPENDRAIN) -#define PIN_ALT7_HIGHDRIVE (_PIN_MODE_ALT7 | _PIN_OUTPUT_HIGHDRIVE) - -/* The initial value for GPIO (Alternative 1 outputs): - * - * ---- ---v ---- ---- ---- ---- ---- ---- - * - * Passive Filter and digital filter enable are valid in all digital pin - * muxing modes. - */ - -#define GPIO_OUTPUT_ONE (1 << 24) /* Bit 24: 1:Initial output value=1 */ -#define GPIO_OUTPUT_ZER0 (0) /* Bit 24: 0:Initial output value=0 */ - -/* Five bits are used to incode DMA/interrupt options: - * - * ---- ---- iiii i--- ---- ---- ---- ---- - * - * The pin interrupt configuration is valid in all digital pin muxing modes - * (restricted to inputs). - */ - -#define _PIN_INT_SHIFT (20) -#define _PIN_INT_MASK (31 << _PIN_INT_SHIFT) - -#define _PIN_INTDMA_MASK (3 << _PIN_INT_SHIFT) -#define _PIN_INTDMA_NONE (0 << _PIN_INT_SHIFT) -#define _PIN_DMA (1 << _PIN_INT_SHIFT) -#define _PIN_INTERRUPT (2 << _PIN_INT_SHIFT) - -#define PIN_DMA_RISING (5 << _PIN_INT_SHIFT) /* 00101 DMA Request on rising edge */ -#define PIN_DMA_FALLING (9 << _PIN_INT_SHIFT) /* 01001 DMA Request on falling edge */ -#define PIN_DMA_BOTH (13 << _PIN_INT_SHIFT) /* 01101 DMA Request on either edge */ -#define PIN_INT_ZERO (2 << _PIN_INT_SHIFT) /* 00010 Interrupt when logic zero */ -#define PIN_INT_RISING (6 << _PIN_INT_SHIFT) /* 00110 Interrupt on rising edge */ -#define PIN_INT_FALLING (10 << _PIN_INT_SHIFT) /* 01010 Interrupt on falling edge */ -#define PIN_INT_BOTH (14 << _PIN_INT_SHIFT) /* 01110 Interrupt on either edge */ -#define PIN_INT_ONE (18 << _PIN_INT_SHIFT) /* 10010 Interrupt when logic one */ - -/* Two bits is used to enable the filter options: - * - * ---- ---- ---- -fd- ---- ---- ---- ---- - * - * Passive Filter and digital filter enable are valid in all digital pin - * muxing modes. - */ - -#define PIN_PASV_FILTER (1 << 18) /* Bit 18: Enable passive filter */ -#define PIN_DIG_FILTER (1 << 17) /* Bit 17: Enable digital filter */ - -/* Three bits are used to define the port number: - * - * ---- ---- ---- ---- ---- -ppp ---- ---- - */ - -#define _PIN_PORT_SHIFT (8) /* Bits 8-10: port number */ -#define _PIN_PORT_MASK (7 << _PIN_PORT_SHIFT) - -#define PIN_PORTA (KL_PORTA << _PIN_PORT_SHIFT) -#define PIN_PORTB (KL_PORTB << _PIN_PORT_SHIFT) -#define PIN_PORTC (KL_PORTC << _PIN_PORT_SHIFT) -#define PIN_PORTD (KL_PORTD << _PIN_PORT_SHIFT) -#define PIN_PORTE (KL_PORTE << _PIN_PORT_SHIFT) - -/* Five bits are used to define the pin number: - * - * ---- ---- ---- ---- ---- ---- ---b bbbb - */ - -#define _PIN_SHIFT (0) /* Bits 0-4: port number */ -#define _PIN_MASK (31 << _PIN_SHIFT) - -#define PIN(n) ((n) << _PIN_SHIFT) -#define PIN0 (0 << _PIN_SHIFT) -#define PIN1 (1 << _PIN_SHIFT) -#define PIN2 (2 << _PIN_SHIFT) -#define PIN3 (3 << _PIN_SHIFT) -#define PIN4 (4 << _PIN_SHIFT) -#define PIN5 (5 << _PIN_SHIFT) -#define PIN6 (6 << _PIN_SHIFT) -#define PIN7 (7 << _PIN_SHIFT) -#define PIN8 (8 << _PIN_SHIFT) -#define PIN9 (9 << _PIN_SHIFT) -#define PIN10 (10 << _PIN_SHIFT) -#define PIN11 (11 << _PIN_SHIFT) -#define PIN12 (12 << _PIN_SHIFT) -#define PIN13 (13 << _PIN_SHIFT) -#define PIN14 (14 << _PIN_SHIFT) -#define PIN15 (15 << _PIN_SHIFT) -#define PIN16 (16 << _PIN_SHIFT) -#define PIN17 (17 << _PIN_SHIFT) -#define PIN18 (18 << _PIN_SHIFT) -#define PIN19 (19 << _PIN_SHIFT) -#define PIN20 (20 << _PIN_SHIFT) -#define PIN21 (21 << _PIN_SHIFT) -#define PIN22 (22 << _PIN_SHIFT) -#define PIN23 (23 << _PIN_SHIFT) -#define PIN24 (24 << _PIN_SHIFT) -#define PIN25 (25 << _PIN_SHIFT) -#define PIN26 (26 << _PIN_SHIFT) -#define PIN27 (27 << _PIN_SHIFT) -#define PIN28 (28 << _PIN_SHIFT) -#define PIN29 (29 << _PIN_SHIFT) -#define PIN30 (30 << _PIN_SHIFT) -#define PIN31 (31 << _PIN_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -typedef FAR void *DMA_HANDLE; -typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); - -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ - -#ifdef CONFIG_DEBUG_DMA -struct kl_dmaglobalregs_s -{ -#warning "Missing logic" - /* Global Registers */ -}; - -struct kl_dmachanregs_s -{ -#warning "Missing logic" - /* Channel Registers */ -}; - -struct kl_dmaregs_s -{ - /* Global Registers */ - - struct kl_dmaglobalregs_s gbl; - - /* Channel Registers */ - - struct kl_dmachanregs_s ch; -}; -#endif - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: kl_clockconfig - * - * Description: - * Called to initialize the Kinetis chip. This does whatever setup is needed to - * put the MCU in a usable state. This includes the initialization of clocking - * using the settings in board.h. - * - ************************************************************************************/ - -void kl_clockconfig(void); - -/************************************************************************************ - * Name: kl_lowsetup - * - * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. - * - ************************************************************************************/ - -void kl_lowsetup(void); - -/****************************************************************************** - * Name: kl_uartreset - * - * Description: - * Reset a UART. - * - ******************************************************************************/ - -#ifdef HAVE_UART_DEVICE -void kl_uartreset(uintptr_t uart_base); -#endif - -/****************************************************************************** - * Name: kl_uartconfigure - * - * Description: - * Configure a UART as a RS-232 UART. - * - ******************************************************************************/ - -#ifdef HAVE_UART_DEVICE -void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, - unsigned int parity, unsigned int nbits); -#endif - -/************************************************************************************ - * Name: kl_wddisable - * - * Description: - * Disable the watchdog timer - * - ************************************************************************************/ - -void kl_wddisable(void); - -/************************************************************************************ - * Name: kl_pinconfig - * - * Description: - * Configure a pin based on bit-encoded description of the pin. - * - ************************************************************************************/ - -int kl_pinconfig(uint32_t cfgset); - -/************************************************************************************ - * Name: kl_pinfilter - * - * Description: - * Configure the digital filter associated with a port. The digital filter - * capabilities of the PORT module are available in all digital pin muxing modes. - * - * Input parmeters: - * port - See KL_PORTn definitions in kl_port.h - * lpo - true: Digital Filters are clocked by the bus clock - * false: Digital Filters are clocked by the 1 kHz LPO clock - * width - Filter Length - * - ************************************************************************************/ - -int kl_pinfilter(unsigned int port, bool lpo, unsigned int width); - -/************************************************************************************ - * Name: kl_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ************************************************************************************/ - -void kl_gpiowrite(uint32_t pinset, bool value); - -/************************************************************************************ - * Name: kl_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ************************************************************************************/ - -bool kl_gpioread(uint32_t pinset); - -/************************************************************************************ - * Name: kl_pinirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -void kl_pinirqinitialize(void); -#else -# define kl_pinirqinitialize() -#endif - -/************************************************************************************ - * Name: kl_pinirqattach - * - * Description: - * Attach a pin interrupt handler. The normal initalization sequence is: - * - * 1. Call kl_pinconfig() to configure the interrupting pin (pin interrupts - * will be disabled. - * 2. Call kl_pinirqattach() to attach the pin interrupt handling function. - * 3. Call kl_pinirqenable() to enable interrupts on the pin. - * - * Parameters: - * - pinset: Pin configuration - * - pinisr: Pin interrupt service routine - * - * Returns: - * The previous value of the interrupt handler function pointer. This value may, - * for example, be used to restore the previous handler when multiple handlers are - * used. - * - ************************************************************************************/ - -xcpt_t kl_pinirqattach(uint32_t pinset, xcpt_t pinisr); - -/************************************************************************************ - * Name: kl_pinirqenable - * - * Description: - * Enable the interrupt for specified pin IRQ - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -void kl_pinirqenable(uint32_t pinset); -#else -# define kl_pinirqenable(pinset) -#endif - -/************************************************************************************ - * Name: kl_pinirqdisable - * - * Description: - * Disable the interrupt for specified pin - * - ************************************************************************************/ - -#ifdef CONFIG_GPIO_IRQ -void kl_pinirqdisable(uint32_t pinset); -#else -# define kl_pinirqdisable(pinset) -#endif - -/************************************************************************************ - * Name: kl_pindmaenable - * - * Description: - * Enable DMA for specified pin - * - ************************************************************************************/ - -#ifdef CONFIG_KL_DMA -void kl_pindmaenable(uint32_t pinset); -#endif - -/************************************************************************************ - * Name: kl_pindmadisable - * - * Description: - * Disable DMA for specified pin - * - ************************************************************************************/ - -#ifdef CONFIG_KL_DMA -void kl_pindmadisable(uint32_t pinset); -#endif - -/************************************************************************************ - * Function: kl_pindump - * - * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_GPIO -int kl_pindump(uint32_t pinset, const char *msg); -#else -# define kl_pindump(p,m) -#endif - -/************************************************************************************ - * Name: kl_clrpend - * - * Description: - * Clear a pending interrupt at the NVIC. This does not seem to be required - * for most interrupts. - * - ************************************************************************************/ - -void kl_clrpend(int irq); - -/************************************************************************************ - * Name: kl_spi[n]select, kl_spi[n]status, and kl_spi[n]cmddata - * - * Description: - * These external functions must be provided by board-specific logic. They are - * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods - * including up_spiinitialize()) are provided by common Kinetis logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in kl_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide kl_spi[n]select() and kl_spi[n]status() functions - * in your board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * kl_spi[n]cmddata() functions in your board-specific logic. These - * functions will perform cmd/data selection operations using GPIOs in the way - * your board is configured. - * 3. Add a call to up_spiinitialize() in your low level application - * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ************************************************************************************/ - -struct spi_dev_s; -enum spi_dev_e; - -#ifdef CONFIG_KL_SPI0 -void kl_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kl_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kl_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif -#ifdef CONFIG_KL_SPI1 -void kl_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kl_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kl_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif -#ifdef CONFIG_KL_SPI2 -void kl_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kl_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kl_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif - -/**************************************************************************** - * Name: ssp_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be called - * from spi[n]select after a device is deselected (if you worry about such - * things). - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI2) -struct spi_dev_s; -void spi_flush(FAR struct spi_dev_s *dev); -#endif - -/**************************************************************************** - * Name: kl_dmainitialize - * - * Description: - * Initialize the GPDMA subsystem. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -void kl_dmainitilaize(void); -#endif - -/**************************************************************************** - * Name: kl_dmachannel - * - * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and - * gives the caller exclusive access to the DMA channel. - * - * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -DMA_HANDLE kl_dmachannel(void); -#endif - -/**************************************************************************** - * Name: kl_dmafree - * - * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until kl_dmachannel() is called again to re-gain - * a valid handle. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -void kl_dmafree(DMA_HANDLE handle); -#endif - -/**************************************************************************** - * Name: kl_dmasetup - * - * Description: - * Configure DMA for one transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -int kl_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, - uint32_t srcaddr, uint32_t destaddr, size_t nbytes); -#endif - -/**************************************************************************** - * Name: kl_dmastart - * - * Description: - * Start the DMA transfer - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -int kl_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -#endif - -/**************************************************************************** - * Name: kl_dmastop - * - * Description: - * Cancel the DMA. After kl_dmastop() is called, the DMA channel is - * reset and kl_dmasetup() must be called before kl_dmastart() can be - * called again - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -void kl_dmastop(DMA_HANDLE handle); -#endif - -/**************************************************************************** - * Name: kl_dmasample - * - * Description: - * Sample DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -#ifdef CONFIG_DEBUG_DMA -void kl_dmasample(DMA_HANDLE handle, struct kl_dmaregs_s *regs); -#else -# define kl_dmasample(handle,regs) -#endif -#endif - -/**************************************************************************** - * Name: kl_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_KL_DMA -#ifdef CONFIG_DEBUG_DMA -void kl_dmadump(DMA_HANDLE handle, const struct kl_dmaregs_s *regs, - const char *msg); -#else -# define kl_dmadump(handle,regs,msg) -#endif -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_KL_KL_INTERNAL_H */ diff --git a/nuttx/arch/arm/src/kl/kl_irq.h b/nuttx/arch/arm/src/kl/kl_irq.h index 089cd60bd..ee5de9309 100644 --- a/nuttx/arch/arm/src/kl/kl_irq.h +++ b/nuttx/arch/arm/src/kl/kl_irq.h @@ -54,6 +54,16 @@ * Public Data ************************************************************************************/ +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + /************************************************************************************ * Inline Functions ************************************************************************************/ @@ -62,4 +72,10 @@ * Public Functions ************************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_KL_KINETIS_IRQ_H */ diff --git a/nuttx/arch/arm/src/kl/kl_lowputc.c b/nuttx/arch/arm/src/kl/kl_lowputc.c index 5f2242969..27675a017 100644 --- a/nuttx/arch/arm/src/kl/kl_lowputc.c +++ b/nuttx/arch/arm/src/kl/kl_lowputc.c @@ -49,7 +49,8 @@ #include "kl_config.h" #include "kl_lowputc.h" -#include "kl_internal.h" +#include "kl_gpio.h" + #include "chip/kl_uart.h" #include "chip/kl_sim.h" #include "chip/kl_port.h" diff --git a/nuttx/arch/arm/src/kl/kl_lowputc.h b/nuttx/arch/arm/src/kl/kl_lowputc.h index b30544e0f..ab9df0ce4 100644 --- a/nuttx/arch/arm/src/kl/kl_lowputc.h +++ b/nuttx/arch/arm/src/kl/kl_lowputc.h @@ -74,48 +74,50 @@ extern "C" * Name: kl_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization. + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console UART. This UART done early so that the serial + * console is available for debugging very early in the boot sequence. * ************************************************************************************/ void kl_lowsetup(void); -/**************************************************************************** - * Name: kl_setbaud +/************************************************************************************ + * Name: kl_uartreset * * Description: - * Set the BAUD divxisor for the selected UART - * - * Mode DIV_X_EN DIV_X_ONE Divider X BRD (Baud rate equation) - * ------------------------------------------------------------- - * 0 Disable 0 B A UART_CLK / [16 * (A+2)] - * 1 Enable 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8 - * 2 Enable 1 Don't care A UART_CLK / (A+2), A must >=3 + * Reset a UART. * - * Here we assume that the default clock source for the UART modules is - * the external high speed crystal. - * - *****************************************************************************/ + ************************************************************************************/ -#ifdef HAVE_UART -void kl_setbaud(uintptr_t base, uint32_t baud); +#ifdef HAVE_UART_DEVICE +void kl_uartreset(uintptr_t uart_base); #endif -/**************************************************************************** +/************************************************************************************ * Name: kl_lowputc * * Description: * Output one character to the UART using a simple polling method. * - *****************************************************************************/ + ************************************************************************************/ #ifdef HAVE_SERIAL_CONSOLE void kl_lowputc(uint32_t ch); #endif -void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, - uint32_t clock, unsigned int parity, - unsigned int nbits); +/************************************************************************************ + * Name: kl_uartconfigure + * + * Description: + * Configure a UART as a RS-232 UART. + * + ************************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void kl_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock, + unsigned int parity, unsigned int nbits); +#endif #undef EXTERN #if defined(__cplusplus) diff --git a/nuttx/arch/arm/src/kl/kl_serial.c b/nuttx/arch/arm/src/kl/kl_serial.c index 290192dcd..a2f3918c7 100644 --- a/nuttx/arch/arm/src/kl/kl_serial.c +++ b/nuttx/arch/arm/src/kl/kl_serial.c @@ -61,9 +61,9 @@ #include "kl_config.h" #include "kl_lowputc.h" #include "chip.h" +#include "kl_gpio.h" #include "chip/kl_uart.h" -#include "kl_internal.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/arch/arm/src/kl/kl_spi.h b/nuttx/arch/arm/src/kl/kl_spi.h new file mode 100644 index 000000000..e6252a488 --- /dev/null +++ b/nuttx/arch/arm/src/kl/kl_spi.h @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/arm/src/kl/kl_gpio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KL_KL_SPI_H +#define __ARCH_ARM_SRC_KL_KL_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +/**************************************************************************** + * Pre-processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/************************************************************************************ + * Name: kl_spi[n]select, kl_spi[n]status, and kl_spi[n]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods + * including up_spiinitialize()) are provided by common Kinetis logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in kl_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide kl_spi[n]select() and kl_spi[n]status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * kl_spi[n]cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; + +#ifdef CONFIG_KL_SPI0 +void kl_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t kl_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int kl_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_KL_SPI1 +void kl_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t kl_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int kl_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_KL_SPI2 +void kl_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t kl_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int kl_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +/**************************************************************************** + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from spi[n]select after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI2) +struct spi_dev_s; +void spi_flush(FAR struct spi_dev_s *dev); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_KL_KL_SPI_H */ diff --git a/nuttx/arch/arm/src/kl/kl_start.c b/nuttx/arch/arm/src/kl/kl_start.c index be45a688d..ee411be83 100644 --- a/nuttx/arch/arm/src/kl/kl_start.c +++ b/nuttx/arch/arm/src/kl/kl_start.c @@ -53,9 +53,10 @@ #include "chip/kl_sim.h" #include "kl_config.h" +#include "kl_gpio.h" #include "kl_lowputc.h" #include "kl_userspace.h" -#include "kl_internal.h" +#include "kl_clockconfig.h" /**************************************************************************** * Pre-processor Definitions diff --git a/nuttx/configs/freedom-kl25z/src/freedom-kl25z.h b/nuttx/configs/freedom-kl25z/src/freedom-kl25z.h index b387b5a55..cc2f35a84 100644 --- a/nuttx/configs/freedom-kl25z/src/freedom-kl25z.h +++ b/nuttx/configs/freedom-kl25z/src/freedom-kl25z.h @@ -79,9 +79,9 @@ * LED_IDLE K25Z1XX is in sleep mode (Optional, not used) */ -#define GPIO_LED_R (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN18) -#define GPIO_LED_G (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN19) -#define GPIO_LED_B (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN1) +#define GPIO_LED_R (GPIO_OUTPUT | PIN_PORTB | PIN18) +#define GPIO_LED_G (GPIO_OUTPUT | PIN_PORTB | PIN19) +#define GPIO_LED_B (GPIO_OUTPUT | PIN_PORTD | PIN1) /* Button definitions ***************************************************************/ /* The Freedom KL25Z has no buttons */ diff --git a/nuttx/configs/freedom-kl25z/src/kl_led.c b/nuttx/configs/freedom-kl25z/src/kl_led.c index ccd4b4f58..a71c56638 100644 --- a/nuttx/configs/freedom-kl25z/src/kl_led.c +++ b/nuttx/configs/freedom-kl25z/src/kl_led.c @@ -127,11 +127,9 @@ void kl_ledinit(void) { - led_dumpgpio("Before configuration"); - //kl_configgpio(GPIO_LED_R); - //kl_configgpio(GPIO_LED_G); - //kl_configgpio(GPIO_LED_B); - led_dumpgpio("After configuration"); + kl_configgpio(GPIO_LED_R); + kl_configgpio(GPIO_LED_G); + kl_configgpio(GPIO_LED_B); } /**************************************************************************** |