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* SAMA5: Fix HSMCI race condition. Now memory card interface is functional ↵Gregory Nutt2013-08-104-79/+251
| | | | with DMA
* Rearrange configuration settings so that ARCH_HAVE_SDIO is moved to higher, ↵Gregory Nutt2013-08-105-4/+4
| | | | sharable level
* Extend the virtual-to-physical address conversion logic to handle NFS SRM, ↵Gregory Nutt2013-08-091-34/+290
| | | | UDPH SRAM, and external SRAM and PSRAM.
* SAMA5: Centralize logic for conversion between physical and virtual addressesGregory Nutt2013-08-096-112/+437
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* Fix some cache-related issues with the SAMA5 DMA driverGregory Nutt2013-08-091-1/+33
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* SAM3,4,A5 DMA fixes; SAMA5 SPI driver now supports DMA transfersGregory Nutt2013-08-099-203/+1086
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* SAMA5: Use RDR/TDR registers for DMA, not FIFO registers; change DMA bit ↵Gregory Nutt2013-08-085-23/+48
| | | | settings to match Atmel example. Still no DMA
* SAMA5 DMA: Need to flush caches; DMA channel depends upon direction of DMA; ↵Gregory Nutt2013-08-084-74/+480
| | | | the maximum transfer size in bytes depends on the number of bytes per transfer
* More SAMA5 DMAC driver fixes. Still does not work.Gregory Nutt2013-08-075-27/+67
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* SAMA3,4,A5: Misc corrections to DMA and HSMCI driversGregory Nutt2013-08-076-182/+233
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* Fix SAM bug: Parmaters reversed in DMA function callGregory Nutt2013-08-064-9/+9
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* SAM3,4,A5 DMAC driver fixesGregory Nutt2013-08-063-12/+54
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* SAM3,4,A5: Fix some masked status checks that can generate false error reportsGregory Nutt2013-08-062-10/+16
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* SAMA5: A few early, easy bug fixes. The rest will all be difficultGregory Nutt2013-08-061-30/+36
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* SAMA5: Add PIO interrupt support. Massive name changes for consistency in ↵Gregory Nutt2013-08-0614-770/+1235
| | | | PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
* SAMA5: Add HSMCI memory card driver supportGregory Nutt2013-08-057-34/+3505
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* SAMA5: SPI Driver + AT25 FLASH work; SAM3/4: Correct an error, SPI will ↵Gregory Nutt2013-08-052-42/+75
| | | | not be correctly configured if CONFIG_SPI_OWNBUS=n
* SAMA5: Add logic to auto-mount a file system on AT25 SPI FLASH for NSHGregory Nutt2013-08-051-1/+1
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* SAMA5D3x-EK: At support for the AT25 serial FLASHGregory Nutt2013-08-041-0/+18
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* SAMA5: Add register level debug option for SPIGregory Nutt2013-08-042-4/+111
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* SAMA5: SPI driver now supports both SPI0 and SPI1Gregory Nutt2013-08-044-173/+375
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* SAMA5: Add basic SPI suppport (untested)Gregory Nutt2013-08-045-0/+1417
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* SAMA5: Add DMA suppport (untested)Gregory Nutt2013-08-047-9/+2267
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* SAMA5: Add DMA controller register definitionsGregory Nutt2013-08-032-1/+791
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* Standard configuration variables used to enable interupt controller debug; ↵Gregory Nutt2013-08-0311-213/+273
| | | | SAMA5: Correct handling of spurious interrupts
* Various changes to get SAMA5 SDRAM working. Marginally functional, but ↵Gregory Nutt2013-08-022-3/+3
| | | | there is more to be done
* Correct some typos int he MPADDRCS register address definitionsGregory Nutt2013-08-021-25/+25
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* SAMA5: More MMU-related changes to properly initialize SDRAMGregory Nutt2013-08-028-147/+551
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* SAMA5: Add logic to initialize SAMA5D3x-EK on-board SDRAMGregory Nutt2013-08-013-38/+51
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* SAMA5: Add DDR controller register definitionsGregory Nutt2013-08-011-0/+399
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* ARMv7-A: Map all of .text, .bss, .data., stacks before enabling the MMU and ↵Gregory Nutt2013-08-012-176/+140
| | | | caching. This is simpler and avoids fears I have about caching
* ARMv7-A: Separate CONFIG_PAGING start-up logic into a different startup ↵Gregory Nutt2013-08-013-147/+751
| | | | file. Too much conditional compilation.
* SAMA5: Add an NSH configuration of the SAMA5D3x-EK boardGregory Nutt2013-07-311-2/+2
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* SAMA5: Modification of some CPSR-related inline functionsGregory Nutt2013-07-311-9/+8
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* Fix Cortex-A CPSR register field definitionGregory Nutt2013-07-304-23/+28
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* SAMA5: Change mapping of vector tables to work around that fact that I don't ↵Gregory Nutt2013-07-302-0/+41
| | | | understand how the AXI MATRIX remap works
* ARMv7-A: Add cp15_disable_dcache(); SAMA5: nor_main.c no disables MMU and ↵Gregory Nutt2013-07-302-8/+58
| | | | caches; Should not remap ISRAM to address 0x0 unless we booted into ISRAM
* More DAC changes from John WharingtonGregory Nutt2013-07-301-1/+3
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* Add ARMv7-A irqdisable() inline functionGregory Nutt2013-07-301-0/+18
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* STM32 F3 I2C driver from John WharingtonGregory Nutt2013-07-304-92/+2313
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* STM32 DAC DMA fixes from John WharingtonGregory Nutt2013-07-306-44/+359
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* SAMA5: More cache and mmu inline utility functionsGregory Nutt2013-07-294-5/+254
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* SAMA5: Separate cache operations into separate filesGregory Nutt2013-07-297-305/+522
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* Changes to ARMv7-A boot logic to handle the case where we execute out of NOR ↵Gregory Nutt2013-07-292-60/+87
| | | | FLASH
* Add SAMA5 HSMC register definitions and logic to reconfigure the NOR FLASHGregory Nutt2013-07-291-0/+559
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* SAMA5: Add file structure to support board-specific initialization of NOR flashGregory Nutt2013-07-294-21/+167
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* SAMA5: The ostest configuration have been converted to run out of NOR flash. ↵Gregory Nutt2013-07-284-61/+121
| | | | There is more to be done, however
* SAMA5: Correct a clock configuration bug; clarify some MMU memory typesGregory Nutt2013-07-283-26/+86
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* SAMA5: Correct vector mappingGregory Nutt2013-07-285-96/+111
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* Removed unused ARMv7-A cache functionGregory Nutt2013-07-271-41/+0
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