path: root/nuttx/arch/arm/src/samv7/Kconfig

#
# For a description of the syntax of this configuration file,
# see misc/tools/kconfig-language.txt.
#

if ARCH_CHIP_SAMV7

comment "SAMV7 Configuration Options"

# Chip Selection

choice
	prompt "Atmel SAMV7 Chip Selection"
	default ARCH_CHIP_SAMV71Q21

config ARCH_CHIP_SAMV71Q19
	bool "SAMV71Q19"
	select ARCH_CHIP_SAMV71Q

config ARCH_CHIP_SAMV71Q20
	bool "SAMV71Q20"
	select ARCH_CHIP_SAMV71Q

config ARCH_CHIP_SAMV71Q21
	bool "SAMV71Q21"
	select ARCH_CHIP_SAMV71Q

config ARCH_CHIP_SAMV71N19
	bool "SAMV71N19"
	select ARCH_CHIP_SAMV71N

config ARCH_CHIP_SAMV71N20
	bool "SAMV71N20"
	select ARCH_CHIP_SAMV71N

config ARCH_CHIP_SAMV71N21
	bool "SAMV71N21"
	select ARCH_CHIP_SAMV71N

config ARCH_CHIP_SAMV71J19
	bool "SAMV71J19"
	select ARCH_CHIP_SAMV71J

config ARCH_CHIP_SAMV71J20
	bool "SAMV71J20"
	select ARCH_CHIP_SAMV71J

config ARCH_CHIP_SAMV71J21
	bool "SAMV71J21"
	select ARCH_CHIP_SAMV71J

endchoice # Atmel SAMV7 Chip Selection

config ARCH_CHIP_SAMV71
	bool
	default n
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU # REVISIT
	select ARMV7M_HAVE_ICACHE
	select ARMV7M_HAVE_DCACHE
	select ARMV7M_HAVE_ITCM
	select ARMV7M_HAVE_DTCM

config ARCH_CHIP_SAMV71Q
	bool
	default n
	select ARCH_CHIP_SAMV71
	select SAMV7_HAVE_CAN1
	select SAMV7_HAVE_DAC1
	select SAMV7_HAVE_EBI
	select SAMV7_HAVE_HSMCI0
	select SAMV7_HAVE_SDRAMC
	select SAMV7_HAVE_SPI0
	select SAMV7_HAVE_SPI1
	select SAMV7_HAVE_TWIHS2
	select SAMV7_HAVE_USBHS
	select SAMV7_HAVE_USART0
	select SAMV7_HAVE_USART1
	select SAMV7_HAVE_USART2

config ARCH_CHIP_SAMV71N
	bool
	default n
	select ARCH_CHIP_SAMV71
	select SAMV7_HAVE_CAN1
	select SAMV7_HAVE_DAC1
	select SAMV7_HAVE_HSMCI0
	select SAMV7_HAVE_SPI0
	select SAMV7_HAVE_TWIHS2
	select SAMV7_HAVE_USBHS
	select SAMV7_HAVE_USART0
	select SAMV7_HAVE_USART1
	select SAMV7_HAVE_USART2

config ARCH_CHIP_SAMV71J
	bool
	default n
	select ARCH_CHIP_SAMV71
	select SAMV7_QSPI_IS_SPI
	select SAMV7_HAVE_USBFS
	select SAMV7_HAVE_ISI8

# Chip Capabilities

config SAMV7_HAVE_CAN1
	bool
	default n

config SAMV7_HAVE_DAC1
	bool
	default n

config SAMV7_HAVE_EBI
	bool
	default n

config SAMV7_EMAC
	bool
	default n
	select ARMV7M_DCACHE_WRITETHROUGH if ARMV7M_DCACHE
	---help---
		NOTE that write-through caching is automatically selected.  This is
		to work around issues with the RX and TX descriptors with are 8-bytes
		in size.  But the D-Cache cache line size is 32-bytes.  That means
		that you cannot reload, clean or invalidate a descriptor without also
		effecting three neighboring descriptors.  Setting write through mode
		eliminates the need for cleaning.  If only reloading and invalidating
		are done, then there is no problem.

config SAMV7_HSMCI
	bool
	default n

config SAMV7_HAVE_HSMCI0
	bool
	default n

config SAMV7_HAVE_ISI8
	bool
	default n

config SAMV7_HAVE_SDRAMC
	bool
	default n

config SAMV7_HAVE_SPI
	bool
	default n

config SAMV7_HAVE_SPI0
	bool
	default n

config SAMV7_HAVE_SPI1
	bool
	default n

config SAMV7_QSPI_IS_SPI
	bool
	default n

config SAMV7_SSC
	bool
	default n

config SAMV7_HAVE_TWIHS2
	bool
	default n

config SAMV7_HAVE_USBFS
	bool
	default n

config SAMV7_HAVE_USBHS
	bool
	default n

config SAMV7_HAVE_USART0
	bool
	default n

config SAMV7_HAVE_USART1
	bool
	default n

config SAMV7_HAVE_USART2
	bool
	default n

# Peripheral Selection

menu "SAMV7 Peripheral Selection"

config SAMV7_ACC
	bool "Analog Comparator (ACC)"
	default n

config SAMV7_ADC
	bool "12-bit ADC Controller (ADC)"
	default n

config SAMV7_AFEC0
	bool "Analog Front End 0 (AFEC0)"
	default n

config SAMV7_AFEC1
	bool "Analog Front End 1 (AFEC1)"
	default n

config SAMV7_CAN0
	bool "CAN0"
	default n

config SAMV7_CAN1
	bool "CAN1"
	default n
	depends on SAMV7_HAVE_CAN1

config SAMV7_DAC0
	bool "Digital To Analog Converter 0 (DAC0)"
	default n

config SAMV7_DAC1
	bool "Digital To Analog Converter 1 (DAC1)"
	default n
	depends on SAMV7_HAVE_DAC1

config SAMV7_EBI
	bool "External Bus Interface (EBI)"
	default n
	depends on SAMV7_HAVE_EBI

config SAMV7_EMAC0
	bool "Ethernet MAC (GMAC)"
	default n
	select SAMV7_EMAC
	select NETDEVICES
	select ARCH_HAVE_PHY

config SAMV7_XDMAC
	bool "Central DMA (XDMA)"
	default n
	select ARCH_DMA

config SAMV7_HSMCI0
	bool "High Speed Multimedia Card Interface (HSMCI)"
	default n
	depends on SAMV7_HAVE_HSMCI0
	select SAMV7_HSMCI
	select ARCH_HAVE_SDIO
	select MMCSD

config SAMV7_ISI
	bool "Image Sensor Interface (ISI)"
	default n

config SAMV7_MLB
	bool "Media LB Interface"
	default n

config SAMV7_PWM0
	bool "Pulse Width Modulation Controller 0 (PWM0)"
	default n

config SAMV7_PWM1
	bool "Pulse Width Modulation Controller 0 (PWM1)"
	default n

config SAMV7_QSPI
	bool "Quad SPI (QSPI)"
	default n

config SAMV7_RTC
	bool "Real Time Clock (RTC)"
	default n

config SAMV7_RTT
	bool "Real Time Timer (RTT)"
	default n

config SAMV7_SDRAMC
	bool "SDRAM Controller (SDRAMC)"
	default n
	depends on SAMV7_HAVE_SDRAMC

config SAMV7_SMC
	bool "Static Memory Controller (SMC)"
	default n

config SAMV7_SPI0
	bool "Serial Peripheral Interface 0 (SPI0)"
	default n
	depends on SAMV7_HAVE_SPI0
	select SAMV7_HAVE_SPI
	select SPI

config SAMV7_SPI1
	bool "Serial Peripheral Interface 1 (SPI1)"
	default n
	depends on SAMV7_HAVE_SPI1
	select SAMV7_HAVE_SPI
	select SPI

config SAMV7_SSC0
	bool "Synchronous Serial Controller (SSC)"
	default n
	select SAMV7_SSC

config SAMV7_TC0
	bool "Timer/Counter 0 (TC0)"
	default n
	select SAMV7_TC

config SAMV7_TC1
	bool "Timer/Counter 1 (TC1)"
	default n
	select SAMV7_TC

config SAMV7_TC2
	bool "Timer/Counter 2 (TC2)"
	default n
	select SAMV7_TC

config SAMV7_TC3
	bool "Timer/Counter 3 (TC3)"
	default n
	select SAMV7_TC

config SAMV7_TC4
	bool "Timer/Counter 4 (TC4)"
	default n
	select SAMV7_TC

config SAMV7_TC5
	bool "Timer/Counter 5 (TC5)"
	default n
	select SAMV7_TC

config SAMV7_TC6
	bool "Timer/Counter 6 (TC6)"
	default n
	select SAMV7_TC

config SAMV7_TC7
	bool "Timer/Counter 7 (TC7)"
	default n
	select SAMV7_TC

config SAMV7_TC8
	bool "Timer/Counter 8 (TC8)"
	default n
	select SAMV7_TC

config SAMV7_TC9
	bool "Timer/Counter 9 (TC8)"
	default n
	select SAMV7_TC

config SAMV7_TC10
	bool "Timer/Counter 10 (TC9)"
	default n
	select SAMV7_TC

config SAMV7_TC11
	bool "Timer/Counter 11 (TC8)"
	default n
	select SAMV7_TC

config SAMV7_TRNG
	bool "True Random Number Generator (TRNG)"
	default n

config SAMV7_TWIHS0
	bool "Two-wire Interface 0 (TWIHS0)"
	default n

config SAMV7_TWIHS1
	bool "Two-wire Interface 1 (TWIHS1)"
	default n

config SAMV7_TWIHS2
	bool "Two-wire Interface 2 (TWIHS2)"
	default n
	depends on SAMV7_HAVE_TWIHS2

config SAMV7_UART0
	bool "UART 0"
	default y
	select ARCH_HAVE_UART0
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_UART1
	bool "UART 1"
	default n
	select ARCH_HAVE_UART1
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_UART2
	bool "UART 2"
	default y
	select ARCH_HAVE_UART2
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_UART3
	bool "UART 3"
	default n
	select ARCH_HAVE_UART3
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_UART4
	bool "UART 4"
	default y
	select ARCH_HAVE_UART4
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_USBDEVFS
	bool "USB Device Full Speed (USBFS)"
	default n
	depends on SAMV7_HAVE_USBFS
	select USBDEV

config SAMV7_USBDEVHS
	bool "USB Device High Speed (USBHS)"
	default n
	depends on SAMV7_HAVE_USBHS
	select USBDEV

config SAMV7_USBHOSTFS
	bool "USB Host Full Speed (USBFS)"
	default n
	depends on SAMV7_HAVE_USBFS
	select USBHOST

config SAMV7_USBHOSTHS
	bool "USB Host High Speed (USBHS)"
	default n
	depends on SAMV7_HAVE_USBHS
	select USBHOST

config SAMV7_USART0
	bool "USART 0"
	default n
	depends on SAMV7_HAVE_USART0
	select ARCH_HAVE_USART0
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_USART1
	bool "USART 1"
	default n
	depends on SAMV7_HAVE_USART1
	select ARCH_HAVE_USART1
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_USART2
	bool "USART 2"
	default n
	depends on SAMV7_HAVE_USART2
	select ARCH_HAVE_USART2
	select ARCH_HAVE_SERIAL_TERMIOS

config SAMV7_WDT0
	bool "Watchdog Timer (WDT0)"
	default n

config SAMV7_WDT1
	bool "Watchdog Timer (WDT1)"
	default n

endmenu # SAMV7 Peripheral Selection

menuconfig SAMV7_GPIO_IRQ
	bool "GPIO pin interrupts"
	---help---
		Enable support for interrupting GPIO pins

if SAMV7_GPIO_IRQ

config SAMV7_GPIOA_IRQ
	bool "GPIOA interrupts"
	default n

config SAMV7_GPIOB_IRQ
	bool "GPIOB interrupts"
	default n

config SAMV7_GPIOC_IRQ
	bool "GPIOC interrupts"
	default n

config SAMV7_GPIOD_IRQ
	bool "GPIOD interrupts"
	default n

config SAMV7_GPIOE_IRQ
	bool "GPIOE interrupts"
	default n

endif # SAMV7_GPIO_IRQ
endif # ARCH_CHIP_SAMV7

menu "SDRAM Configuration"
	depends on SAMV7_SDRAMC

config SAMV7_SDRAMSIZE
	int "SDRAM size (bytes)"
	default 0
	---help---
		This is the usable size of the SDRAM.  This may be a value less that
		the actual size of the SDRAM if, for some reason, you wish to
		reserve the end of SDRAM memory for some other purpose.

config SAMV7_SDRAMHEAP
	bool "SDRAM heap"
	default y
	---help---
		Add the first SAMV7_SDRAMSIZE bytes of SDRAM to the heap.  NOTE that
		this requires also that MM_REGIONS be incremented to support another memory region.

endmenu # SDRAM Configuration

menu "SAMV7 SPI device driver options"
	depends on AMV7_SPI0 || SAMV7_SPI1

config SAMV7_SPI_DMA
	bool "SPI DMA"
	default n
	depends on SAMV7_XDMAC
	---help---
		Use DMA to improve SPI transfer performance.

config SAMV7_SPI_DMATHRESHOLD
	int "SPI DMA threshold"
	default 4
	depends on SAMV7_SPI_DMA
	---help---
		When SPI DMA is enabled, small DMA transfers will still be performed
		by polling logic.  But we need a threshold value to determine what
		is small.  That value is provided by SAMV7_SPI_DMATHRESHOLD.

config SAMV7_SPI_DMADEBUG
	bool "SPI DMA transfer debug"
	depends on SAMV7_SPI_DMA && DEBUG && DEBUG_DMA
	default n
	---help---
		Enable special debug instrumentation analyze SPI DMA data transfers.
		This logic is as non-invasive as possible:  It samples DMA
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.

config SAMV7_SPI_REGDEBUG
	bool "SPI Register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level SPI device debug information.
		Requires also DEBUG.

endmenu # SAMV7 SPI device driver options

menu "TWIHS device driver options"
	depends on SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2

config SAMV7_TWIHS0_FREQUENCY
	int "TWIHS0 Frequency"
	default 100000
	depends on SAMV7_TWIHS0

config SAMV7_TWIHS1_FREQUENCY
	int "TWIHS1 Frequency"
	default 100000
	depends on SAMV7_TWIHS1

config SAMV7_TWIHS2_FREQUENCY
	int "TWIHS2 Frequency"
	default 100000
	depends on SAMV7_TWIHS2

config SAMV7_TWIHS_REGDEBUG
	bool "TWIHS register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level TWIHS device debug information.
		Very invasive! Requires also DEBUG.

endmenu # TWIHS device driver options

menu "SSC Configuration"
	depends on SAMV7_SSC

config SAMV7_SSC_MAXINFLIGHT
	int "SSC queue size"
	default 16
	---help---
		This is the total number of transfers, both RX and TX, that can be
		enqueue before the caller is required to wait.  This setting
		determines the number certain queue data structures that will be
		pre-allocated.

if SAMV7_SSC0
comment "SSC0 Configuration"

config SAMV7_SSC0_DATALEN
	int "Data width (bits)"
	default 16
	---help---
		Data width in bits.  This is a default value and may be change
		via the I2S interface

config SAMV7_SSC0_RX
	bool "Enable I2C receiver"
	default n
	---help---
		Enable I2S receipt logic

if SAMV7_SSC0_RX

choice
	prompt "Receiver clock source"
	default SAMV7_SSC0_RX_MCKDIV

config SAMV7_SSC0_RX_RKINPUT
	bool "RK input"
	---help---
		The SSC receiver clock is an external clock provided on the RK input
		pin.  Sample rate determined by the external clock frequency.

config SAMV7_SSC0_RX_TXCLK
	bool "Transmitter Clock"
	---help---
		The SSC receiver clock is transmitter clock.  RX sample rate is the same
		as the TX sample rate.

config SAMV7_SSC0_RX_MCKDIV
	bool "MCK/2"
	---help---
		The SSC receiver clock is the MCK/2 divided by a up to 4095.  Desired
		sample rate must be provided below.

endchoice # Receiver clock source

if !SAMV7_SSC0_RX_RKINPUT
choice
	prompt "Receiver output clock"
	default SAMV7_SSC0_RX_RKOUTPUT_NONE

config SAMV7_SSC0_RX_RKOUTPUT_NONE
	bool "None"

config SAMV7_SSC0_RX_RKOUTPUT_CONT
	bool "Continuous"

config SAMV7_SSC0_RX_RKOUTPUT_XFR
	bool "Only during transfers"

endchoice # Receiver output clock
endif # !SAMV7_SSC0_RX_RKINPUT

config SAMV7_SSC0_RX_FSLEN
	int "Receive Frame Sync Length"
	default 1
	range 1 255
	---help---
		This setting determines the pulse length of the Receive Frame Sync
		signal in units of receive clock periods.

config SAMV7_SSC0_RX_STTDLY
	int "Receive Start Delay Length"
	default 0
	range 0 255
	---help---
		This setting determines the pulse length to the start of data in
		receive clock periods.  It must be greater than or equal to the RX
		frame synch length.  Zero means no start delay.

endif # SAMV7_SSC0_RX

config SAMV7_SSC0_TX
	bool "Enable I2C transmitter"
	default n
	---help---
		Enable I2S transmission logic

if SAMV7_SSC0_TX

choice
	prompt "Transmitter clock source"
	default SAMV7_SSC0_TX_MCKDIV

config SAMV7_SSC0_TX_TKINPUT
	bool "TK input"
	---help---
		The SSC transmitter clock is an external clock provided on the TK input
		pin.  Sample rate determined by the external clock frequency.

config SAMV7_SSC0_TX_RXCLK
	bool "Receiver Clock"
	---help---
		The SSC transmitter clock is receiver clock.  TX sample rate is the same
		as the RX sample rate.

config SAMV7_SSC0_TX_MCKDIV
	bool "MCK/2"
	---help---
		The SSC transmitter clock is the MCK/2 divided by a up to 4095.  Desired
		sample rate must be provided below.

endchoice # Transmitter clock source

if !SAMV7_SSC0_TX_TKINPUT
choice
	prompt "Transmitter output clock"
	default SAMV7_SSC0_TX_TKOUTPUT_NONE

config SAMV7_SSC0_TX_TKOUTPUT_NONE
	bool "None"

config SAMV7_SSC0_TX_TKOUTPUT_CONT
	bool "Continuous"

config SAMV7_SSC0_TX_TKOUTPUT_XFR
	bool "Only during transfers"

endchoice # Receiver output clock
endif # !SAMV7_SSC0_TX_TKINPUT

config SAMV7_SSC0_TX_FSLEN
	int "Transmit Frame Sync Length"
	default 1
	range 0 255
	---help---
		This setting define the length of the Transmit Frame Sync signal in
		units of transmit clock periods.  A value of zero disables this
		feature.  In that case the TD line is driven with the default value
		during the Transmit Frame Sync signal.

config SAMV7_SSC0_TX_STTDLY
	int "Transmit Start Delay Length"
	default 0
	range 0 255
	---help---
		This setting determines the pulse length to the start of data in
		transmit clock periods.  It must be greater than or equal to the RX
		frame synch length.  Zero means no start delay.

endif # SAMV7_SSC0_TX

config SAMV7_SSC0_MCKDIV_SAMPLERATE
	int "Sample rate"
	default 48000
	depends on SAMV7_SSC0_RX_MCKDIV || SAMV7_SSC0_TX_MCKDIV
	---help---
		If the either the receiver or transmitter clock is provided by MCK/2 divided
		down, then the sample rate must be provided.  The bit rate will be the product
		of the sample rate and the data width.  The SSC driver will determine the best
		divider to obtain that bit rate (up to 4095).  If the bit rate can be realized
		by dividing down the MCK/2, a compile time error will occur.

config SAMV7_SSC0_LOOPBACK
	bool "Loopback mode"
	default n
	depends on SAMV7_SSC0_TX && SAMV7_SSC0_RX
	---help---
		If both the receiver and transmitter are enabled, then the SSC can
		be configured in loopback mode.  This setting selects SSC loopback
		and will cause the LOOP bit to be set in the SSC_RFMR register. In
		this case, RD is connected to TD, RF is connected to TF and RK is
		connected to TK.

endif # SAMV7_SSC0

if SAMV7_SSC1
comment "SSC1 Configuration"

config SAMV7_SSC1_DATALEN
	int "Data width (bits)"
	default 16
	---help---
		Data width in bits.  This is a default value and may be change
		via the I2S interface

config SAMV7_SSC1_RX
	bool "Enable I2C receiver"
	default n
	---help---
		Enable I2S receipt logic

if SAMV7_SSC1_RX

choice
	prompt "Receiver clock source"
	default SAMV7_SSC1_RX_MCKDIV

config SAMV7_SSC1_RX_RKINPUT
	bool "RK input"
	---help---
		The SSC receiver clock is an external clock provided on the RK input
		pin.  Sample rate determined by the external clock frequency.

config SAMV7_SSC1_RX_TXCLK
	bool "Transmitter Clock"
	---help---
		The SSC receiver clock is transmitter clock.  RX sample rate is the same
		as the TX sample rate.

config SAMV7_SSC1_RX_MCKDIV
	bool "MCK/2"
	---help---
		The SSC receiver clock is the MCK/2 divided by a up to 4095.  Desired
		sample rate must be provided below.

endchoice # Receiver clock source

if !SAMV7_SSC1_RX_RKINPUT
choice
	prompt "Receiver output clock"
	default SAMV7_SSC1_RX_RKOUTPUT_NONE

config SAMV7_SSC1_RX_RKOUTPUT_NONE
	bool "None"

config SAMV7_SSC1_RX_RKOUTPUT_CONT
	bool "Continuous"

config SAMV7_SSC1_RX_RKOUTPUT_XFR
	bool "Only during transfers"

endchoice # Receiver output clock
endif # !SAMV7_SSC1_RX_RKINPUT

config SAMV7_SSC1_RX_FSLEN
	int "Receive Frame Sync Length"
	default 1
	range 1 255
	---help---
		This setting determines the pulse length of the Receive Frame Sync
		signal in units of receive clock periods.

config SAMV7_SSC1_RX_STTDLY
	int "Receive Start Delay Length"
	default 0
	range 0 255
	---help---
		This setting determines the pulse length to the start of data of
		receive clock periods.  It must be greater than or equal to the RX
		frame synch length.  Zero means no start delay.

endif # SAMV7_SSC1_RX

config SAMV7_SSC1_TX
	bool "Enable I2C transmitter"
	default n
	---help---
		Enable I2S transmission logic

if SAMV7_SSC1_TX

choice
	prompt "Transmitter clock source"
	default SAMV7_SSC1_TX_MCKDIV

config SAMV7_SSC1_TX_TKINPUT
	bool "TK input"
	---help---
		The SSC transmitter clock is an external clock provided on the TK input
		pin.  Sample rate determined by the external clock frequency.

config SAMV7_SSC1_TX_RXCLK
	bool "Receiver Clock"
	---help---
		The SSC transmitter clock is receiver clock.  TX sample rate is the same
		as the RX sample rate.

config SAMV7_SSC1_TX_MCKDIV
	bool "MCK/2"
	---help---
		The SSC transmitter clock is the MCK/2 divided by a up to 4095.  Desired
		sample rate must be provided below.

endchoice # Transmitter clock source

if !SAMV7_SSC1_TX_TKINPUT
choice
	prompt "Transmitter output clock"
	default SAMV7_SSC1_TX_TKOUTPUT_NONE

config SAMV7_SSC1_TX_TKOUTPUT_NONE
	bool "None"

config SAMV7_SSC1_TX_TKOUTPUT_CONT
	bool "Continuous"

config SAMV7_SSC1_TX_TKOUTPUT_XFR
	bool "Only during transfers"

endchoice # Receiver output clock
endif # !SAMV7_SSC1_TX_TKINPUT

config SAMV7_SSC1_TX_FSLEN
	int "Receive Frame Sync Length"
	default 1
	range 0 255
	---help---
		This setting define the length of the Transmit Frame Sync signal in
		units of transmit clock periods.  A value of zero disables this
		feature.  In that case the TD line is driven with the default value
		during the Transmit Frame Sync signal.

config SAMV7_SSC1_TX_STTDLY
	int "Transmit Start Delay Length"
	default 0
	range 0 255
	---help---
		This setting determines the pulse length to the start of data in
		transmit clock periods.  It must be greater than or equal to the RX
		frame synch length.  Zero means no start delay.

endif # SAMV7_SSC1_TX

config SAMV7_SSC1_MCKDIV_SAMPLERATE
	int "Sample rate"
	default 48000
	depends on SAMV7_SSC1_RX_MCKDIV || SAMV7_SSC1_TX_MCKDIV
	---help---
		If the either the receiver or transmitter clock is provided by MCK/2 divided
		down, then the sample rate must be provided.  The bit rate will be the product
		of the sample rate and the data width.  The SSC driver will determine the best
		divider to obtain that bit rate (up to 4095).  If the bit rate can be realized
		by dividing down the MCK/2, a compile time error will occur.

config SAMV7_SSC1_LOOPBACK
	bool "Loopback mode"
	default n
	depends on SAMV7_SSC1_TX && SAMV7_SSC1_RX
	---help---
		If both the receiver and transmitter are enabled, then the SSC can
		be configured in loopback mode.  This setting selects SSC loopback
		and will cause the LOOP bit to be set in the SSC_RFMR register. In
		this case, RD is connected to TD, RF is connected to TF and RK is
		connected to TK.

endif # SAMV7_SSC1

config SAMV7_SSC_DMADEBUG
	bool "SSC DMA transfer debug"
	depends on DEBUG && DEBUG_DMA
	default n
	---help---
		Enable special debug instrumentation analyze SSC DMA data transfers.
		This logic is as non-invasive as possible:  It samples DMA
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.

config SAMV7_SSC_REGDEBUG
	bool "SSC Register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level SSC device debug information.
		Very invasive! Requires also DEBUG.

config SAMV7_SSC_QDEBUG
	bool "SSC Queue debug"
	depends on DEBUG_I2S
	default n
	---help---
		Enable instrumentation to debug audio buffer queue logic.

config SAMV7_SSC_DUMPBUFFERS
	bool "Dump Buffers"
	depends on DEBUG_I2S
	default n
	---help---
		Enable instrumentation to dump TX and RX buffers.

endmenu # SSC Configuration

menu "HSMCI device driver options"
	depends on SAMV7_HSMCI

config SAMV7_HSMCI_RDPROOF
	bool "Read Proof Enable"
	default n
	---help---
		Enabling Read Proof allows to stop the HSMCI Clock during read
		access if the internal FIFO is full. This will guarantee data
		integrity, not bandwidth.

config SAMV7_HSMCI_WRPROOF
	bool "Write Proof Enable"
	default n
	---help---
		Enabling Write Proof allows to stop the HSMCI Clock during write
		access if the internal FIFO is full. This will guarantee data
		integrity, not bandwidth.

config SAMV7_HSMCI_XFRDEBUG
	bool "HSMCI transfer debug"
	depends on DEBUG_FS && DEBUG_VERBOSE
	default n
	---help---
		Enable special debug instrumentation analyze HSMCI data transfers.
		This logic is as non-invasive as possible:  It samples HSMCI
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.  If DEBUG_DMA is also
		enabled, then DMA register will be collected as well.  Requires also
		DEBUG_FS and DEBUG_VERBOSE.

config SAMV7_HSMCI_CMDDEBUG
	bool "HSMCI command debug"
	depends on DEBUG_FS && DEBUG_VERBOSE
	default n
	---help---
		Enable special debug instrumentation analyze HSMCI commands. This
		logic is as non-invasive as possible:  It samples HSMCI registers at
		key points in the data transfer and then dumps all of the registers
		at the end of the transfer.  If DEBUG_DMA is also enabled, then DMA
		register will be collected as well.  Requires also DEBUG_FS and
		DEBUG_VERBOSE.

config SAMV7_HSMCI_REGDEBUG
	bool "HSMCI Register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level HSCMI device debug information.
		Very invasive! Requires also DEBUG.

endmenu # HSMCI device driver options

menu "EMAC device driver options"
	depends on SAMV7_EMAC0

config SAMV7_EMAC0_NRXBUFFERS
	int "Number of RX buffers"
	default 16
	---help---
		EMAC buffer memory is segmented into 128 byte units (not
		configurable).  This setting provides the number of such 128 byte
		units used for reception.  This is also equal to the number of RX
		descriptors that will be allocated  The selected value must be an
		even power of 2.

config SAMV7_EMAC0_NTXBUFFERS
	int "Number of TX buffers"
	default 8
	---help---
		EMAC buffer memory is segmented into full Ethernet packets (size
		NET_BUFSIZE bytes).  This setting provides the number of such packets
		that can be in flight.  This is also equal to the number of TX
		descriptors that will be allocated.

config SAMV7_EMAC0_PHYADDR
	int "PHY address"
	default 1
	---help---
		The 5-bit address of the PHY on the board.  Default: 1

config SAMV7_EMAC0_PHYINIT
	bool "Board-specific PHY Initialization"
	default n
	---help---
		Some boards require specialized initialization of the PHY before it can be used.
		This may include such things as configuring GPIOs, resetting the PHY, etc.  If
		SAMV7_EMAC0_PHYINIT is defined in the configuration then the board specific logic must
		provide sam_phyinitialize();  The SAMV7 EMAC driver will call this function
		one time before it first uses the PHY.

choice
	prompt "PHY interface"
	default SAMV7_EMAC0_MII

config SAMV7_EMAC0_MII
	bool "MII"
	---help---
		Support Ethernet MII interface (vs RMII).

config SAMV7_EMAC0_RMII
	bool "RMII"
	depends on !ARCH_CHIP_SAM4E
	---help---
		Support Ethernet RMII interface (vs MII).

endchoice # PHY interface

config SAMV7_EMAC0_CLAUSE45
	bool "Clause 45 MII"
	depends on SAMV7_EMAC0_MII
	---help---
		MDIO was originally defined in Clause 22 of IEEE RFC802.3. In the
		original specification, a single MDIO interface is able to access up
		to 32 registers in 32 different PHY devices.  To meet the needs the
		expanding needs of 10-Gigabit Ethernet devices, Clause 45 of the
		802.3ae specification provided the following additions to MDIO:

		- Ability to access 65,536 registers in 32 different devices on
		  32 different ports
		- Additional OP-code and ST-code for Indirect Address register
		  access for 10 Gigabit Ethernet
		- End-to-end fault signaling
		- Multiple loopback points
		- Low voltage electrical specification

		By default, Clause 22 PHYs will be supported unless this option is
		selected.

config SAMV7_EMAC0_AUTONEG
	bool "Use autonegotiation"
	default y
	---help---
		Use PHY autonegotiation to determine speed and mode

config SAMV7_EMAC0_ETHFD
	bool "Full duplex"
	default n
	depends on !SAMV7_EMAC0_AUTONEG
	---help---
		If SAMV7_EMAC0_AUTONEG is not defined, then this may be defined to select full duplex
		mode. Default: half-duplex

config SAMV7_EMAC0_ETH100MBPS
	bool "100 Mbps"
	default n
	depends on !SAMV7_EMAC0_AUTONEG
	---help---
		If SAMV7_EMAC0_AUTONEG is not defined, then this may be defined to select 100 MBps
		speed.  Default: 10 Mbps

config SAMV7_EMAC0_PHYSR
	int "PHY Status Register Address (decimal)"
	depends on SAMV7_EMAC0_AUTONEG
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  The PHY status register
		address may diff from PHY to PHY.  This configuration sets the address of
		the PHY status register.

config SAMV7_EMAC0_PHYSR_ALTCONFIG
	bool "PHY Status Alternate Bit Layout"
	default n
	depends on SAMV7_EMAC0_AUTONEG
	---help---
		Different PHYs present speed and mode information in different ways.  Some
		will present separate information for speed and mode (this is the default).
		Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
		full/half duplex indication. This options selects an alternative representation
		where speed and mode information are combined.  This might mean, for example,
		separate bits for 10HD, 100HD, 10FD and 100FD.

if SAMV7_EMAC0_AUTONEG
if SAMV7_EMAC0_PHYSR_ALTCONFIG

config SAMV7_EMAC0_PHYSR_ALTMODE
	hex "PHY Mode Mask"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This provide bit mask
		for isolating the speed and full/half duplex mode bits.

config SAMV7_EMAC0_PHYSR_10HD
	hex "10MBase-T Half Duplex Value"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This is the value
		under the bit mask that represents the 10Mbps, half duplex setting.

config SAMV7_EMAC0_PHYSR_100HD
	hex "100Base-T Half Duplex Value"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This is the value
		under the bit mask that represents the 100Mbps, half duplex setting.

config SAMV7_EMAC0_PHYSR_10FD
	hex "10Base-T Full Duplex Value"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This is the value
		under the bit mask that represents the 10Mbps, full duplex setting.

config SAMV7_EMAC0_PHYSR_100FD
	hex "100Base-T Full Duplex Value"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This is the value
		under the bit mask that represents the 100Mbps, full duplex setting.

endif # SAMV7_EMAC0_PHYSR_ALTCONFIG
if !SAMV7_EMAC0_PHYSR_ALTCONFIG

config SAMV7_EMAC0_PHYSR_SPEED
	hex "PHY Speed Mask"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This provides bit mask
		for isolating the 10 or 100MBps speed indication.

config SAMV7_EMAC0_PHYSR_100MBPS
	hex "PHY 100Mbps Speed Value"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This provides the value
		of the speed bit(s) indicating 100MBps speed.

config SAMV7_EMAC0_PHYSR_MODE
	hex "PHY Mode Mask"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This provides the
		bit mask for isolating the full or half duplex mode bits.

config SAMV7_EMAC0_PHYSR_FULLDUPLEX
	hex "PHY Full Duplex Mode Value"
	---help---
		This must be provided if SAMV7_EMAC0_AUTONEG is defined.  This provides the
		value of the mode bits indicating full duplex mode.

endif # !SAMV7_EMAC0_PHYSR_ALTCONFIG
endif # SAMV7_EMAC0_AUTONEG

# These apply to both EMAC0 and EMAC1 (but are in the EMAC0 menu for now
# because there is not yet any SAMV7 chip that supports two Ethernet MACS

config SAMV7_EMAC0_ISETH0
	bool
	default y

config SAMV7_EMAC_PREALLOCATE
	bool "Preallocate buffers"
	default n
	---help---
		Buffer an descriptor many may either be allocated from the memory
		pool or pre-allocated to lie in .bss.  This options selected pre-
		allocated buffer memory.

config SAMV7_EMAC_NBC
	bool "Disable Broadcast"
	default n
	---help---
		Select to disable receipt of broadcast packets.

config SAMV7_EMAC_DEBUG
	bool "Force EMAC0/1 DEBUG"
	default n
	depends on DEBUG && !DEBUG_NET
	---help---
		This option will force debug output from EMAC driver even without
		network debug output enabled.  This is not normally something
		that would want to do but is convenient if you are debugging the
		driver and do not want to get overloaded with other
		network-related debug output.

config SAMV7_EMAC_REGDEBUG
	bool "Register-Level Debug"
	default n
	depends on DEBUG
	---help---
		Enable very low-level register access debug.  Depends on DEBUG.

endmenu # EMAC0 device driver options

menu "USB High Speed Device Controller driver (DCD) options"
	depends on SAMV7_USBDEVHS

config SAMV7_USBHS_SCATTERGATHER
	bool
	default n
	depends on EXPERIMENTAL
	---help---
		Scatter gather DMA is not yet supported

config SAMV7_USBHS_NDTDS
	int "Number of USBHS DMA transfer descriptors"
	default 8
	---help---
		DMA transfer descriptors are allocated in a pool at boot time.  This
		setting provides the number of DMA transfer descriptors to be
		allocated.

config SAMV7_USBHS_PREALLOCATE
	bool "Pre-allocate DMA transfer descriptors"
	default y
	---help---
		If this option is selected then DMA transfer descriptors will be
		pre-allocated in .bss.  Otherwise, the descriptors will be allocated
		at start-up time with kmm_malloc().  This might be important if a larger
		memory pool is available after startup.

config SAMV7_USBHS_REGDEBUG
	bool "Enable low-level USBHS register debug"
	default n
	depends on DEBUG

endmenu # USB High Speed Device Controller driver (DCD) options