1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
|
#
# For a description of the syntax of this configuration file,
# see misc/tools/kconfig-language.txt.
#
comment "STM32 Configuration Options"
choice
prompt "STM32 Chip Selection"
default ARCH_CHIP_STM32F103ZE
depends on ARCH_CHIP_STM32
config ARCH_CHIP_STM32L151C6
bool "STM32L151C6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151C8
bool "STM32L151C8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151CB
bool "STM32L151CB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151R6
bool "STM32L151R6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151R8
bool "STM32L151R8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151RB
bool "STM32L151RB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151V6
bool "STM32L151V6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151V8
bool "STM32L151V8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L151VB
bool "STM32L151VB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM
config ARCH_CHIP_STM32L152C6
bool "STM32L152C6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x16 LCD interface
config ARCH_CHIP_STM32L152C8
bool "STM32L152C8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x16 LCD interface
config ARCH_CHIP_STM32L152CB
bool "STM32L152CB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x16 LCD interface
config ARCH_CHIP_STM32L152R6
bool "STM32L152R6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152R8
bool "STM32L152R8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152RB
bool "STM32L152RB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x32/8x28 LCD interface
config ARCH_CHIP_STM32L152V6
bool "STM32L152V6"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152V8
bool "STM32L152V8"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L152VB
bool "STM32L152VB"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
---help---
STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPRROM with
4x44/8x40 LCD interface
config ARCH_CHIP_STM32L162ZD
bool "STM32L162ZD"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
select STM32_HIGHDENSITY
select STM32_HAVE_AES
---help---
STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPRROM with
8x40 LCD interface
config ARCH_CHIP_STM32L162VE
bool "STM32L162VE"
select ARCH_CORTEXM3
select STM32_STM32L15XX
select STM32_ENERGYLITE
select STM32_HIGHDENSITY
select STM32_HAVE_AES
---help---
STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPRROM with
8x40 LCD interface
config ARCH_CHIP_STM32F100C8
bool "STM32F100C8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100CB
bool "STM32F100CB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100R8
bool "STM32F100R8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100RB
bool "STM32F100RB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100RC
bool "STM32F100RC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100RD
bool "STM32F100RD"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100RE
bool "STM32F100RE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100V8
bool "STM32F100V8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100VB
bool "STM32F100VB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100VC
bool "STM32F100VC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100VD
bool "STM32F100VD"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100VE
bool "STM32F100VE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F102CB
bool "STM32F102CB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_USBACCESSLINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103T8
bool "STM32F103T8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103TB
bool "STM32F103TB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103C4
bool "STM32F103C4"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_LOWDENSITY
config ARCH_CHIP_STM32F103C8
bool "STM32F103C8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103CB
bool "STM32F103CB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103R8
bool "STM32F103R8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103RB
bool "STM32F103RB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103RC
bool "STM32F103RC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103RD
bool "STM32F103RD"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103RE
bool "STM32F103RE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103RG
bool "STM32F103RG"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103V8
bool "STM32F103V8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103VB
bool "STM32F103VB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_MEDIUMDENSITY
config ARCH_CHIP_STM32F103VC
bool "STM32F103VC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103VE
bool "STM32F103VE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103ZE
bool "STM32F103ZE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F105VB
bool "STM32F105VBT7"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_CONNECTIVITYLINE
config ARCH_CHIP_STM32F107VC
bool "STM32F107VC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_CONNECTIVITYLINE
config ARCH_CHIP_STM32F207IG
bool "STM32F207IG"
select ARCH_CORTEXM3
select STM32_STM32F20XX
select STM32_STM32F207
config ARCH_CHIP_STM32F207ZE
bool "STM32F207ZE"
select ARCH_CORTEXM3
select STM32_STM32F20XX
select STM32_STM32F207
config ARCH_CHIP_STM32F302CB
bool "STM32F302CB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302CC
bool "STM32F302CC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302RB
bool "STM32F302RB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302RC
bool "STM32F302RC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302VB
bool "STM32F302VB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302VC
bool "STM32F302VC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303CB
bool "STM32F303CB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303CC
bool "STM32F303CC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303RB
bool "STM32F303RB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303RC
bool "STM32F303RC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303VB
bool "STM32F303VB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303VC
bool "STM32F303VC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372C8
bool "STM32F372C8"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372R8
bool "STM32F372R8"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372V8
bool "STM32F372V8"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372CB
bool "STM32F372CB"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372RB
bool "STM32F372RB"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372VB
bool "STM32F372VB"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372CC
bool "STM32F372CC"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372RC
bool "STM32F372RC"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F372VC
bool "STM32F372VC"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373C8
bool "STM32F373C8"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373R8
bool "STM32F373R8"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373V8
bool "STM32F373V8"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373CB
bool "STM32F373CB"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373RB
bool "STM32F373RB"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373VB
bool "STM32F373VB"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373CC
bool "STM32F373CC"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373RC
bool "STM32F373RC"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F373VC
bool "STM32F373VC"
select ARCH_CORTEXM4
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F401RE
bool "STM32F401RE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F401
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F411RE
bool "STM32F411RE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F411
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405RG
bool "STM32F405RG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F405
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405VG
bool "STM32F405VG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F405
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405ZG
bool "STM32F405ZG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F405
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407VE
bool "STM32F407VE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407VG
bool "STM32F407VG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407ZE
bool "STM32F407ZE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407ZG
bool "STM32F407ZG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407IE
bool "STM32F407IE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407IG
bool "STM32F407IG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F407
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427V
bool "STM32F427V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427Z
bool "STM32F427Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427I
bool "STM32F427I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429V
bool "STM32F429V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429Z
bool "STM32F429Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429I
bool "STM32F429I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429B
bool "STM32F429B"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429N
bool "STM32F429N"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
endchoice
# This is really 15XX/16XX, but we treat the two the same.
config STM32_STM32L15XX
bool
default n
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY
config STM32_ENERGYLITE
bool
default n
select STM32_HAVE_USBDEV
select STM32_HAVE_USART3
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_ADC2
config STM32_STM32F10XX
bool
default n
select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY
select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY
config STM32_VALUELINE
bool
default n
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM12
select STM32_HAVE_TIM13
select STM32_HAVE_TIM14
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
select STM32_HAVE_ADC2
select STM32_HAVE_SPI2 if STM32_HIGHDENSITY
select STM32_HAVE_SPI3 if STM32_HIGHDENSITY
config STM32_CONNECTIVITYLINE
bool
default n
select STM32_HAVE_OTGFS
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
config STM32_PERFORMANCELINE
bool
default n
select STM32_HAVE_USBDEV
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_CAN1
config STM32_USBACCESSLINE
bool
default n
select STM32_HAVE_USBDEV
select STM32_HAVE_FSMC
select STM32_HAVE_USART3
select STM32_HAVE_SPI2
config STM32_HIGHDENSITY
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
config STM32_MEDIUMDENSITY
bool
default n
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
config STM32_LOWDENSITY
bool
default n
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_ADC2
select STM32_HAVE_CAN1 if !STM32_VALUELINE
config STM32_STM32F20XX
bool
default n
config STM32_STM32F207
bool
default n
select STM32_HAVE_OTGFS
select STM32_HAVE_FSMC
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_TIM12
select STM32_HAVE_TIM13
select STM32_HAVE_TIM14
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
config STM32_STM32F30XX
bool
default n
select STM32_HAVE_USBDEV
select STM32_HAVE_CCM
select STM32_HAVE_TIM1
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_ADC4
select STM32_HAVE_CAN1
select STM32_HAVE_SPI2
config STM32_STM32F37XX
bool
default n
select STM32_HAVE_USBDEV
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM15
select STM32_HAVE_TIM16
select STM32_HAVE_TIM17
select STM32_HAVE_CAN1
select STM32_HAVE_USART3
config STM32_STM32F40XX
bool
default n
select STM32_HAVE_OTGFS
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
config STM32_STM32F401
bool
default n
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
config STM32_STM32F411
bool
default n
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
config STM32_STM32F405
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_TIM12
select STM32_HAVE_TIM13
select STM32_HAVE_TIM14
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_RNG
config STM32_STM32F407
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_TIM12
select STM32_HAVE_TIM13
select STM32_HAVE_TIM14
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
# This is really 427/437, but we treat the two the same.
config STM32_STM32F427
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_UART7
select STM32_HAVE_UART8
select STM32_HAVE_TIM1
select STM32_HAVE_TIM5
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_TIM12
select STM32_HAVE_TIM13
select STM32_HAVE_TIM14
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
# This is really 429/439, but we treat the two the same.
config STM32_STM32F429
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
select STM32_HAVE_UART4
select STM32_HAVE_UART5
select STM32_HAVE_USART6
select STM32_HAVE_UART7
select STM32_HAVE_UART8
select STM32_HAVE_TIM1
select STM32_HAVE_TIM6
select STM32_HAVE_TIM7
select STM32_HAVE_TIM8
select STM32_HAVE_TIM9
select STM32_HAVE_TIM10
select STM32_HAVE_TIM11
select STM32_HAVE_TIM12
select STM32_HAVE_TIM13
select STM32_HAVE_TIM14
select STM32_HAVE_ADC2
select STM32_HAVE_ADC3
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4
select STM32_HAVE_SPI5
select STM32_HAVE_SPI6
config STM32_DFU
bool "DFU bootloader"
default n
depends on !STM32_VALUELINE
---help---
Configure and position code for use with the STMicro DFU bootloader. Do
not select this option if you will load code using JTAG/SWM.
menu "STM32 Peripheral Support"
# These "hidden" settings determine is a peripheral option is available for the
# selection MCU
config STM32_HAVE_CCM
bool
default n
config STM32_HAVE_USBDEV
bool
default n
config STM32_HAVE_OTGFS
bool
default n
config STM32_HAVE_FSMC
bool
default n
config STM32_HAVE_USART3
bool
default n
config STM32_HAVE_UART4
bool
default n
config STM32_HAVE_UART5
bool
default n
config STM32_HAVE_USART6
bool
default n
config STM32_HAVE_UART7
bool
default n
config STM32_HAVE_UART8
bool
default n
config STM32_HAVE_TIM1
bool
default n
config STM32_HAVE_TIM5
bool
default n
config STM32_HAVE_TIM6
bool
default n
config STM32_HAVE_TIM7
bool
default n
config STM32_HAVE_TIM8
bool
default n
config STM32_HAVE_TIM9
bool
default n
config STM32_HAVE_TIM10
bool
default n
config STM32_HAVE_TIM11
bool
default n
config STM32_HAVE_TIM12
bool
default n
config STM32_HAVE_TIM13
bool
default n
config STM32_HAVE_TIM14
bool
default n
config STM32_HAVE_TIM15
bool
default n
config STM32_HAVE_TIM16
bool
default n
config STM32_HAVE_TIM17
bool
default n
config STM32_HAVE_ADC2
bool
default n
config STM32_HAVE_ADC3
bool
default n
config STM32_HAVE_ADC4
bool
default n
config STM32_HAVE_CAN1
bool
default n
config STM32_HAVE_CAN2
bool
default n
config STM32_HAVE_RNG
bool
default n
config STM32_HAVE_ETHMAC
bool
default n
config STM32_HAVE_SPI2
bool
default n
config STM32_HAVE_SPI3
bool
default n
config STM32_HAVE_SPI4
bool
default n
config STM32_HAVE_SPI5
bool
default n
config STM32_HAVE_SPI6
bool
default n
# These are the peripheral selections proper
config STM32_ADC1
bool "ADC1"
default n
select STM32_ADC
config STM32_ADC2
bool "ADC2"
default n
select STM32_ADC
depends on STM32_HAVE_ADC2
config STM32_ADC3
bool "ADC3"
default n
select STM32_ADC
depends on STM32_HAVE_ADC3
config STM32_ADC4
bool "ADC4"
default n
select STM32_ADC
depends on STM32_HAVE_ADC4
config STM32_COMP
bool "COMP"
default n
depends on STM32_STM32L15XX
config STM32_BKP
bool "BKP"
default n
depends on STM32_STM32F10XX
config STM32_BKPSRAM
bool "Enable BKP RAM Domain"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
config STM32_CAN1
bool "CAN1"
default n
select CAN
select STM32_CAN
depends on STM32_HAVE_CAN1
config STM32_CAN2
bool "CAN2"
default n
select CAN
select STM32_CAN
depends on STM32_HAVE_CAN2
config STM32_CCMDATARAM
bool "CMD/DATA RAM"
default n
depends on STM32_STM32F40XX
config STM32_AES
bool "128-bit AES"
default n
depends on STM32_HAVE_AES
select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST
select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST
config STM32_CEC
bool "CEC"
default n
depends on STM32_VALUELINE
config STM32_CRC
bool "CRC"
default n
config STM32_CRYP
bool "CRYP"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
config STM32_DMA1
bool "DMA1"
default n
select ARCH_DMA
config STM32_DMA2
bool "DMA2"
default n
select ARCH_DMA
depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY)
config STM32_DAC1
bool "DAC1"
default n
select STM32_DAC
config STM32_DAC2
bool "DAC2"
default n
select STM32_DAC
config STM32_DCMI
bool "DCMI"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
config STM32_ETHMAC
bool "Ethernet MAC"
default n
depends on STM32_HAVE_ETHMAC
select NETDEVICES
select ARCH_HAVE_PHY
config STM32_FSMC
bool "FSMC"
default n
depends on STM32_HAVE_FSMC
config STM32_HASH
bool "HASH"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
config STM32_I2C1
bool "I2C1"
default n
select STM32_I2C
config STM32_I2C2
bool "I2C2"
default n
depends on !(STM32_STM32F10XX && STM32_LOWDENSITY)
select STM32_I2C
config STM32_I2C3
bool "I2C3"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX
select STM32_I2C
config STM32_LTDC
bool "LTDC"
default n
depends on STM32_STM32F429
---help---
The STM32 LTDC is an LCD-TFT Display Controller available on
the STM32F429 and STM32F439 devices. It is a standard parallel
video interface (HSYNC, VSYNC, etc.) for controlling TFT
LCD displays.
config STM32_DMA2D
bool "DMA2D"
default n
depends on STM32_STM32F429
---help---
The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation
available on the STM32F429 and STM32F439 devices.
config STM32_OTGFS
bool "OTG FS"
default n
depends on STM32_HAVE_OTGFS
config STM32_OTGHS
bool "OTG HS"
default n
depends on STM32_STM32F207 || STM32_STM32F40XX || STM32_STM32F429
config STM32_PWR
bool "PWR"
default n
config STM32_RNG
bool "RNG"
default n
depends on STM32_HAVE_RNG
select ARCH_HAVE_RNG
config STM32_SDIO
bool "SDIO"
default n
depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE
select ARCH_HAVE_SDIO
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
select SDIO_PREFLIGHT
config STM32_SPI1
bool "SPI1"
default n
select SPI
select STM32_SPI
config STM32_SPI2
bool "SPI2"
default n
depends on STM32_HAVE_SPI2
select SPI
select STM32_SPI
config STM32_SPI3
bool "SPI3"
default n
depends on STM32_HAVE_SPI3
select SPI
select STM32_SPI
config STM32_SPI4
bool "SPI4"
default n
depends on STM32_HAVE_SPI4
select SPI
select STM32_SPI
config STM32_SPI5
bool "SPI5"
default n
depends on STM32_HAVE_SPI5
select SPI
select STM32_SPI
config STM32_SPI6
bool "SPI6"
default n
depends on STM32_HAVE_SPI6
select SPI
select STM32_SPI
config STM32_SYSCFG
bool "SYSCFG"
default y
depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F37XX || STM32_STM32F207 || STM32_STM32F40XX
config STM32_TIM1
bool "TIM1"
default n
depends on STM32_HAVE_TIM1
config STM32_TIM2
bool "TIM2"
default n
config STM32_TIM3
bool "TIM3"
default n
config STM32_TIM4
bool "TIM4"
default n
config STM32_TIM5
bool "TIM5"
default n
depends on STM32_HAVE_TIM5
config STM32_TIM6
bool "TIM6"
default n
depends on STM32_HAVE_TIM6
config STM32_TIM7
bool "TIM7"
default n
depends on STM32_HAVE_TIM7
config STM32_TIM8
bool "TIM8"
default n
depends on STM32_HAVE_TIM8
config STM32_TIM9
bool "TIM9"
default n
depends on STM32_HAVE_TIM9
config STM32_TIM10
bool "TIM10"
default n
depends on STM32_HAVE_TIM10
config STM32_TIM11
bool "TIM11"
default n
depends on STM32_HAVE_TIM11
config STM32_TIM12
bool "TIM12"
default n
depends on STM32_HAVE_TIM12
config STM32_TIM13
bool "TIM13"
default n
depends on STM32_HAVE_TIM13
config STM32_TIM14
bool "TIM14"
default n
depends on STM32_HAVE_TIM14
config STM32_TIM15
bool "TIM15"
default n
depends on STM32_HAVE_TIM15
config STM32_TIM16
bool "TIM16"
default n
depends on STM32_HAVE_TIM16
config STM32_TIM17
bool "TIM17"
default n
depends on STM32_HAVE_TIM17
config STM32_TSC
bool "TSC"
default n
depends on STM32_STM32F30XX
config STM32_USART1
bool "USART1"
default n
select ARCH_HAVE_USART1
select ARCH_HAVE_SERIAL_TERMIOS
select STM32_USART
config STM32_USART2
bool "USART2"
default n
select ARCH_HAVE_USART2
select ARCH_HAVE_SERIAL_TERMIOS
select STM32_USART
config STM32_USART3
bool "USART3"
default n
depends on STM32_HAVE_USART3
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_USART3
select STM32_USART
config STM32_UART4
bool "UART4"
default n
depends on STM32_HAVE_UART4
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_UART4
select STM32_USART
config STM32_UART5
bool "UART5"
default n
depends on STM32_HAVE_UART5
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_UART5
select STM32_USART
config STM32_USART6
bool "USART6"
default n
depends on STM32_HAVE_USART6
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_USART6
select STM32_USART
config STM32_UART7
bool "UART7"
default n
depends on STM32_HAVE_UART7
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_UART7
select STM32_USART
config STM32_UART8
bool "UART8"
default n
depends on STM32_HAVE_UART8
select ARCH_HAVE_SERIAL_TERMIOS
select ARCH_HAVE_UART8
select STM32_USART
config STM32_USB
bool "USB Device"
default n
depends on STM32_HAVE_USBDEV
select USBDEV
config STM32_LCD
bool "Segment LCD"
default n
depends on STM32_STM32L15XX
config STM32_IWDG
bool "IWDG"
default n
select WATCHDOG
config STM32_WWDG
bool "WWDG"
default n
select WATCHDOG
endmenu
config STM32_ADC
bool
config STM32_DAC
bool
config STM32_SPI
bool
config STM32_I2C
bool
config STM32_CAN
bool
menu "Alternate Pin Mapping"
choice
prompt "CAN1 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_CAN1
default STM32_CAN1_NO_REMAP
config STM32_CAN1_NO_REMAP
bool "No pin remapping"
config STM32_CAN1_REMAP1
bool "CAN1 alternate pin remapping #1"
config STM32_CAN1_REMAP2
bool "CAN1 alternate pin remapping #2"
endchoice
config STM32_CAN2_REMAP
bool "CAN2 Alternate Pin Mapping"
default n
depends on STM32_CONNECTIVITYLINE && STM32_CAN2
config STM32_CEC_REMAP
bool "CEC Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_CEC
config STM32_ETH_REMAP
bool "Ethernet Alternate Pin Mapping"
default n
depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC
config STM32_I2C1_REMAP
bool "I2C1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_I2C1
config STM32_SPI1_REMAP
bool "SPI1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_SPI1
config STM32_SPI3_REMAP
bool "SPI3 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE
choice
prompt "TIM1 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_TIM1
default STM32_TIM1_NO_REMAP
config STM32_TIM1_NO_REMAP
bool "No pin remapping"
config STM32_TIM1_FULL_REMAP
bool "Full pin remapping"
config STM32_TIM1_PARTIAL_REMAP
bool "Partial pin remapping"
endchoice
choice
prompt "TIM2 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_TIM2
default STM32_TIM2_NO_REMAP
config STM32_TIM2_NO_REMAP
bool "No pin remapping"
config STM32_TIM2_FULL_REMAP
bool "Full pin remapping"
config STM32_TIM2_PARTIAL_REMAP_1
bool "Partial pin remapping #1"
config STM32_TIM2_PARTIAL_REMAP_2
bool "Partial pin remapping #2"
endchoice
choice
prompt "TIM3 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_TIM3
default STM32_TIM3_NO_REMAP
config STM32_TIM3_NO_REMAP
bool "No pin remapping"
config STM32_TIM3_FULL_REMAP
bool "Full pin remapping"
config STM32_TIM3_PARTIAL_REMAP
bool "Partial pin remapping"
endchoice
config STM32_TIM4_REMAP
bool "TIM4 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM4
config STM32_TIM9_REMAP
bool "TIM9 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM9
config STM32_TIM10_REMAP
bool "TIM10 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM10
config STM32_TIM11_REMAP
bool "TIM11 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM11
config STM32_TIM12_REMAP
bool "TIM12 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM12
config STM32_TIM13_REMAP
bool "TIM13 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM13
config STM32_TIM14_REMAP
bool "TIM14 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM14
config STM32_TIM15_REMAP
bool "TIM15 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM15
config STM32_TIM16_REMAP
bool "TIM16 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM16
config STM32_TIM17_REMAP
bool "TIM17 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM17
config STM32_USART1_REMAP
bool "USART1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_USART1
config STM32_USART2_REMAP
bool "USART2 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_USART2
choice
prompt "USART3 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_USART3
default STM32_USART3_NO_REMAP
config STM32_USART3_NO_REMAP
bool "No pin remapping"
config STM32_USART3_FULL_REMAP
bool "Full pin remapping"
config STM32_USART3_PARTIAL_REMAP
bool "Partial pin remapping"
endchoice
endmenu
config STM32_FLASH_PREFETCH
bool "Enable FLASH Pre-fetch"
depends on STM32_STM32F207 || STM32_STM32F40XX
default y if STM32_STM32F427 || STM32_STM32F429
default n
---help---
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
properly and enabling this option may interfere with ADC accuracy.
choice
prompt "JTAG Configuration"
default STM32_JTAG_DISABLE
---help---
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled)
config STM32_JTAG_DISABLE
bool "Disable all JTAG clocking"
config STM32_JTAG_FULL_ENABLE
bool "Enable full SWJ (JTAG-DP + SW-DP)"
config STM32_JTAG_NOJNTRST_ENABLE
bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST"
config STM32_JTAG_SW_ENABLE
bool "Set JTAG-DP disabled and SW-DP enabled"
endchoice
config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG
bool "Disable IDLE Sleep (WFI) in debug mode"
default n
---help---
In debug configuration, disables the WFI instruction in the IDLE loop
to prevent the JTAG from disconnecting. With some JTAG debuggers, such
as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI
instruction, the debugger will disconnect, terminating the debug session.
config STM32_FORCEPOWER
bool "Force power"
default n
---help---
Timer and I2C devices may need to the following to force power to be applied
unconditionally at power up. (Otherwise, the device is powered when it is
initialized).
config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
bool "Custom clock configuration"
default n
---help---
Enables special, board-specific STM32 clock configuration.
config STM32_CCMEXCLUDE
bool "Exclude CCM SRAM from the heap"
default y if ARCH_DMA || ELF
depends on STM32_HAVE_CCM
---help---
Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA
and (2) it appears to be impossible to execute ELF modules from CCM
RAM.
config STM32_CCM_PROCFS
bool "CCM PROCFS support"
default n
depends on STM32_CCMEXCLUDE && FS_PROCFS
---help---
Select to build in support for /proc/ccm. Reading from /proc/ccm
will provide statistics about CCM memory use similar to what you
would get from mallinfo() for the user heap.
config STM32_DMACAPABLE
bool "Workaround non-DMA capable memory"
depends on ARCH_DMA
default y if STM32_STM32F40XX && !STM32_CCMEXCLUDE
default n if !STM32_STM32F40XX || STM32_CCMEXCLUDE
---help---
This option enables the DMA interface stm32_dmacapable that can be
used to check if it is possible to do DMA from the selected address.
Drivers then may use this information to determine if they should
attempt the DMA or fall back to a different transfer method.
config STM32_FSMC_SRAM
bool "External SRAM on FSMC"
default n
depends on STM32_FSMC
select ARCH_HAVE_HEAP2
---help---
In addition to internal SRAM, SRAM may also be available through the FSMC.
config STM32_TIM1_PWM
bool "TIM1 PWM"
default n
depends on STM32_TIM1
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 1 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM1
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM1_CHANNEL
int "TIM1 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM1_PWM
---help---
If TIM1 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM2_PWM
bool "TIM2 PWM"
default n
depends on STM32_TIM2
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 2 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM2
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM2_CHANNEL
int "TIM2 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM2_PWM
---help---
If TIM2 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM3_PWM
bool "TIM3 PWM"
default n
depends on STM32_TIM3
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 3 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM3
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM3_CHANNEL
int "TIM3 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM3_PWM
---help---
If TIM3 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM4_PWM
bool "TIM4 PWM"
default n
depends on STM32_TIM4
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 4 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM4
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM4_CHANNEL
int "TIM4 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM4_PWM
---help---
If TIM4 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM5_PWM
bool "TIM5 PWM"
default n
depends on STM32_TIM5
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 5 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM5
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM5_CHANNEL
int "TIM5 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM5_PWM
---help---
If TIM5 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM8_PWM
bool "TIM8 PWM"
default n
depends on STM32_TIM8
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 8 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM8
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM8_CHANNEL
int "TIM8 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM8_PWM
---help---
If TIM8 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM9_PWM
bool "TIM9 PWM"
default n
depends on STM32_TIM9
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 9 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM9
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM9_CHANNEL
int "TIM9 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM9_PWM
---help---
If TIM9 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM10_PWM
bool "TIM10 PWM"
default n
depends on STM32_TIM10
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 10 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM10
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM10_CHANNEL
int "TIM10 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM10_PWM
---help---
If TIM10 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM11_PWM
bool "TIM11 PWM"
default n
depends on STM32_TIM11
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 11 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM11
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM11_CHANNEL
int "TIM11 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM11_PWM
---help---
If TIM11 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM12_PWM
bool "TIM12 PWM"
default n
depends on STM32_TIM12
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 12 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM12
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM12_CHANNEL
int "TIM12 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM12_PWM
---help---
If TIM12 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM13_PWM
bool "TIM13 PWM"
default n
depends on STM32_TIM13
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 13 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM13
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM13_CHANNEL
int "TIM13 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM13_PWM
---help---
If TIM13 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM14_PWM
bool "TIM14 PWM"
default n
depends on STM32_TIM14
select ARCH_HAVE_PWM_PULSECOUNT
---help---
Reserve timer 14 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM14
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM14_CHANNEL
int "TIM14 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM14_PWM
---help---
If TIM14 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM15_PWM
bool "TIM15 PWM"
default n
depends on STM32_TIM15
---help---
Reserve timer 15 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM15
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM15_CHANNEL
int "TIM15 PWM Output Channel"
default 1
range 1 2
depends on STM32_TIM15_PWM
---help---
If TIM15 is enabled for PWM usage, you also need specifies the timer output
channel {1,2}
config STM32_TIM16_PWM
bool "TIM16 PWM"
default n
depends on STM32_TIM16
---help---
Reserve timer 16 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM16
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM16_CHANNEL
int "TIM16 PWM Output Channel"
default 1
range 1 1
depends on STM32_TIM16_PWM
---help---
If TIM16 is enabled for PWM usage, you also need specifies the timer output
channel {1}
config STM32_TIM17_PWM
bool "TIM17 PWM"
default n
depends on STM32_TIM17
---help---
Reserve timer 17 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM17
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM17_CHANNEL
int "TIM17 PWM Output Channel"
default 1
range 1 1
depends on STM32_TIM17_PWM
---help---
If TIM17 is enabled for PWM usage, you also need specifies the timer output
channel {1}
config STM32_TIM1_ADC
bool "TIM1 ADC"
default n
depends on STM32_TIM1 && STM32_ADC
---help---
Reserve timer 1 for use by ADC
Timer devices may be used for different purposes. If STM32_TIM1 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM1 ADC channel"
default STM32_TIM1_ADC1
depends on STM32_TIM1_ADC
config STM32_TIM1_ADC1
bool "TIM1 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM1 to trigger ADC1
config STM32_TIM1_ADC2
bool "TIM1 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM1 to trigger ADC2
config STM32_TIM1_ADC3
bool "TIM1 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM1 to trigger ADC3
endchoice
config STM32_TIM2_ADC
bool "TIM2 ADC"
default n
depends on STM32_TIM2 && STM32_ADC
---help---
Reserve timer 1 for use by ADC
Timer devices may be used for different purposes. If STM32_TIM2 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM2 ADC channel"
default STM32_TIM2_ADC1
depends on STM32_TIM2_ADC
config STM32_TIM2_ADC1
bool "TIM2 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM2 to trigger ADC1
config STM32_TIM2_ADC2
bool "TIM2 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM2 to trigger ADC2
config STM32_TIM2_ADC3
bool "TIM2 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM2 to trigger ADC3
endchoice
config STM32_TIM3_ADC
bool "TIM3 ADC"
default n
depends on STM32_TIM3 && STM32_ADC
---help---
Reserve timer 1 for use by ADC
Timer devices may be used for different purposes. If STM32_TIM3 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM3 ADC channel"
default STM32_TIM3_ADC1
depends on STM32_TIM3_ADC
config STM32_TIM3_ADC1
bool "TIM3 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM3 to trigger ADC1
config STM32_TIM3_ADC2
bool "TIM3 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM3 to trigger ADC2
config STM32_TIM3_ADC3
bool "TIM3 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM3 to trigger ADC3
endchoice
config STM32_TIM4_ADC
bool "TIM4 ADC"
default n
depends on STM32_TIM4 && STM32_ADC
---help---
Reserve timer 1 for use by ADC
Timer devices may be used for different purposes. If STM32_TIM4 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM4 ADC channel"
default STM32_TIM4_ADC1
depends on STM32_TIM4_ADC
config STM32_TIM4_ADC1
bool "TIM4 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM4 to trigger ADC1
config STM32_TIM4_ADC2
bool "TIM4 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM4 to trigger ADC2
config STM32_TIM4_ADC3
bool "TIM4 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM4 to trigger ADC3
endchoice
config STM32_TIM5_ADC
bool "TIM5 ADC"
default n
depends on STM32_TIM5 && STM32_ADC
---help---
Reserve timer 1 for use by ADC
Timer devices may be used for different purposes. If STM32_TIM5 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM5 ADC channel"
default STM32_TIM5_ADC1
depends on STM32_TIM5_ADC
config STM32_TIM5_ADC1
bool "TIM5 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM5 to trigger ADC1
config STM32_TIM5_ADC2
bool "TIM5 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM5 to trigger ADC2
config STM32_TIM5_ADC3
bool "TIM5 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM5 to trigger ADC3
endchoice
config STM32_TIM8_ADC
bool "TIM8 ADC"
default n
depends on STM32_TIM8 && STM32_ADC
---help---
Reserve timer 1 for use by ADC
Timer devices may be used for different purposes. If STM32_TIM8 is
defined then the following may also be defined to indicate that the
timer is intended to be used for ADC conversion. Note that ADC usage
requires two definition: Not only do you have to assign the timer
for used by the ADC, but then you also have to configure which ADC
channel it is assigned to.
choice
prompt "Select TIM8 ADC channel"
default STM32_TIM8_ADC1
depends on STM32_TIM8_ADC
config STM32_TIM8_ADC1
bool "TIM8 ADC channel 1"
depends on STM32_ADC1
select HAVE_ADC1_TIMER
---help---
Reserve TIM8 to trigger ADC1
config STM32_TIM8_ADC2
bool "TIM8 ADC channel 2"
depends on STM32_ADC2
select HAVE_ADC2_TIMER
---help---
Reserve TIM8 to trigger ADC2
config STM32_TIM8_ADC3
bool "TIM8 ADC channel 3"
depends on STM32_ADC3
select HAVE_ADC3_TIMER
---help---
Reserve TIM8 to trigger ADC3
endchoice
config HAVE_ADC1_TIMER
bool
config HAVE_ADC2_TIMER
bool
config HAVE_ADC3_TIMER
bool
config STM32_ADC1_SAMPLE_FREQUENCY
int "ADC1 Sampling Frequency"
default 100
depends on HAVE_ADC1_TIMER
---help---
ADC1 sampling frequency. Default: 100Hz
config STM32_ADC1_TIMTRIG
int "ADC1 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC1_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32_ADC2_SAMPLE_FREQUENCY
int "ADC2 Sampling Frequency"
default 100
depends on HAVE_ADC2_TIMER
---help---
ADC2 sampling frequency. Default: 100Hz
config STM32_ADC2_TIMTRIG
int "ADC2 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC2_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32_ADC3_SAMPLE_FREQUENCY
int "ADC3 Sampling Frequency"
default 100
depends on HAVE_ADC3_TIMER
---help---
ADC3 sampling frequency. Default: 100Hz
config STM32_ADC3_TIMTRIG
int "ADC3 Timer Trigger"
default 0
range 0 4
depends on HAVE_ADC3_TIMER
---help---
Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
config STM32_TIM1_DAC
bool "TIM1 DAC"
default n
depends on STM32_TIM1 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM1 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM1 DAC channel"
default STM32_TIM1_DAC1
depends on STM32_TIM1_DAC
config STM32_TIM1_DAC1
bool "TIM1 DAC channel 1"
---help---
Reserve TIM1 to trigger DAC1
config STM32_TIM1_DAC2
bool "TIM1 DAC channel 2"
---help---
Reserve TIM1 to trigger DAC2
endchoice
config STM32_TIM2_DAC
bool "TIM2 DAC"
default n
depends on STM32_TIM2 && STM32_DAC
---help---
Reserve timer 2 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM2 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM2 DAC channel"
default STM32_TIM2_DAC1
depends on STM32_TIM2_DAC
config STM32_TIM2_DAC1
bool "TIM2 DAC channel 1"
---help---
Reserve TIM2 to trigger DAC1
config STM32_TIM2_DAC2
bool "TIM2 DAC channel 2"
---help---
Reserve TIM2 to trigger DAC2
endchoice
config STM32_TIM3_DAC
bool "TIM3 DAC"
default n
depends on STM32_TIM3 && STM32_DAC
---help---
Reserve timer 3 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM3 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM3 DAC channel"
default STM32_TIM3_DAC1
depends on STM32_TIM3_DAC
config STM32_TIM3_DAC1
bool "TIM3 DAC channel 1"
---help---
Reserve TIM3 to trigger DAC1
config STM32_TIM3_DAC2
bool "TIM3 DAC channel 2"
---help---
Reserve TIM3 to trigger DAC2
endchoice
config STM32_TIM4_DAC
bool "TIM4 DAC"
default n
depends on STM32_TIM4 && STM32_DAC
---help---
Reserve timer 4 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM4 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM4 DAC channel"
default STM32_TIM4_DAC1
depends on STM32_TIM4_DAC
config STM32_TIM4_DAC1
bool "TIM4 DAC channel 1"
---help---
Reserve TIM4 to trigger DAC1
config STM32_TIM4_DAC2
bool "TIM4 DAC channel 2"
---help---
Reserve TIM4 to trigger DAC2
endchoice
config STM32_TIM5_DAC
bool "TIM5 DAC"
default n
depends on STM32_TIM5 && STM32_DAC
---help---
Reserve timer 5 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM5 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM5 DAC channel"
default STM32_TIM5_DAC1
depends on STM32_TIM5_DAC
config STM32_TIM5_DAC1
bool "TIM5 DAC channel 1"
---help---
Reserve TIM5 to trigger DAC1
config STM32_TIM5_DAC2
bool "TIM5 DAC channel 2"
---help---
Reserve TIM5 to trigger DAC2
endchoice
config STM32_TIM6_DAC
bool "TIM6 DAC"
default n
depends on STM32_TIM6 && STM32_DAC
---help---
Reserve timer 6 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM6 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM6 DAC channel"
default STM32_TIM6_DAC1
depends on STM32_TIM6_DAC
config STM32_TIM6_DAC1
bool "TIM6 DAC channel 1"
---help---
Reserve TIM6 to trigger DAC1
config STM32_TIM6_DAC2
bool "TIM6 DAC channel 2"
---help---
Reserve TIM6 to trigger DAC2
endchoice
config STM32_TIM7_DAC
bool "TIM7 DAC"
default n
depends on STM32_TIM7 && STM32_DAC
---help---
Reserve timer 7 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM7 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM7 DAC channel"
default STM32_TIM7_DAC1
depends on STM32_TIM7_DAC
config STM32_TIM7_DAC1
bool "TIM7 DAC channel 1"
---help---
Reserve TIM7 to trigger DAC1
config STM32_TIM7_DAC2
bool "TIM7 DAC channel 2"
---help---
Reserve TIM7 to trigger DAC2
endchoice
config STM32_TIM8_DAC
bool "TIM8 DAC"
default n
depends on STM32_TIM8 && STM32_DAC
---help---
Reserve timer 8 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM8 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM8 DAC channel"
default STM32_TIM8_DAC1
depends on STM32_TIM8_DAC
config STM32_TIM8_DAC1
bool "TIM8 DAC channel 1"
---help---
Reserve TIM8 to trigger DAC1
config STM32_TIM8_DAC2
bool "TIM8 DAC channel 2"
---help---
Reserve TIM8 to trigger DAC2
endchoice
config STM32_TIM9_DAC
bool "TIM9 DAC"
default n
depends on STM32_TIM9 && STM32_DAC
---help---
Reserve timer 9 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM9 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM9 DAC channel"
default STM32_TIM9_DAC1
depends on STM32_TIM9_DAC
config STM32_TIM9_DAC1
bool "TIM9 DAC channel 1"
---help---
Reserve TIM9 to trigger DAC1
config STM32_TIM9_DAC2
bool "TIM9 DAC channel 2"
---help---
Reserve TIM9 to trigger DAC2
endchoice
config STM32_TIM10_DAC
bool "TIM10 DAC"
default n
depends on STM32_TIM10 && STM32_DAC
---help---
Reserve timer 10 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM10 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM10 DAC channel"
default STM32_TIM10_DAC1
depends on STM32_TIM10_DAC
config STM32_TIM10_DAC1
bool "TIM10 DAC channel 1"
---help---
Reserve TIM10 to trigger DAC1
config STM32_TIM10_DAC2
bool "TIM10 DAC channel 2"
---help---
Reserve TIM10 to trigger DAC2
endchoice
config STM32_TIM11_DAC
bool "TIM11 DAC"
default n
depends on STM32_TIM11 && STM32_DAC
---help---
Reserve timer 11 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM11 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM11 DAC channel"
default STM32_TIM11_DAC1
depends on STM32_TIM11_DAC
config STM32_TIM11_DAC1
bool "TIM11 DAC channel 1"
---help---
Reserve TIM11 to trigger DAC1
config STM32_TIM11_DAC2
bool "TIM11 DAC channel 2"
---help---
Reserve TIM11 to trigger DAC2
endchoice
config STM32_TIM12_DAC
bool "TIM12 DAC"
default n
depends on STM32_TIM12 && STM32_DAC
---help---
Reserve timer 12 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM12 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM12 DAC channel"
default STM32_TIM12_DAC1
depends on STM32_TIM12_DAC
config STM32_TIM12_DAC1
bool "TIM12 DAC channel 1"
---help---
Reserve TIM12 to trigger DAC1
config STM32_TIM12_DAC2
bool "TIM12 DAC channel 2"
---help---
Reserve TIM12 to trigger DAC2
endchoice
config STM32_TIM13_DAC
bool "TIM13 DAC"
default n
depends on STM32_TIM13 && STM32_DAC
---help---
Reserve timer 13 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM13 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM13 DAC channel"
default STM32_TIM13_DAC1
depends on STM32_TIM13_DAC
config STM32_TIM13_DAC1
bool "TIM13 DAC channel 1"
---help---
Reserve TIM13 to trigger DAC1
config STM32_TIM13_DAC2
bool "TIM13 DAC channel 2"
---help---
Reserve TIM13 to trigger DAC2
endchoice
config STM32_TIM14_DAC
bool "TIM14 DAC"
default n
depends on STM32_TIM14 && STM32_DAC
---help---
Reserve timer 14 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM14 is
defined then the following may also be defined to indicate that the
timer is intended to be used for DAC conversion. Note that DAC usage
requires two definition: Not only do you have to assign the timer
for used by the DAC, but then you also have to configure which DAC
channel it is assigned to.
choice
prompt "Select TIM14 DAC channel"
default STM32_TIM14_DAC1
depends on STM32_TIM14_DAC
config STM32_TIM14_DAC1
bool "TIM14 DAC channel 1"
---help---
Reserve TIM14 to trigger DAC1
config STM32_TIM14_DAC2
bool "TIM14 DAC channel 2"
---help---
Reserve TIM14 to trigger DAC2
endchoice
menu "DAC Configuration"
depends on STM32_DAC1 || STM32_DAC2
config STM32_DAC1_DMA
bool "DAC1 DMA"
depends on STM32_DAC1
default n
---help---
If DMA is selected, then a timer and output frequency must also be
provided to support the DMA transfer. The DMA transfer could be
supported by and EXTI trigger, but this feature is not currently
supported by the driver.
if STM32_DAC1_DMA
config STM32_DAC1_TIMER
int "DAC1 timer"
range 2 7
config STM32_DAC1_TIMER_FREQUENCY
int "DAC1 timer frequency"
default 0
endif
config STM32_DAC2_DMA
bool "DAC2 DMA"
depends on STM32_DAC2
default n
---help---
If DMA is selected, then a timer and output frequency must also be
provided to support the DMA transfer. The DMA transfer could be
supported by and EXTI trigger, but this feature is not currently
supported by the driver.
if STM32_DAC2_DMA
config STM32_DAC2_TIMER
int "DAC2 timer"
default 0
range 2 7
config STM32_DAC2_TIMER_FREQUENCY
int "DAC2 timer frequency"
default 0
endif
config STM32_DAC_DMA_BUFFER_SIZE
int "DAC DMA buffer size"
default 256
endmenu
config STM32_USART
bool
menu "U[S]ART Configuration"
depends on STM32_USART
config USART1_RS485
bool "RS-485 on USART1"
default n
depends on STM32_USART1
---help---
Enable RS-485 interface on USART1. Your board config will have to
provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
used with USART1_RXDMA.
config USART1_RS485_DIR_POLARITY
int "USART1 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART1_RS485
---help---
Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART1_RXDMA
bool "USART1 Rx DMA"
default n
depends on STM32_USART1 && (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2))
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config USART2_RS485
bool "RS-485 on USART2"
default n
depends on STM32_USART2
---help---
Enable RS-485 interface on USART2. Your board config will have to
provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
used with USART2_RXDMA.
config USART2_RS485_DIR_POLARITY
int "USART2 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART2_RS485
---help---
Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART2_RXDMA
bool "USART2 Rx DMA"
default n
depends on STM32_USART2 && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config USART3_RS485
bool "RS-485 on USART3"
default n
depends on STM32_USART3
---help---
Enable RS-485 interface on USART3. Your board config will have to
provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
used with USART3_RXDMA.
config USART3_RS485_DIR_POLARITY
int "USART3 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART3_RS485
---help---
Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART3_RXDMA
bool "USART3 Rx DMA"
default n
depends on STM32_USART3 && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config UART4_RS485
bool "RS-485 on UART4"
default n
depends on STM32_UART4
---help---
Enable RS-485 interface on UART4. Your board config will have to
provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
used with UART4_RXDMA.
config UART4_RS485_DIR_POLARITY
int "UART4 RS-485 DIR pin polarity"
default 1
range 0 1
depends on UART4_RS485
---help---
Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART4_RXDMA
bool "UART4 Rx DMA"
default n
depends on STM32_UART4 && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config UART5_RS485
bool "RS-485 on UART5"
default n
depends on STM32_UART5
---help---
Enable RS-485 interface on UART5. Your board config will have to
provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
used with UART5_RXDMA.
config UART5_RS485_DIR_POLARITY
int "UART5 RS-485 DIR pin polarity"
default 1
range 0 1
depends on UART5_RS485
---help---
Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART5_RXDMA
bool "UART5 Rx DMA"
default n
depends on STM32_UART5 && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config USART6_RS485
bool "RS-485 on USART6"
default n
depends on STM32_USART6
---help---
Enable RS-485 interface on USART6. Your board config will have to
provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be
used with USART6_RXDMA.
config USART6_RS485_DIR_POLARITY
int "USART6 RS-485 DIR pin polarity"
default 1
range 0 1
depends on USART6_RS485
---help---
Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config USART6_RXDMA
bool "USART6 Rx DMA"
default n
depends on STM32_USART6 && STM32_DMA2
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config UART7_RS485
bool "RS-485 on UART7"
default n
depends on STM32_UART7
---help---
Enable RS-485 interface on UART7. Your board config will have to
provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be
used with UART7_RXDMA.
config UART7_RS485_DIR_POLARITY
int "UART7 RS-485 DIR pin polarity"
default 1
range 0 1
depends on UART7_RS485
---help---
Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART7_RXDMA
bool "UART7 Rx DMA"
default n
depends on STM32_UART7 && STM32_DMA2
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config UART8_RS485
bool "RS-485 on UART8"
default n
depends on STM32_UART8
---help---
Enable RS-485 interface on UART8. Your board config will have to
provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be
used with UART8_RXDMA.
config UART8_RS485_DIR_POLARITY
int "UART8 RS-485 DIR pin polarity"
default 1
range 0 1
depends on UART8_RS485
---help---
Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which
enables TX (0 - low / nTXEN, 1 - high / TXEN).
config UART8_RXDMA
bool "UART8 Rx DMA"
default n
depends on STM32_UART8 && STM32_DMA2
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config SERIAL_DISABLE_REORDERING
bool "Disable reordering of ttySx devices."
depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_UART4 || STM32_UART5 || STM32_USART6 || STM32_UART7 || STM32_UART8
default n
---help---
NuttX per default reorders the serial ports (/dev/ttySx) so that the
console is always on /dev/ttyS0. If more than one UART is in use this
can, however, have the side-effect that all port mappings
(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
UART. This is in particular relevant if a project uses the USB console
in some configs and a serial console in other configs, but does not
want the side effect of having all serial port names change when just
the console is moved from serial to USB.
config STM32_FLOWCONTROL_BROKEN
bool "Use Software UART RTS flow control"
depends on STM32_USART
default n
---help---
Enable UART RTS flow control using Software. Because STM
Current STM32 have broken HW based RTS behavior (they assert
nRTS after every byte received) Enable this setting workaround
this issue by useing software based management of RTS
endmenu
config STM32_USART_SINGLEWIRE
bool "Single Wire Support"
default n
depends on STM32_USART
---help---
Enable single wire UART support. The option enables support for the
TIOCSSINGLEWIRE ioctl in the STM32 serial driver.
menu "SPI Configuration"
depends on STM32_SPI
config STM32_SPI_INTERRUPTS
bool "Interrupt driver SPI"
default n
---help---
Select to enable interrupt driven SPI support. Non-interrupt-driven,
poll-waiting is recommended if the interrupt rate would be to high in
the interrupt driven case.
config STM32_SPI_DMA
bool "SPI DMA"
default n
---help---
Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT.
endmenu
menu "I2C Configuration"
depends on STM32_I2C
config STM32_I2C_ALT
bool "Alternate I2C implementation"
default n if !STM32_PERFORMANCELINE
default y if STM32_PERFORMANCELINE
depends on !STM32_STM32F30XX
---help---
This selection enables an alternative I2C driver. This alternate
driver implements some rather complex workarounds for errata against
the STM32 F103 "Performance Line". This selection is an option
because: (1) It has not yet been fully verified and (2) It is not
certain that he scope of this workaround is needed only for the F103.
config STM32_I2C_DYNTIMEO
bool "Use dynamic timeouts"
default n
depends on STM32_I2C
config STM32_I2C_DYNTIMEO_USECPERBYTE
int "Timeout Microseconds per Byte"
default 500
depends on STM32_I2C_DYNTIMEO
config STM32_I2C_DYNTIMEO_STARTSTOP
int "Timeout for Start/Stop (Milliseconds)"
default 1000
depends on STM32_I2C_DYNTIMEO
config STM32_I2CTIMEOSEC
int "Timeout seconds"
default 0
depends on STM32_I2C
config STM32_I2CTIMEOMS
int "Timeout Milliseconds"
default 500
depends on STM32_I2C && !STM32_I2C_DYNTIMEO
config STM32_I2CTIMEOTICKS
int "Timeout for Done and Stop (ticks)"
default 500
depends on STM32_I2C && !STM32_I2C_DYNTIMEO
config STM32_I2C_DUTY16_9
bool "Frequency with Tlow/Thigh = 16/9 "
default n
depends on STM32_I2C
endmenu
menu "SDIO Configuration"
depends on STM32_SDIO
config SDIO_DMA
bool "Support DMA data transfers"
default y if STM32_DMA2
depends on STM32_DMA2
---help---
Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2.
config SDIO_PRI
hex "SDIO interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDIO interrupt priority. Default: 128.
config SDIO_DMAPRIO
hex "SDIO DMA priority"
default 0x00001000 if STM32_STM32F10XX
default 0x00010000 if !STM32_STM32F10XX
---help---
Select SDIO DMA prority.
For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium,
0x00002000 high, 0x00003000 very high. Default: medium.
For other STM32's, options are: 0x00000000 low, 0x00010000 medium,
0x00020000 high, 0x00030000 very high. Default: medium.
config SDIO_WIDTH_D1_ONLY
bool "Use D1 only"
default n
---help---
Select 1-bit transfer mode. Default: 4-bit transfer mode.
endmenu
if STM32_BKPSRAM
config STM32_BBSRAM
bool "BBSRAM File Support"
default n
config STM32_BBSRAM_FILES
int "Max Files to support in BBSRAM"
default 4
config STM32_SAVE_CRASHDUMP
bool "Enable Saving Panic to BBSRAM"
default n
endif # STM32_BKPSRAM
config STM32_HAVE_RTC_SUBSECONDS
bool
default n
choice
prompt "RTC clock source"
default RTC_LSECLOCK
depends on RTC
config RTC_LSECLOCK
bool "LSE clock"
---help---
Drive the RTC with the LSE clock
config RTC_LSICLOCK
bool "LSI clock"
---help---
Drive the RTC with the LSI clock
config RTC_HSECLOCK
bool "HSE clock"
---help---
Drive the RTC with the HSE clock, divided down to 1MHz.
endchoice
if STM32_ETHMAC
menu "Ethernet MAC configuration"
config STM32_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config STM32_PHYINIT
bool "Board-specific PHY Initialization"
default n
---help---
Some boards require specialized initialization of the PHY before it can be used.
This may include such things as configuring GPIOs, resetting the PHY, etc. If
STM32_PHYINIT is defined in the configuration then the board specific logic must
provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function
one time before it first uses the PHY.
config STM32_MII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface.
choice
prompt "MII clock configuration"
default STM32_MII_MCO if STM32_STM32F10XX
default STM32_MII_MCO1 if STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_MII
config STM32_MII_MCO
bool "Use MC0 as MII clock"
depends on STM32_STM32F10XX
---help---
Use MCO to clock the MII interface. Default: Use MC0
config STM32_MII_MCO1
bool "Use MC01 as MII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
---help---
Use MCO1 to clock the MII interface. Default: Use MC01
config STM32_MII_MCO2
bool "Use MC02 as MII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
---help---
Use MCO2 to clock the MII interface. Default: Use MC01
config STM32_MII_EXTCLK
bool "External MII clock"
---help---
Clocking is provided by external logic. Don't use MCO for MII
clock. Default: Use MC0[1]
endchoice
config STM32_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
config STM32_ETHFD
bool "Full duplex"
default n
depends on !STM32_AUTONEG
---help---
If STM32_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
config STM32_ETH100MBPS
bool "100 Mbps"
default n
depends on !STM32_AUTONEG
---help---
If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
config STM32_PHYSR
int "PHY Status Register Address (decimal)"
depends on STM32_AUTONEG
---help---
This must be provided if STM32_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
config STM32_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on STM32_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config STM32_PHYSR_SPEED
hex "PHY Speed Mask"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config STM32_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config STM32_PHYSR_MODE
hex "PHY Mode Mask"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config STM32_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config STM32_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config STM32_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config STM32_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config STM32_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config STM32_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG
---help---
This must be provided if STM32_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
config STM32_ETH_PTP
bool "Precision Time Protocol (PTP)"
default n
---help---
Precision Time Protocol (PTP). Not supported but some hooks are indicated
with this condition.
config STM32_RMII
bool
default y if !STM32_MII
choice
prompt "RMII clock configuration"
default STM32_RMII_MCO if STM32_STM32F10XX
default STM32_RMII_MCO1 if STM32_STM32F207 || STM32_STM32F40XX
depends on STM32_RMII
config STM32_RMII_MCO
bool "Use MC0 as RMII clock"
depends on STM32_STM32F10XX
---help---
Use MCO to clock the RMII interface. Default: Use MC0
config STM32_RMII_MCO1
bool "Use MC01 as RMII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
---help---
Use MCO1 to clock the RMII interface. Default: Use MC01
config STM32_RMII_MCO2
bool "Use MC02 as RMII clock"
depends on (STM32_STM32F207 || STM32_STM32F40XX)
---help---
Use MCO2 to clock the RMII interface. Default: Use MC01
config STM32_RMII_EXTCLK
bool "External RMII clock"
---help---
Clocking is provided by external logic. Don't use MCO for RMII
clock. Default: Use MC0[1]
endchoice
config STM32_ETHMAC_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG.
endmenu
endif
menu "USB FS Host Configuration"
config STM32_OTGFS_RXFIFO_SIZE
int "Rx Packet Size"
default 128
depends on USBHOST && STM32_OTGFS
---help---
Size of the RX FIFO in 32-bit words. Default 128 (512 bytes)
config STM32_OTGFS_NPTXFIFO_SIZE
int "Non-periodic Tx FIFO Size"
default 96
depends on USBHOST && STM32_OTGFS
---help---
Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
config STM32_OTGFS_PTXFIFO_SIZE
int "Periodic Tx FIFO size"
default 128
depends on USBHOST && STM32_OTGFS
---help---
Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
config STM32_OTGFS_DESCSIZE
int "Descriptor Size"
default 128
depends on USBHOST && STM32_OTGFS
---help---
Maximum size to allocate for descriptor memory descriptor. Default: 128
config STM32_OTGFS_SOFINTR
bool "Enable SOF interrupts"
default n
depends on USBHOST && STM32_OTGFS
---help---
Enable SOF interrupts. Why would you ever want to do that?
endmenu
menu "USB HS Host Configuration"
config STM32_OTGHS_RXFIFO_SIZE
int "Rx Packet Size"
default 128
depends on USBHOST && STM32_OTGHS
---help---
Size of the RX FIFO in 32-bit words. Default 128 (512 bytes)
config STM32_OTGHS_NPTXFIFO_SIZE
int "Non-periodic Tx FIFO Size"
default 96
depends on USBHOST && STM32_OTGHS
---help---
Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
config STM32_OTGHS_PTXFIFO_SIZE
int "Periodic Tx FIFO size"
default 128
depends on USBHOST && STM32_OTGHS
---help---
Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
config STM32_OTGHS_DESCSIZE
int "Descriptor Size"
default 128
depends on USBHOST && STM32_OTGHS
---help---
Maximum size to allocate for descriptor memory descriptor. Default: 128
config STM32_OTGHS_SOFINTR
bool "Enable SOF interrupts"
default n
depends on USBHOST && STM32_OTGHS
---help---
Enable SOF interrupts. Why would you ever want to do that?
endmenu
menu "USB Host Debug Configuration"
config STM32_USBHOST_REGDEBUG
bool "Register-Level Debug"
default n
depends on USBHOST && (STM32_OTGFS || STM32_OTGHS)
---help---
Enable very low-level register access debug. Depends on DEBUG.
config STM32_USBHOST_PKTDUMP
bool "Packet Dump Debug"
default n
depends on USBHOST && (STM32_OTGFS || STM32_OTGHS)
---help---
Dump all incoming and outgoing USB packets. Depends on DEBUG.
endmenu
comment "USB Device Configuration"
config STM32_USB_ITRMP
bool "Re-map USB interrupt"
default n if !STM32_CAN1
default y if STM32_CAN1
depends on STM32_USB && STM32_STM32F30XX
---help---
The legacy USB in the F1 series shared interrupt lines with USB
device and CAN1. In the F3 series, a hardware options was added to
either retain the legacy F1 behavior or to map the USB interupts to
there own dedicated vectors. The option is available only for the
F3 family and selects the use of the dedicated USB interrupts.
menu "CAN driver configuration"
depends on STM32_CAN1 || STM32_CAN2
config CAN1_BAUD
int "CAN1 BAUD"
default 250000
depends on STM32_CAN1
---help---
CAN1 BAUD rate. Required if STM32_CAN1 is defined.
config CAN2_BAUD
int "CAN2 BAUD"
default 250000
depends on STM32_CAN2
---help---
CAN2 BAUD rate. Required if STM32_CAN2 is defined.
config CAN_TSEG1
int "TSEG1 quanta"
default 6
---help---
The number of CAN time quanta in segment 1. Default: 6
config CAN_TSEG2
int "TSEG2 quanta"
default 7
---help---
The number of CAN time quanta in segment 2. Default: 7
endmenu
if STM32_LTDC
menu "LTDC Configuration"
config STM32_LTDC_INTERFACE
bool "LTDC interface support"
default n
---help---
Enable the ltdc interface to support ltdc layer control.
config STM32_LTDC_BACKLIGHT
bool "Backlight support"
default y
config STM32_LTDC_DEFBACKLIGHT
hex "Default backlight level"
default 0xf0
config STM32_LTDC_BACKCOLOR
hex "Background color"
default 0x0
---help---
This is the background color that will be used as the LTDC
background layer color. It is an RGB888 format value.
config STM32_LTDC_DITHER
bool "Dither support"
default n
config STM32_LTDC_DITHER_RED
depends on STM32_LTDC_DITHER
int "Dither red width"
range 0 7
default 2
---help---
This is the dither red width.
config STM32_LTDC_DITHER_GREEN
depends on STM32_LTDC_DITHER
int "Dither green width"
range 0 7
default 2
---help---
This is the dither green width.
config STM32_LTDC_DITHER_BLUE
depends on STM32_LTDC_DITHER
int "Dither blue width"
range 0 7
default 2
---help---
This is the dither blue width.
config STM32_LTDC_FB_BASE
hex "Framebuffer memory start address"
---help---
If you are using the the LTDC, then you must provide the address
of the start of the framebuffer. This address will typically
be in the SRAM or SDRAM memory region of the FSMC.
config STM32_LTDC_FB_SIZE
int "Framebuffer memory size (bytes)"
default 0
choice
prompt "Layer 1 color format"
default STM32_LTDC_L1_RGB565
config STM32_LTDC_L1_L8
bool "8 bpp L8 (8-bit CLUT)"
config STM32_LTDC_L1_AL44
bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)"
config STM32_LTDC_L1_AL88
bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)"
config STM32_LTDC_L1_RGB565
bool "16 bpp RGB 565"
config STM32_LTDC_L1_ARGB4444
bool "16 bpp ARGB 4444"
config STM32_LTDC_L1_ARGB1555
bool "16 bpp ARGB 1555"
config STM32_LTDC_L1_RGB888
bool "24 bpp RGB 888"
config STM32_LTDC_L1_ARGB8888
bool "32 bpp ARGB 8888"
endchoice # Layer 1 color format
config STM32_LTDC_L2
bool "Enable Layer 2 support"
default y
if STM32_LTDC_L2
choice
prompt "Layer 2 (top layer) color format"
default STM32_LTDC_L2_RGB565
config STM32_LTDC_L2_L8
bool "8 bpp L8 (8-bit CLUT)"
config STM32_LTDC_L2_AL44
bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)"
config STM32_LTDC_L2_AL88
bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)"
config STM32_LTDC_L2_RGB565
bool "16 bpp RGB 565"
config STM32_LTDC_L2_ARGB4444
bool "16 bpp ARGB 4444"
config STM32_LTDC_L2_ARGB1555
bool "16 bpp ARGB 1555"
config STM32_LTDC_L2_RGB888
bool "24 bpp RGB 888"
config STM32_LTDC_L2_ARGB8888
bool "32 bpp ARGB 8888"
endchoice # Layer 2 color format
endif # STM32_LTDC_L2
if STM32_LTDC_L1_L8 || STM32_LTDC_L2_L8
config FB_CMAP
bool "Enable color map support"
default y
---help---
Enabling color map suport is neccessary for ltdc L8 format.
endif
endmenu
endif # STM32_LTDC
if STM32_DMA2D
menu "DMA2D Configuration"
config STM32_DMA2D_NLAYERS
int "Number DMA2D layers"
default 2
---help---
Number of allocatable DMA2D layers except the LTDC layer.
menu "Supported pixel format"
config STM32_DMA2D_L8
bool "8 bpp L8 (8-bit CLUT)"
default y
config STM32_DMA2D_AL44
bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)"
default n
config STM32_DMA2D_AL88
bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)"
default n
config STM32_DMA2D_RGB565
bool "16 bpp RGB 565"
default y
config STM32_DMA2D_ARGB4444
bool "16 bpp ARGB 4444"
default n
config STM32_DMA2D_ARGB1555
bool "16 bpp ARGB 1555"
default n
config STM32_DMA2D_RGB888
bool "24 bpp RGB 888"
default y
config STM32_DMA2D_ARGB8888
bool "32 bpp ARGB 8888"
default n
endmenu
endmenu
endif # STM32_DMA2D
|