1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
|
/************************************************************************************
* arch/hc/src/mc9s12ne64/mc9s12ne64_pim.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PIM_H
#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PIM_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define HCS12_PIM_PORTT_OFFSET (0x0000)
#define HCS12_PIM_PORTS_OFFSET (0x0008)
#define HCS12_PIM_PORTG_OFFSET (0x0010)
#define HCS12_PIM_PORTH_OFFSET (0x0018)
#define HCS12_PIM_PORTJ_OFFSET (0x0020)
#define HCS12_PIM_PORTL_OFFSET (0x0028)
#define HCS12_PIM_IO_OFFSET (0x0000) /* I/O Register (ALL) */
#define HCS12_PIM_INPUT_OFFSET (0x0001) /* Input Register (ALL) */
#define HCS12_PIM_DDR_OFFSET (0x0002) /* Data Direction Register (ALL) */
#define HCS12_PIM_RDR_OFFSET (0x0003) /* Reduced Drive Register (ALL) */
#define HCS12_PIM_PER_OFFSET (0x0004) /* Pull Device Enable Register (ALL) */
#define HCS12_PIM_PS_OFFSET (0x0005) /* Polarity Select Register (ALL) */
#define HCS12_PIM_WOM_OFFSET (0x0006) /* Wired OR Mode Register (PORT S and L) */
#define HCS12_PIM_IE_OFFSET (0x0006) /* Interrupt Enable Register (PORT G, H, and J) */
#define HCS12_PIM_IF_OFFSET (0x0007) /* Interrupt Flag Register (PORT G, H, and J) */
/* Register Addresses ***************************************************************/
#define PIM_PORTT (0)
#define PIM_PORTS (1)
#define PIM_PORTG (2)
#define PIM_PORTH (3)
#define PIM_PORTJ (4)
#define PIM_PORTL (5)
#define HCS12_PIM_PORT_BASE(n) (HCS12_PIM_BASE + 0x0008*(n))
#define HCS12_PIM_PORTT_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTT_OFFSET)
#define HCS12_PIM_PORTS_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTS_OFFSET)
#define HCS12_PIM_PORTG_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTG_OFFSET)
#define HCS12_PIM_PORTH_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTH_OFFSET)
#define HCS12_PIM_PORTJ_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTJ_OFFSET)
#define HCS12_PIM_PORTL_BASE (HCS12_PIM_BASE + HCS12_PIM_PORTL_OFFSET)
#define HCS12_PIM_PORT_IO(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORT_INPUT(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORT_DDR(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORT_RDR(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORT_PER(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORT_PS(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORT_IE(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IE_OFFSET)
#define HCS12_PIM_PORT_IF(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IF_OFFSET)
#define HCS12_PIM_PORTT_IO (HCS12_PIM_PORTT_BASE + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORTT_INPUT (HCS12_PIM_PORTT_BASE + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORTT_DDR (HCS12_PIM_PORTT_BASE + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORTT_RDR (HCS12_PIM_PORTT_BASE + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORTT_PER (HCS12_PIM_PORTT_BASE + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORTT_PS (HCS12_PIM_PORTT_BASE + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORTS_IO (HCS12_PIM_PORTS_BASE + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORTS_INPUT (HCS12_PIM_PORTS_BASE + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORTS_DDR (HCS12_PIM_PORTS_BASE + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORTS_RDR (HCS12_PIM_PORTS_BASE + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORTS_PER (HCS12_PIM_PORTS_BASE + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORTS_PS (HCS12_PIM_PORTS_BASE + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORTS_WOM (HCS12_PIM_PORTS_BASE + HCS12_PIM_WOM_OFFSET)
#define HCS12_PIM_PORTG_IO (HCS12_PIM_PORTG_BASE + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORTG_INPUT (HCS12_PIM_PORTG_BASE + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORTG_DDR (HCS12_PIM_PORTG_BASE + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORTG_RDR (HCS12_PIM_PORTG_BASE + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORTG_PER (HCS12_PIM_PORTG_BASE + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORTG_PS (HCS12_PIM_PORTG_BASE + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORTG_IE (HCS12_PIM_PORTG_BASE + HCS12_PIM_IE_OFFSET)
#define HCS12_PIM_PORTG_IF (HCS12_PIM_PORTG_BASE + HCS12_PIM_IF_OFFSET)
#define HCS12_PIM_PORTH_IO (HCS12_PIM_PORTH_BASE + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORTH_INPUT (HCS12_PIM_PORTH_BASE + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORTH_DDR (HCS12_PIM_PORTH_BASE + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORTH_RDR (HCS12_PIM_PORTH_BASE + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORTH_PER (HCS12_PIM_PORTH_BASE + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORTH_PS (HCS12_PIM_PORTH_BASE + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORTH_IE (HCS12_PIM_PORTH_BASE + HCS12_PIM_IE_OFFSET)
#define HCS12_PIM_PORTH_IF (HCS12_PIM_PORTH_BASE + HCS12_PIM_IF_OFFSET)
#define HCS12_PIM_PORTJ_IO (HCS12_PIM_PORTJ_BASE + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORTJ_INPUT (HCS12_PIM_PORTJ_BASE + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORTJ_DDR (HCS12_PIM_PORTJ_BASE + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORTJ_RDR (HCS12_PIM_PORTJ_BASE + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORTJ_PER (HCS12_PIM_PORTJ_BASE + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORTJ_PS (HCS12_PIM_PORTJ_BASE + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORTJ_IE (HCS12_PIM_PORTJ_BASE + HCS12_PIM_IE_OFFSET)
#define HCS12_PIM_PORTJ_IF (HCS12_PIM_PORTJ_BASE + HCS12_PIM_IF_OFFSET)
#define HCS12_PIM_PORTL_IO (HCS12_PIM_PORTL_BASE + HCS12_PIM_IO_OFFSET)
#define HCS12_PIM_PORTL_INPUT (HCS12_PIM_PORTL_BASE + HCS12_PIM_INPUT_OFFSET)
#define HCS12_PIM_PORTL_DDR (HCS12_PIM_PORTL_BASE + HCS12_PIM_DDR_OFFSET)
#define HCS12_PIM_PORTL_RDR (HCS12_PIM_PORTL_BASE + HCS12_PIM_RDR_OFFSET)
#define HCS12_PIM_PORTL_PER (HCS12_PIM_PORTL_BASE + HCS12_PIM_PER_OFFSET)
#define HCS12_PIM_PORTL_PS (HCS12_PIM_PORTL_BASE + HCS12_PIM_PS_OFFSET)
#define HCS12_PIM_PORTL_WOM (HCS12_PIM_PORTL_BASE + HCS12_PIM_WOM_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Port register bits */
#define PIM_PIN(n) (1 << (n))
#define PIM_PIN0 (1 << 0)
#define PIM_PIN1 (1 << 1)
#define PIM_PIN2 (1 << 2)
#define PIM_PIN3 (1 << 3)
#define PIM_PIN4 (1 << 4)
#define PIM_PIN5 (1 << 5)
#define PIM_PIN6 (1 << 6)
#define PIM_PIN7 (1 << 7)
/* Port T I/O register aliases */
#define TIM_IOC4 PIM_PIN4
#define TIM_IOC5 PIM_PIN5
#define TIM_IOC6 PIM_PIN6
#define TIM_IOC7 PIM_PIN7
/* Port S I/O register aliases */
#define SCI0_RXD PIM_PIN0
#define SCI0_TXD PIM_PIN1
#define SCI1_RXD PIM_PIN2
#define SCI1_TXD PIM_PIN3
#define SPI_MISO PIM_PIN4
#define SPI_MOSI PIM_PIN5
#define SPI_SCK PIM_PIN6
#define SPI_SS PIM_PIN7
/* Port G I/O register aliases */
#define MII_RXD0 PIM_PIN0
#define MII_RXD1 PIM_PIN1
#define MII_RXD2 PIM_PIN2
#define MII_RXD3 PIM_PIN3
#define MII_RXCLK PIM_PIN4
#define MII_RXDV PIM_PIN5
#define MII_RXER PIM_PIN6
/* Port H I/O register aliases */
#define MII_TXD0 PIM_PIN0
#define MII_TXD1 PIM_PIN1
#define MII_TXD2 PIM_PIN2
#define MII_TXD3 PIM_PIN3
#define MII_TXCLK PIM_PIN4
#define MII_TXEN PIM_PIN5
#define MII_TXER PIM_PIN6
/* Port J I/O register aliases */
#define MII_MDC PIM_PIN0
#define MII_MDIO PIM_PIN1
#define MII_CRS PIM_PIN2
#define MII_COL PIM_PIN3
#define IIC_SDA PIM_PIN5
#define IIC_SCL PIM_PIN6
/* Port L I/O register aliases */
#define PHY_ACTLED PIM_PIN0
#define PHY_LNKLED PIM_PIN1
#define PHY_SPDLED PIM_PIN2
#define PHY_DUPLED PIM_PIN3
#define PHY_COLLED PIM_PIN4
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_PIM_H */
|