CAN ISO-11783 support contributed by Gary Teravskis

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4400 42af7a65-404d-4744-a932-0658087f49c3

14 files changed, 341 insertions, 98 deletions

diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog
index d957a193b..62e11f6bb 100644
--- a/nuttx/ChangeLog
+++ b/nuttx/ChangeLog
@@ -2466,3 +2466,4 @@
 	* arch/arm/src/stm32/stm32_qencoder.c/.h:  Add a initial implementation of
 	  a lower-half quadrature encoder driver for the STM32.  On initial check-in,
 	  this is little more than a "skeleton" file.
+	* Various files:  CAN ISO-11783 support contributed by Gary Teravskis.
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
index 8446a2472..248b1ecc3 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
@@ -356,14 +356,14 @@
 /* CAN */
 
 #if defined(CONFIG_STM32_CAN1_REMAP1)
-#  define GPIO_CAN1_TX      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#  define GPIO_CAN1_RX      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_CAN1_TX      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_CAN1_RX      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
 #elif defined(CONFIG_STM32_CAN1_REMAP2)
-#  define GPIO_CAN1_TX      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
-#  define GPIO_CAN1_RX      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
+#  define GPIO_CAN1_TX      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
+#  define GPIO_CAN1_RX      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN0)
 #else
-#  define GPIO_CAN1_TX      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
-#  define GPIO_CAN1_RX      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
+#  define GPIO_CAN1_TX      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
+#  define GPIO_CAN1_RX      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
 #endif
 
 /* FSMC: CF */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
index 110816f1f..21d4648fa 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
@@ -210,7 +210,8 @@
 #define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST        (1 << 22) /* Bit 22: I2C 2 reset */
 #define RCC_APB1RSTR_USBRST         (1 << 23) /* Bit 23: USB reset */
-#define RCC_APB1RSTR_CANRST         (1 << 25) /* Bit 25: CAN reset */
+#define RCC_APB1RSTR_CAN1RST        (1 << 25) /* Bit 25: CAN1 reset */
+#define RCC_APB1RSTR_CAN2RST        (1 << 26) /* Bit 26: CAN2 reset */
 #define RCC_APB1RSTR_BKPRST         (1 << 27) /* Bit 27: Backup interface reset */
 #define RCC_APB1RSTR_PWRRST         (1 << 28) /* Bit 28: Power interface reset */
 #define RCC_APB1RSTR_DACRST         (1 << 29) /* Bit 29: DAC interface reset */
@@ -262,7 +263,8 @@
 #define RCC_APB1ENR_I2C1EN          (1 << 21) /* Bit 21: I2C 1 clock enable */
 #define RCC_APB1ENR_I2C2EN          (1 << 22) /* Bit 22: I2C 2 clock enable */
 #define RCC_APB1ENR_USBEN           (1 << 23) /* Bit 23: USB clock enable */
-#define RCC_APB1ENR_CANEN           (1 << 25) /* Bit 25: CAN clock enable */
+#define RCC_APB1ENR_CAN1EN          (1 << 25) /* Bit 25: CAN1 clock enable */
+#define RCC_APB1ENR_CAN2EN          (1 << 26) /* Bit 25: CAN2 clock enable */
 #define RCC_APB1ENR_BKPEN           (1 << 27) /* Bit 27: Backup interface clock enable */
 #define RCC_APB1ENR_PWREN           (1 << 28) /* Bit 28: Power interface clock enable */
 #define RCC_APB1ENR_DACEN           (1 << 29) /* Bit 29: DAC interface clock enable */
diff --git a/nuttx/arch/arm/src/stm32/stm32_can.c b/nuttx/arch/arm/src/stm32/stm32_can.c
index 5df6de4f7..7e65ecfc8 100755
--- a/nuttx/arch/arm/src/stm32/stm32_can.c
+++ b/nuttx/arch/arm/src/stm32/stm32_can.c
@@ -1282,7 +1282,8 @@ static int can_bittiming(struct stm32_can_s *priv)
   uint32_t ts1;
   uint32_t ts2;
 
-  canllvdbg("CAN%d PCLK1: %d baud: %d\n", priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
+  canllvdbg("CAN%d PCLK1: %d baud: %d\n",
+            priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
 
   /* Try to get CAN_BIT_QUANTA quanta in one bit_time.
    *
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c
index e95d437d1..54672481a 100644
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c
@@ -1,8 +1,8 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32_rcc.c
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
index 15aed029a..9b87def75 100644
--- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -1,8 +1,8 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32f10xxx_rcc.c
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -114,31 +114,31 @@ static inline void rcc_enableahb(void)
 
   regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN;
 
-#if CONFIG_STM32_DMA1
+#ifdef CONFIG_STM32_DMA1
   /* DMA 1 clock enable */
 
   regval |= RCC_AHBENR_DMA1EN;
 #endif
 
-#if CONFIG_STM32_DMA2
+#ifdef CONFIG_STM32_DMA2
   /* DMA 2 clock enable */
 
   regval |= RCC_AHBENR_DMA2EN;
 #endif
 
-#if CONFIG_STM32_CRC
+#ifdef CONFIG_STM32_CRC
   /* CRC clock enable */
 
   regval |= RCC_AHBENR_CRCEN;
 #endif
 
-#if CONFIG_STM32_FSMC
+#ifdef CONFIG_STM32_FSMC
   /* FSMC clock enable */
 
   regval |=  RCC_AHBENR_FSMCEN;
 #endif
 
-#if CONFIG_STM32_SDIO
+#ifdef CONFIG_STM32_SDIO
   /* SDIO clock enable */
 
   regval |=  RCC_AHBENR_SDIOEN;
@@ -159,7 +159,7 @@ static inline void rcc_enableapb1(void)
 {
   uint32_t regval;
 
-#if CONFIG_STM32_USB
+#ifdef CONFIG_STM32_USB
   /* USB clock divider. This bit must be valid before enabling the USB
    * clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
    * clock is enabled.
@@ -176,123 +176,129 @@ static inline void rcc_enableapb1(void)
    */
 
   regval  = getreg32(STM32_RCC_APB1ENR);
-#if CONFIG_STM32_TIM2
+#ifdef CONFIG_STM32_TIM2
   /* Timer 2 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_TIM2EN;
 #endif
 #endif
 
-#if CONFIG_STM32_TIM3
+#ifdef CONFIG_STM32_TIM3
   /* Timer 3 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_TIM3EN;
 #endif
 #endif
 
-#if CONFIG_STM32_TIM4
+#ifdef CONFIG_STM32_TIM4
   /* Timer 4 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_TIM4EN;
 #endif
 #endif
 
-#if CONFIG_STM32_TIM5
+#ifdef CONFIG_STM32_TIM5
   /* Timer 5 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_TIM5EN;
 #endif
 #endif
 
-#if CONFIG_STM32_TIM6
+#ifdef CONFIG_STM32_TIM6
   /* Timer 6 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_TIM6EN;
 #endif
 #endif
 
-#if CONFIG_STM32_TIM7
+#ifdef CONFIG_STM32_TIM7
   /* Timer 7 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_TIM7EN;
 #endif
 #endif
 
-#if CONFIG_STM32_WWDG
+#ifdef CONFIG_STM32_WWDG
   /* Window Watchdog clock enable */
 
   regval |= RCC_APB1ENR_WWDGEN;
 #endif
 
-#if CONFIG_STM32_SPI2
+#ifdef CONFIG_STM32_SPI2
   /* SPI 2 clock enable */
 
   regval |= RCC_APB1ENR_SPI2EN;
 #endif
   
-#if CONFIG_STM32_SPI3
+#ifdef CONFIG_STM32_SPI3
   /* SPI 3 clock enable */
 
   regval |= RCC_APB1ENR_SPI3EN;
 #endif
 
-#if CONFIG_STM32_USART2
+#ifdef CONFIG_STM32_USART2
   /* USART 2 clock enable */
 
   regval |= RCC_APB1ENR_USART2EN;
 #endif
 
-#if CONFIG_STM32_USART3
+#ifdef CONFIG_STM32_USART3
   /* USART 3 clock enable */
 
   regval |= RCC_APB1ENR_USART3EN;
 #endif
 
-#if CONFIG_STM32_UART4
+#ifdef CONFIG_STM32_UART4
   /* UART 4 clock enable */
 
   regval |= RCC_APB1ENR_UART4EN;
 #endif
 
-#if CONFIG_STM32_UART5
+#ifdef CONFIG_STM32_UART5
   /* UART 5 clock enable */
 
   regval |= RCC_APB1ENR_UART5EN;
 #endif
 
-#if CONFIG_STM32_I2C1
+#ifdef CONFIG_STM32_I2C1
   /* I2C 1 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_I2C1EN;
 #endif
 #endif
 
-#if CONFIG_STM32_I2C2
+#ifdef CONFIG_STM32_I2C2
   /* I2C 2 clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB1ENR_I2C2EN;
 #endif
 #endif
 
-#if CONFIG_STM32_USB
+#ifdef CONFIG_STM32_USB
   /* USB clock enable */
 
   regval |= RCC_APB1ENR_USBEN;
 #endif
 
-#if CONFIG_STM32_CAN
-  /* CAN clock enable */
+#if defined(CONFIG_STM32_CAN) || defined (CONFIG_STM32_CAN1)
+  /* CAN1 clock enable */
 
-  regval |= RCC_APB1ENR_CANEN;
+  regval |= RCC_APB1ENR_CAN1EN;
 #endif
 
-#if CONFIG_STM32_BKP
+#ifdef CONFIG_STM32_CAN2
+  /* CAN2 clock enable */
+
+  regval |= RCC_APB1ENR_CAN2EN;
+#endif
+
+#ifdef CONFIG_STM32_BKP
   /* Backup interface clock enable */
 
   regval |= RCC_APB1ENR_BKPEN;
 #endif
 
-#if CONFIG_STM32_PWR
+#ifdef CONFIG_STM32_PWR
   /*  Power interface clock enable */
 
   regval |= RCC_APB1ENR_PWREN;
@@ -349,45 +355,45 @@ static inline void rcc_enableapb2(void)
 #endif
              );
 
-#if CONFIG_STM32_ADC1
+#ifdef CONFIG_STM32_ADC1
   /* ADC 1 interface clock enable */
 
   regval |= RCC_APB2ENR_ADC1EN;
 #endif
 
-#if CONFIG_STM32_ADC2
+#ifdef CONFIG_STM32_ADC2
   /* ADC 2 interface clock enable */
 
   regval |= RCC_APB2ENR_ADC2EN;
 #endif
 
-#if CONFIG_STM32_TIM1
+#ifdef CONFIG_STM32_TIM1
   /* TIM1 Timer clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB2ENR_TIM1EN;
 #endif
 #endif
 
-#if CONFIG_STM32_SPI1
+#ifdef CONFIG_STM32_SPI1
   /* SPI 1 clock enable */
 
   regval |= RCC_APB2ENR_SPI1EN;
 #endif
 
-#if CONFIG_STM32_TIM8
+#ifdef CONFIG_STM32_TIM8
   /* TIM8 Timer clock enable */
 #ifdef CONFIG_STM32_FORCEPOWER
   regval |= RCC_APB2ENR_TIM8EN;
 #endif
 #endif
 
-#if CONFIG_STM32_USART1
+#ifdef CONFIG_STM32_USART1
   /* USART1 clock enable */
 
   regval |= RCC_APB2ENR_USART1EN;
 #endif
 
-#if CONFIG_STM32_ADC3
+#ifdef CONFIG_STM32_ADC3
   /*ADC3 interface clock enable */
 
   regval |= RCC_APB2ENR_ADC3EN;
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index b1c7e8254..330d56aef 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -151,31 +151,31 @@ static inline void rcc_enableahb1(void)
              );
 #endif
 
-#if CONFIG_STM32_CRC
+#ifdef CONFIG_STM32_CRC
   /* CRC clock enable */
 
   regval |= RCC_AHB1ENR_CRCEN;
 #endif
 
-#if CONFIG_STM32_BKPSRAM
+#ifdef CONFIG_STM32_BKPSRAM
   /* Backup SRAM clock enable */
 
   regval |= RCC_AHB1ENR_BKPSRAMEN;
 #endif
 
-#if CONFIG_STM32_CCMDATARAM
+#ifdef CONFIG_STM32_CCMDATARAM
   /* CCM data RAM clock enable */
 
   regval |= RCC_AHB1ENR_CCMDATARAMEN;
 #endif
 
-#if CONFIG_STM32_DMA1
+#ifdef CONFIG_STM32_DMA1
   /* DMA 1 clock enable */
 
   regval |= RCC_AHB1ENR_DMA1EN;
 #endif
 
-#if CONFIG_STM32_DMA2
+#ifdef CONFIG_STM32_DMA2
   /* DMA 2 clock enable */
 
   regval |= RCC_AHB1ENR_DMA2EN;
@@ -221,31 +221,31 @@ static inline void rcc_enableahb2(void)
 
   regval = getreg32(STM32_RCC_AHB2ENR);
 
-#if CONFIG_STM32_DCMI
+#ifdef CONFIG_STM32_DCMI
   /* Camera interface enable */
 
   regval |= RCC_AHB2ENR_DCMIEN;
 #endif
 
-#if CONFIG_STM32_CRYP
+#ifdef CONFIG_STM32_CRYP
   /* Cryptographic modules clock enable */
 
   regval |= RCC_AHB2ENR_CRYPEN;
 #endif
 
-#if CONFIG_STM32_HASH
+#ifdef CONFIG_STM32_HASH
   /* Hash modules clock enable */
 
   regval |= RCC_AHB2ENR_HASHEN;
 #endif
 
-#if CONFIG_STM32_RNG
+#ifdef CONFIG_STM32_RNG
   /* Random number generator clock enable */
 
   regval |= RCC_AHB2ENR_RNGEN;
 #endif
 
-#if CONFIG_STM32_OTGFS
+#ifdef CONFIG_STM32_OTGFS
   /* USB OTG FS clock enable */
 
   regval |= RCC_AHB2ENR_OTGFSEN;
@@ -264,7 +264,7 @@ static inline void rcc_enableahb2(void)
 
 static inline void rcc_enableahb3(void)
 {
-#if CONFIG_STM32_FSMC
+#ifdef CONFIG_STM32_FSMC
   uint32_t regval;
 
   /* Set the appropriate bits in the AHB3ENR register to enabled the
@@ -299,127 +299,127 @@ static inline void rcc_enableapb1(void)
 
   regval = getreg32(STM32_RCC_APB1ENR);
 
-#if CONFIG_STM32_TIM2
+#ifdef CONFIG_STM32_TIM2
   /* TIM2 clock enable */
 
   regval |= RCC_APB1ENR_TIM2EN;
 #endif
 
-#if CONFIG_STM32_TIM3
+#ifdef CONFIG_STM32_TIM3
   /* TIM3 clock enable */
 
   regval |= RCC_APB1ENR_TIM3EN;
 #endif
 
-#if CONFIG_STM32_TIM4
+#ifdef CONFIG_STM32_TIM4
   /* TIM4 clock enable */
 
   regval |= RCC_APB1ENR_TIM4EN;
 #endif
 
-#if CONFIG_STM32_TIM5
+#ifdef CONFIG_STM32_TIM5
   /* TIM5 clock enable */
 
   regval |= RCC_APB1ENR_TIM5EN;
 #endif
 
-#if CONFIG_STM32_TIM6
+#ifdef CONFIG_STM32_TIM6
   /* TIM6 clock enable */
 
   regval |= RCC_APB1ENR_TIM6EN;
 #endif
 
-#if CONFIG_STM32_TIM7
+#ifdef CONFIG_STM32_TIM7
   /* TIM7 clock enable */
 
   regval |= RCC_APB1ENR_TIM7EN;
 #endif
 
-#if CONFIG_STM32_TIM12
+#ifdef CONFIG_STM32_TIM12
   /* TIM12 clock enable */
 
   regval |= RCC_APB1ENR_TIM12EN;
 #endif
 
-#if CONFIG_STM32_TIM13
+#ifdef CONFIG_STM32_TIM13
   /* TIM13 clock enable */
 
   regval |= RCC_APB1ENR_TIM13EN;
 #endif
 
-#if CONFIG_STM32_TIM14
+#ifdef CONFIG_STM32_TIM14
   /* TIM14 clock enable */
 
   regval |= RCC_APB1ENR_TIM14EN;
 #endif
 
-#if CONFIG_STM32_WWDG
+#ifdef CONFIG_STM32_WWDG
   /* Window watchdog clock enable */
 
   regval |= RCC_APB1ENR_WWDGEN;
 #endif
 
-#if CONFIG_STM32_SPI2
+#ifdef CONFIG_STM32_SPI2
   /* SPI2 clock enable */
 
   regval |= RCC_APB1ENR_SPI2EN;
 #endif
 
-#if CONFIG_STM32_SPI3
+#ifdef CONFIG_STM32_SPI3
   /* SPI3 clock enable */
 
   regval |= RCC_APB1ENR_SPI3EN;
 #endif
 
-#if CONFIG_STM32_USART2
+#ifdef CONFIG_STM32_USART2
   /* USART 2 clock enable */
 
   regval |= RCC_APB1ENR_USART2EN;
 #endif
 
-#if CONFIG_STM32_USART3
+#ifdef CONFIG_STM32_USART3
   /* USART3 clock enable */
 
   regval |= RCC_APB1ENR_USART3EN;
 #endif
 
-#if CONFIG_STM32_UART4
+#ifdef CONFIG_STM32_UART4
   /* UART4 clock enable */
 
   regval |= RCC_APB1ENR_UART4EN;
 #endif
 
-#if CONFIG_STM32_UART5
+#ifdef CONFIG_STM32_UART5
   /* UART5 clock enable */
 
   regval |= RCC_APB1ENR_UART5EN;
 #endif
 
-#if CONFIG_STM32_I2C1
+#ifdef CONFIG_STM32_I2C1
   /* I2C1 clock enable */
 
   regval |= RCC_APB1ENR_I2C1EN;
 #endif
 
-#if CONFIG_STM32_I2C2
+#ifdef CONFIG_STM32_I2C2
   /* I2C2 clock enable */
 
   regval |= RCC_APB1ENR_I2C2EN;
 #endif
 
-#if CONFIG_STM32_I2C3
+#ifdef CONFIG_STM32_I2C3
   /* I2C3 clock enable */
 
   regval |= RCC_APB1ENR_I2C3EN;
 #endif
 
-#if CONFIG_STM32_CAN1
+#ifdef CONFIG_STM32_CAN1
   /* CAN 1 clock enable */
 
   regval |= RCC_APB1ENR_CAN1EN;
 #endif
 
-#if CONFIG_STM32_CAN2
+#ifdef CONFIG_STM32_CAN2
   /* CAN 2 clock enable */
 
   regval |= RCC_APB1ENR_CAN2EN;
@@ -458,79 +458,79 @@ static inline void rcc_enableapb2(void)
 
   regval = getreg32(STM32_RCC_APB2ENR);
 
-#if CONFIG_STM32_TIM1
+#ifdef CONFIG_STM32_TIM1
   /* TIM1 clock enable */
 
   regval |= RCC_APB2ENR_TIM1EN;
 #endif
 
-#if CONFIG_STM32_TIM8
+#ifdef CONFIG_STM32_TIM8
   /* TIM8 clock enable */
 
   regval |= RCC_APB2ENR_TIM8EN;
 #endif
 
-#if CONFIG_STM32_USART1
+#ifdef CONFIG_STM32_USART1
   /* USART1 clock enable */
 
   regval |= RCC_APB2ENR_USART1EN;
 #endif
 
-#if CONFIG_STM32_USART6
+#ifdef CONFIG_STM32_USART6
   /* USART6 clock enable */
 
   regval |= RCC_APB2ENR_USART6EN;
 #endif
 
-#if CONFIG_STM32_ADC1
+#ifdef CONFIG_STM32_ADC1
   /* ADC1 clock enable */
 
   regval |= RCC_APB2ENR_ADC1EN;
 #endif
 
-#if CONFIG_STM32_ADC2
+#ifdef CONFIG_STM32_ADC2
   /* ADC2 clock enable */
 
   regval |= RCC_APB2ENR_ADC2EN;
 #endif
 
-#if CONFIG_STM32_ADC3
+#ifdef CONFIG_STM32_ADC3
   /* ADC3 clock enable */
 
   regval |= RCC_APB2ENR_ADC3EN;
 #endif
 
-#if CONFIG_STM32_SDIO
+#ifdef CONFIG_STM32_SDIO
   /* SDIO clock enable */
 
   regval |= RCC_APB2ENR_SDIOEN;
 #endif
 
-#if CONFIG_STM32_SPI1
+#ifdef CONFIG_STM32_SPI1
   /* SPI1 clock enable */
 
   regval |= RCC_APB2ENR_SPI1EN;
 #endif
 
-#if CONFIG_STM32_SYSCFG
+#ifdef CONFIG_STM32_SYSCFG
   /* System configuration controller clock enable */
 
   regval |= RCC_APB2ENR_SYSCFGEN;
 #endif
 
-#if CONFIG_STM32_TIM9
+#ifdef CONFIG_STM32_TIM9
   /* TIM9 clock enable */
 
   regval |= RCC_APB2ENR_TIM9EN;
 #endif
 
-#if CONFIG_STM32_TIM10
+#ifdef CONFIG_STM32_TIM10
   /* TIM10 clock enable */
 
   regval |= RCC_APB2ENR_TIM10EN;
 #endif
 
-#if CONFIG_STM32_TIM11
+#ifdef CONFIG_STM32_TIM11
   /* TIM11 clock enable */
 
   regval |= RCC_APB2ENR_TIM11EN;
diff --git a/nuttx/configs/stm3210e-eval/README.txt b/nuttx/configs/stm3210e-eval/README.txt
index 9b1615f42..e08d0bfa5 100755
--- a/nuttx/configs/stm3210e-eval/README.txt
+++ b/nuttx/configs/stm3210e-eval/README.txt
@@ -458,7 +458,7 @@ STM3210E-EVAL-specific Configuration Options
     CONFIG_STM32_I2C1
     CONFIG_STM32_I2C2
     CONFIG_STM32_USB
-    CONFIG_STM32_CAN
+    CONFIG_STM32_CAN1
     CONFIG_STM32_BKP
     CONFIG_STM32_PWR
     CONFIG_STM32_DAC1
@@ -698,6 +698,22 @@ Where <subdir> is one of the following:
 
         Failure to do this could result in corruption of the SD card format.
 
+    The nsh2 contains support for some built-in applications that can be
+    enabled by make some additional minor changes:
+
+    (1) examples/can.  The CAN test example can be enabled by changing the
+        following settings in nsh2/defconfig:
+
+        CONFIG_CAN=y             # Enable CAN "upper-half" driver support
+        CONFIG_STM32_CAN1=y      # Enable STM32 CAN1 "lower-half" driver support
+
+        The default CAN settings may need to change in your board board
+        configuration:
+
+        CONFIG_CAN_EXTID=y       # Support extended IDs
+        CONFIG_CAN1_BAUD=250000  # Bit rate: 250 KHz
+        CONFIG_CAN_TSEG1=12      # 80% sample point
+        CONFIG_CAN_TSEG2=3
   nx:
   ---
     An example using the NuttX graphics system (NX).  This example
diff --git a/nuttx/configs/stm3210e-eval/nsh2/appconfig b/nuttx/configs/stm3210e-eval/nsh2/appconfig
index fb6bf1a66..ff12c4103 100644
--- a/nuttx/configs/stm3210e-eval/nsh2/appconfig
+++ b/nuttx/configs/stm3210e-eval/nsh2/appconfig
@@ -2,7 +2,7 @@
 # configs/stm3210e-eval/nsh2/appconfig
 #
 #   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
@@ -48,4 +48,8 @@ CONFIGURED_APPS += examples/nx
 CONFIGURED_APPS += examples/nxhello
 CONFIGURED_APPS += examples/usbstorage
 
+# Applications configured as an NX built-in commands
 
+ifeq ($(CONFIG_CAN),y)
+CONFIGURED_APPS += examples/can
+endif
diff --git a/nuttx/configs/stm3210e-eval/nsh2/defconfig b/nuttx/configs/stm3210e-eval/nsh2/defconfig
index 369a1fcc8..e7ffc8bc6 100644
--- a/nuttx/configs/stm3210e-eval/nsh2/defconfig
+++ b/nuttx/configs/stm3210e-eval/nsh2/defconfig
@@ -1,7 +1,7 @@
 ############################################################################
 # configs/stm3210e-eval/nsh2/defconfig
 #
-#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -116,6 +116,27 @@ CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n
 CONFIG_STM32_JTAG_SW_ENABLE=n
 
 #
+# Alternate pin mappings
+#
+CONFIG_STM32_TIM1_FULL_REMAP=n
+CONFIG_STM32_TIM1_PARTIAL_REMAP=n
+CONFIG_STM32_TIM2_FULL_REMAP=n
+CONFIG_STM32_TIM2_PARTIAL_REMAP_1=n
+CONFIG_STM32_TIM2_PARTIAL_REMAP_2=n
+CONFIG_STM32_TIM3_FULL_REMAP=n
+CONFIG_STM32_TIM3_PARTIAL_REMAP=n
+CONFIG_STM32_TIM4_REMAP=n
+CONFIG_STM32_USART1_REMAP=n
+CONFIG_STM32_USART2_REMAP=n
+CONFIG_STM32_USART3_FULL_REMAP=n
+CONFIG_STM32_USART3_PARTIAL_REMAP=n
+CONFIG_STM32_SPI1_REMAP=n
+CONFIG_STM32_SPI3_REMAP=n
+CONFIG_STM32_I2C1_REMAP=n
+CONFIG_STM32_CAN1_REMAP1=y
+CONFIG_STM32_CAN1_REMAP2=n 
+
+#
 # Individual subsystems can be enabled:
 # AHB: 
 CONFIG_STM32_DMA1=n
@@ -140,7 +161,8 @@ CONFIG_STM32_UART5=n
 CONFIG_STM32_I2C1=y
 CONFIG_STM32_I2C2=n
 CONFIG_STM32_USB=y
-CONFIG_STM32_CAN=n
+CONFIG_STM32_CAN1=n
+CONFIG_STM32_CAN2=n
 CONFIG_STM32_BKP=n
 CONFIG_STM32_PWR=n
 CONFIG_STM32_DAC=n
@@ -240,6 +262,36 @@ CONFIG_STM32_SPFD5408B_DISABLE=n
 CONFIG_STM32_R61580_DISABLE=y
 
 #
+# STM32F10xxx specific CAN device driver settings
+#
+# CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+#   CONFIG_STM32_CAN2 must also be defined)
+# CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID.  Default
+#   Standard 11-bit IDs.
+# CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+#   Default: 8
+# CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+#   Default: 4
+# CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+#   mode for testing. The STM32 CAN driver does support loopback mode.
+# CONFIG_CAN1_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN1 is defined.
+# CONFIG_CAN2_BAUD - CAN1 BAUD rate.  Required if CONFIG_STM32_CAN2 is defined.
+# CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
+# CONFIG_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
+#
+CONFIG_CAN=n
+CONFIG_CAN_EXTID=y
+#CONFIG_CAN_FIFOSIZE
+#CONFIG_CAN_NPENDINGRTR
+CONFIG_CAN_LOOPBACK=n
+# ISO-11783 requires the baud to be set to 250K
+CONFIG_CAN1_BAUD=250000
+CONFIG_CAN2_BAUD=250000
+# ISO-11783 requires the sample point to be within 75 to 80%
+CONFIG_CAN_TSEG1=12
+CONFIG_CAN_TSEG2=3
+
+#
 # General build options
 #
 # CONFIG_RRLOAD_BINARY - make the rrload binary format used with
@@ -360,6 +412,7 @@ CONFIG_DEBUG_GRAPHICS=n
 CONFIG_DEBUG_LCD=n
 CONFIG_DEBUG_USB=n
 CONFIG_DEBUG_SYMBOLS=n
+CONFIG_DEBUG_CAN=n
 CONFIG_HAVE_CXX=n
 CONFIG_MM_REGIONS=1
 CONFIG_ARCH_LOWPUTC=y
@@ -1126,6 +1179,22 @@ CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
 CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
 CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
 
+# Settings for examples/can
+#
+# CONFIG_CAN - Enables CAN support.
+# CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+#   mode for testing. The STM32 CAN driver does support loopback mode.
+# CONFIG_NSH_BUILTIN_APPS - Build the CAN test as an NSH built-in function.
+#   Default: Built as a standalone problem
+#
+# CONFIG_EXAMPLES_CAN_DEVPATH - The path to the CAN device. Default: /dev/can0
+# CONFIG_EXAMPLES_CAN_NMSGS - If CONFIG_NSH_BUILTIN_APPS
+#   is defined, then the number of loops is provided on the command line
+#   and this value is ignored.  Otherwise, this number of CAN message is
+#   collected and the program terminates.  Default:  If built as an NSH
+#   built-in, the default is 32.  Otherwise messages are sent and received
+#   indefinitely.
+
 #
 # Settings for examples/nx
 #
diff --git a/nuttx/configs/stm3210e-eval/src/Makefile b/nuttx/configs/stm3210e-eval/src/Makefile
index d7247619a..a4e83483b 100644
--- a/nuttx/configs/stm3210e-eval/src/Makefile
+++ b/nuttx/configs/stm3210e-eval/src/Makefile
@@ -68,6 +68,10 @@ ifeq ($(CONFIG_I2C_LM75),y)
 CSRCS		+= up_lm75.c
 endif
 
+ifeq ($(CONFIG_CAN),y)
+CSRCS		+= up_can.c
+endif
+
 COBJS		= $(CSRCS:.c=$(OBJEXT))
 
 SRCS		= $(ASRCS) $(CSRCS)
diff --git a/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h b/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h
index 25b1da320..5cb5e91af 100644
--- a/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h
+++ b/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h
@@ -60,6 +60,12 @@
 #  undef CONFIG_STM32_SPI2
 #endif
 
+/* There is only CAN1 on the STM3210E-EVAL board */
+
+#if defined(CONFIG_STM32_CAN2)
+#  warning "The STM3210E-EVAL only supports CAN1"
+#endif
+
 /* STM3210E-EVAL GPIOs **************************************************************/
 /* LEDs */
 
diff --git a/nuttx/configs/stm3210e-eval/src/up_can.c b/nuttx/configs/stm3210e-eval/src/up_can.c
new file mode 100644
index 000000000..7ca712daf
--- /dev/null
+++ b/nuttx/configs/stm3210e-eval/src/up_can.c
@@ -0,0 +1,134 @@
+/************************************************************************************
+ * configs/stm3210e-eval/src/up_can.c
+ * arch/arm/src/board/up_can.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "stm32.h"
+#include "stm32_can.h"
+#include "stm3210e-internal.h"
+
+#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+/* The STM32F103ZE supports only CAN1 */
+
+#define CAN_PORT 1
+
+/* Debug ***************************************************************************/
+/* Non-standard debug that may be enabled just for testing CAN */
+
+#ifdef CONFIG_DEBUG_CAN
+#  define candbg    dbg
+#  define canvdbg   vdbg
+#  define canlldbg  lldbg
+#  define canllvdbg llvdbg
+#else
+#  define candbg(x...)
+#  define canvdbg(x...)
+#  define canlldbg(x...)
+#  define canllvdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: can_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/can.
+ *
+ ************************************************************************************/
+
+int can_devinit(void)
+{
+  static bool initialized = false;
+  struct can_dev_s *can;
+  int ret;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Call stm32_caninitialize() to get an instance of the CAN interface */
+
+      can = stm32_caninitialize(CAN_PORT);
+      if (can == NULL)
+        {
+          candbg("ERROR:  Failed to get CAN interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the CAN driver at "/dev/can0" */
+
+      ret = can_register("/dev/can0", can);
+      if (ret < 0)
+        {
+          candbg("ERROR: can_register failed: %d\n", ret);
+          return ret;
+        }
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+}
+
+#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */
diff --git a/nuttx/configs/stm3240g-eval/src/up_can.c b/nuttx/configs/stm3240g-eval/src/up_can.c
index 713a5325a..6fcbbb211 100644
--- a/nuttx/configs/stm3240g-eval/src/up_can.c
+++ b/nuttx/configs/stm3240g-eval/src/up_can.c
@@ -2,7 +2,7 @@
  * configs/stm3240g-eval/src/up_can.c
  * arch/arm/src/board/up_can.c
  *
- *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -139,4 +139,4 @@ int can_devinit(void)
   return OK;
 }
 
-#endif /* CONFIG_CAN && (CONFIG_STM32_CAN2 || CONFIG_STM32_CAN3) */
+#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */