arch/arm/src/armv7-a/arm_l2cc_pl310.c, l2cc.h, l2cc_pl310.h, Kconfig: Add initiali support for the ARM L2CC-PL310 L2 cache.

5 files changed, 1217 insertions, 20 deletions

diff --git a/nuttx/arch/arm/src/armv7-a/Kconfig b/nuttx/arch/arm/src/armv7-a/Kconfig
index 5f2b3fdec..a8291d89e 100644
--- a/nuttx/arch/arm/src/armv7-a/Kconfig
+++ b/nuttx/arch/arm/src/armv7-a/Kconfig
@@ -5,14 +5,38 @@
 
 comment "ARMv7-A Configuration Options"
 
+config ARMV7A_HAVE_L2CC
+	bool
+	default n
+	---help---
+	Selected by the configuration tool if the architecutre supports any kind of L2 cache.
+
 config ARMV7A_HAVE_L2CC_PL310
 	bool
 	default n
+	select ARMV7A_HAVE_L2CC
+	---help---
+		Set by architecture-specific code if the hardware supports a PL310
+		r3p2 L2 cache (only version r3p2 is supported).
+
+if ARMV7A_HAVE_L2CC
+
+menu "L2 Cache Configuration"
+
+config ARMV7A_L2CC
+	bool
+	default n
+		---help---
+		Set by the configuration tool if the architecture specific L2CC is
+		enabled.  This is an architecture-independent setting to inform
+		firmware that an L2 cache is present and that standard L2 cache
+		operations are supported.
 
 config ARMV7A_L2CC_PL310
 	bool "ARMv7-A L2CC P310 Support"
 	default n
 	depends on ARMV7A_HAVE_L2CC_PL310
+	select ARMV7A_L2CC
 	---help---
 		Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
 		multi-way cache macrocell, version r3p2.  The addition of an on-chip
@@ -25,7 +49,6 @@ if ARMV7A_L2CC_PL310
 config PL310_LOCKDOWN_BY_MASTER
 	bool "PL310 Lockdown by Master"
 	default n
-	depends on ARMV7A_L2CC_PL310
 
 config PL310_LOCKDOWN_BY_LINE
 	bool "PL310 Lockdown by Line"
@@ -38,6 +61,57 @@ config PL310_ADDRESS_FILTERING
 endif # ARMV7A_L2CC_PL310
 
 choice
+	prompt "L2 Cache Associativity"
+	default ARMV7A_ASSOCIATIVITY_8WAY
+	depends on ARMV7A_L2CC
+	---help---
+		This choice specifies the associativity of L2 cache in terms of the
+		number of ways.  This value could be obtained by querying cache
+		configuration registers.  However, by defining a configuration
+		setting instead, we can avoid using RAM memory to hold information
+		about properties of the memory.
+
+config ARMV7A_ASSOCIATIVITY_8WAY
+	bool "8-Way Associativity"
+
+config ARMV7A_ASSOCIATIVITY_16WAY
+	bool "16-Way Associativity"
+
+endchoice # L2 Cache Associativity
+
+choice
+	prompt "L2 Cache Way Size"
+	default ARMV7A_WAYSIZE_16KB
+	depends on ARMV7A_L2CC
+	---help---
+		This choice specifies size of each way. This value can be obtained
+		by querying cache configuration registers.  However, by defining a
+		configuration setting instead, we can avoid using RAM memory to hold
+		information
+
+config ARMV7A_WAYSIZE_16KB
+	bool "16 KiB"
+
+config ARMV7A_WAYSIZE_32KB
+	bool "32 KiB"
+
+config ARMV7A_WAYSIZE_64KB
+	bool "64 KiB"
+
+config ARMV7A_WAYSIZE_128KB
+	bool "128 KiB"
+
+config ARMV7A_WAYSIZE_256KB
+	bool "256 KiB"
+
+config ARMV7A_WAYSIZE_512KB
+	bool "512 KiB"
+
+endchoice # L2 Cache Associativity
+endmenu # L2 Cache Configuration
+endif # 
+
+choice
 	prompt "Toolchain Selection"
 	default ARMV7A_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
 	default ARMV7A_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
@@ -80,7 +154,7 @@ config ARMV7A_TOOLCHAIN_GNU_OABI
 	---help---
 		This option should work for any GNU toolchain configured for arm-elf-.
 
-endchoice
+endchoice # ARMV7A_HAVE_L2CC
 
 config ARMV7A_OABI_TOOLCHAIN
 	bool "OABI (vs EABI)"
diff --git a/nuttx/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/nuttx/arch/arm/src/armv7-a/arm_l2cc_pl310.c
new file mode 100644
index 000000000..55568270e
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -0,0 +1,862 @@
+/************************************************************************************
+ * arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
+ *   Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
+ *
+ * NOTE: This logic is incompatible with older versions of the PL310!
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "up_arch.h"
+#include "l2cc.h"
+#include "l2cc_pl310.h"
+
+#ifdef CONFIG_ARMV7A_L2CC_PL310
+
+/***************************************************************************
+ * Pre-Processor Definitions
+ ***************************************************************************/
+/* Configuration ***********************************************************/
+/* Number of ways depends on ARM configuration */
+
+#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+#  define PL310_NWAYS      8
+#  define PL310_WAY_MASK   0x000000ff
+#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+#  define PL310_NWAYS 16
+#  define PL310_WAY_MASK   0x0000ffff
+#else
+#  error "Number of ways not selected"
+#endif
+
+/* The size of one depends on ARM configuration */
+
+#if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
+#  define PL310_WAYSIZE (16*1024)
+#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
+#  define PL310_WAYSIZE (32*1024)
+#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
+#  define PL310_WAYSIZE (64*1024)
+#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
+#  define PL310_WAYSIZE (128*1024)
+#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
+#  define PL310_WAYSIZE (256*1024)
+#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
+#  define PL310_WAYSIZE (512*1024)
+#else
+#  error "Way size not selected"
+#endif
+
+/* The size of the cache is then the product of the number of ways times
+ * the size of each way.
+ */
+
+#define PL310_CACHE_SIZE           (PL310_NWAYS * PL310_WAYSIZE)
+
+/* Use for aligning addresses to a cache line boundary */
+
+#define PL310_CACHE_LINE_MASK      (PL310_CACHE_LINE_SIZE - 1)
+
+/* Configurable options
+ *
+ * REVISIT: Currently there are not configuration options.  All values
+ * are just set to the default.
+ */
+
+/* Bit 0:  Full line zero enable
+ *
+ * Default:  0=Full line of write zero behavior disabled
+ */
+
+#define L2CC_ACR_FLZE_CONFIG       (0)  /* 0=Full line of write zero behavior disabled */
+
+/* Bit 10: High Priority for SO and Dev Reads Enable
+ *
+ * Default: 0=Strongly Ordered and Device reads have lower priority than
+ *          cacheable accesses
+ */
+
+#define L2CC_ACR_HPSO_CONFIG       (0) /* 0=Have lower priority than cache */
+
+/* Bit 11: Store Buffer Device Limitation Enable
+ *
+ * Default: 0=Store buffer device limitation disabled
+ */
+
+#define L2CC_ACR_SBDLE_CONFIG     (0) /* 0=Store buffer device limitation disabled */
+
+/* Bit 12: Exclusive Cache Configuration
+ *
+ * Default: 0=Disabled
+ */
+
+#define L2CC_ACR_EXCC_CONFIG       (0) /* 0=Disabled */
+
+/* Bit 13: Shared Attribute Invalidate Enable
+ *
+ * Default: 0=Shared invalidate behavior disabled
+ */
+
+#define L2CC_ACR_SAIE_CONFIG       (0) /* 0=Shared invalidate behavior disabled */
+
+/* Bit 20: Event Monitor Bus Enable
+ *
+ * Default: 0=Disabled
+ */
+
+#define L2CC_ACR_EMBEN_CONFIG      (0) /* 0=Disabled */
+
+/* Bit 21: Parity Enable
+ *
+ * Default: 0=Disabled
+ */
+
+#define L2CC_ACR_PEN_CONFIG        (0) /* 0=Disabled */
+
+/* Bit 22: Shared Attribute Override Enable
+ *
+ * Default: 0=Treats shared accesses as specified in the TRM
+ */
+
+#define L2CC_ACR_SAOEN_CONFIG      (0) /* 0=As specified in the TRM */
+
+/* Bits 23-24:  Force Write Allocate
+ *
+ * Default: 0=Use AWCACHE attributes for WA
+ */
+
+#define L2CC_ACR_FWA_CONFIG        L2CC_ACR_FWA_AWCACHE /* Use AWCACHE attributes for WA */
+
+/* Bit 25: Cache Replacement Policy
+ *
+ * Default: 0=Pseudo-random replacement using lfsr
+ */
+
+#define L2CC_ACR_CRPOL_CONFIG      (0) /* 0=Pseudo-random replacement */
+
+/* Bit 26: Non-Secure Lockdown Enable
+ *
+ * Default: 0=Lockdown registers cannot be modified using non-secure acceses
+ */
+
+#define L2CC_ACR_NSLEN_CONFIG      (0) /* 0=Secure access only */
+
+/* Bit 27: Non-Secure Interrupt Access Control
+ *
+ * Default: 0=Interrupt Clear and Mask can only be modified or read with
+ *          secure accesses
+ */
+
+#define L2CC_ACR_NSIAC_CONFIG      (0) /* 0=Secure access only */
+
+/* Bit 28: Data Prefetch Enable
+ *
+ * Default: 0=Data prefetching disabled
+ */
+
+#define L2CC_ACR_DPEN_CONFIG       (0) /* 0=Data prefetching disabled */
+
+/* Bit 29: Instruction Prefetch Enable
+ *
+ * Default: 0=Instruction prefetching disabled
+ */
+
+#define L2CC_ACR_IPEN_CONFIG       (0) /* 0=Instruction prefetching disabled */
+
+/* Bit 30: Early BRESP enable
+ *
+ * Default: 0=Early BRESP disabled
+ */
+
+#define L2CC_ACR_EBRESP_CONFIG     (0) /* 0=Early BRESP disabled */
+
+#define L2CC_ACR_CONFIG \
+  (L2CC_ACR_FLZE_CONFIG  | L2CC_ACR_HPSO_CONFIG  | L2CC_ACR_SBDLE_CONFIG | \
+   L2CC_ACR_EXCC_CONFIG  | L2CC_ACR_SAIE_CONFIG  | L2CC_ACR_EMBEN_CONFIG | \
+   L2CC_ACR_PEN_CONFIG   | L2CC_ACR_SAOEN_CONFIG | L2CC_ACR_FWA_CONFIG   | \
+   L2CC_ACR_CRPOL_CONFIG | L2CC_ACR_NSLEN_CONFIG | L2CC_ACR_NSIAC_CONFIG | \
+   L2CC_ACR_DPEN_CONFIG  | L2CC_ACR_IPEN_CONFIG  | L2CC_ACR_EBRESP_CONFIG)
+
+#define L2CC_ACR_ALLCONFIGS        (0x7f303c01)
+#define L2CC_ACR_CONFIGMASK        (L2CC_ACR_SBZ | L2CC_ACR_ALLCONFIGS)
+
+/* Filter end address */
+
+#define CONFIG_PL310_FLEND         (CONFIG_PL310_FLSTRT + CONFIG_PL310_FLSIZE)
+
+/* Block size.  Used to break up long operations so that interrupts are not
+ * disabled for a long time.
+ */
+
+#define PL310_GULP_SIZE            4096
+
+/* Misc commoly defined and re-defined things */
+
+#ifndef MIN
+#  define MIN(a,b)                 (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef MAX
+#  define MAX(a,b)                 (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef OK
+#  define OK                       0
+#endif
+
+/* Data synchronization barrier */
+
+#define dsb(a) __asm__ __volatile__ ("dsb " #a : : : "memory")
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: pl310_flush_all
+ *
+ * Description:
+ *   Flush all ways using the Clean Invalidate Way Register (CIWR).
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+static void pl310_flush_all(void)
+{
+  /* Flush all ways by writing the set of ways to be cleaned to the Clean
+   * Invalidate Way Register (CIWR).
+   */
+
+  putreg32(PL310_WAY_MASK, L2CC_CIWR);
+
+  /* Wait for cache operation by way to complete */
+
+  while ((getreg32(L2CC_CIWR) & PL310_WAY_MASK) != 0);
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+ 
+  putreg32(0, L2CC_CSR);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/***************************************************************************
+ * Name: l2cc_initialize
+ *
+ * Description:
+ *   One time configuration of the L2 cache.  The L2 cache will be enabled
+ *   upon return.
+ *
+ * Input Parameters:
+ *   None.  The L2 cache configuration is controlled by configuration
+ *   settings.
+ *
+ * Returned Value:
+ *   Always returns OK.
+ *
+ ***************************************************************************/
+
+int l2cc_initialize(void)
+{
+  uint32_t regval;
+  int i;
+
+  /* Make sure that this is a PL310 cache, version r3p2 */
+
+  DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
+
+  /* Make sure that actual cache configuration agrees with the configured
+   * cache configuration.
+   */
+
+#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
+#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1);
+#endif
+
+#if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB);
+#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB);
+#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB);
+#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB);
+#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
+#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
+  DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
+#endif
+
+  /* L2 configuration can only be changed if the cache is disabled,
+   *
+   * NOTE: This register access will fail if we are not in secure more.
+   */
+
+  if ((getreg32(L2CC_CR) & L2CC_CR_L2CEN) == 0)
+    {
+#if defined(CONFIG_PL310_TRCR_TSETLAT) && defined(CONFIG_PL310_TRCR_TRDLAT) && \
+    defined(CONFIG_PL310_TRCR_TWRLAT)
+      /* Configure Tag RAM control */
+
+      regval = ((CONFIG_PL310_TRCR_TSETLAT - 1) << L2CC_TRCR_TSETLAT_SHIFT)
+               ((CONFIG_PL310_TRCR_TRDLAT - 1) << L2CC_TRCR_TRDLAT_SHIFT) |
+               ((CONFIG_PL310_TRCR_TWRLAT - 1) << L2CC_TRCR_TWRLAT_SHIFT);
+      putreg32(regval, L2CC_TRCR);
+#endif
+
+#if defined(CONFIG_PL310_DRCR_DSETLAT) && defined(CONFIG_PL310_DRCR_DRDLAT) && \
+    defined(CONFIG_PL310_DRCR_DWRLAT)
+      /* Configure Data RAM control */
+
+      regval = ((CONFIG_PL310_DRCR_DSETLAT - 1) << L2CC_DRCR_DSETLAT_SHIFT) |
+               ((CONFIG_PL310_DRCR_DRDLAT - 1) << L2CC_DRCR_DRDLAT_SHIFT) |
+               ((CONFIG_PL310_DRCR_DWRLAT - 1) << L2CC_DRCR_DWRLAT_SHIFT);
+      putreg32(regval, L2CC_DRCR);
+#endif
+
+#ifdef PL310_ADDRESS_FILTERING
+#if defined(CONFIG_PL310_FLSTRT) && defined(CONFIG_PL310_FLSIZE)
+      /* Configure the address filter */
+
+      regval = (CONFIG_PL310_FLEND + ~L2CC_FLEND_MASK) & L2CC_FLEND_MASK;
+      putreg32(regval, L2CC_FLEND);
+
+      regval = (CONFIG_PL310_FLSTRT & L2CC_FLSTRT_MASK) | L2CC_FLSTRT_ENABLE;
+      putreg32(regval | L2X0_ADDR_FILTER_EN, L2CC_FLSTRT);
+#endif
+#endif
+
+      /* Make sure that the memory is not locked down */
+
+      for (i = 0; i < PL310_NLOCKREGS; i++)
+        {
+          putreg32(0, L2CC_DLKR_OFFSET(i));
+          putreg32(0, L2CC_ILKR_OFFSET(i));
+        }
+
+      /* Configure the cache properties */
+
+      regval  = getreg32(L2CC_ACR);
+      regval &= ~L2CC_ACR_CONFIGMASK;
+      regval |= L2CC_ACR_CONFIG;
+      putreg32(regval, L2CC_ACR);
+
+      /* Invalidate and enable the cache */
+
+      l2cc_invalidate_all();
+      putreg32(L2CC_CR_L2CEN, L2CC_CR);
+    }
+
+  lldbg("(%d ways) * (%d bytes/way) = %d bytes\n",
+        PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
+
+  return OK;
+}
+
+/***************************************************************************
+ * Name: l2cc_enable
+ *
+ * Description:
+ *    Re-enable the L2CC-P310 L2 cache by setting the enable bit in the
+ *    Control Register (CR)
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    None
+ *
+ ***************************************************************************/
+
+void l2cc_enable(void)
+{
+  irqstate_t flags;
+
+  /* Invalidate and enable the cache (must be disabled to do this!) */
+
+  flags = irqsave();
+  l2cc_invalidate_all();
+  putreg32(L2CC_CR_L2CEN, L2CC_CR);
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_disable
+ *
+ * Description:
+ *    Disable the L2CC-P310 L2 cache by clearing the Control Register (CR)
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    None
+ *
+ ***************************************************************************/
+
+void l2cc_disable(void)
+{
+  irqstate_t flags;
+
+  /* Flush all ways using the Clean Invalidate Way Register (CIWR). */
+
+  flags = irqsave();
+  pl310_flush_all();
+
+  /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */
+
+  putreg32(0, L2CC_CR);
+  dsb();
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_sync
+ *
+ * Description:
+ *   Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+ *   EB, are empty.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_sync(void)
+{
+  irqstate_t flags;
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+
+  flags = irqsave();
+  putreg32(0, L2CC_CSR);
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_invalidate_all
+ *
+ * Description:
+ *   Invalidate all ways using the Invalidate Way Register (IWR).
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+static void l2cc_invalidate_all(void)
+{
+  irqstate_t flags;
+
+  /* Invalidate all ways */
+
+  flags = irqsave();
+
+  /* Verify that we are not attempting to invalidate the L2 cache while it
+   * is enabled
+   */
+
+  DEBUGASSERT((getreg32(L2CC_CR) & L2CC_CR_L2CEN) == 0);
+
+  /* Invalidate all ways by writing the bit mask of ways to be invalidated
+   * the Invalidate Way Register (IWR).
+   */
+
+  putreg32(PL310_WAY_MASK, L2CC_IWR);
+
+  /* Wait for cache operation by way to complete */
+
+  while ((getreg32(L2CC_IWR) & PL310_WAY_MASK) != 0);
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+ 
+  putreg32(0, L2CC_CSR);
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_invalidate
+ *
+ * Description:
+ *   Invalidate a range of addresses by writing to the Invalidate Physical
+ *   Address Line Register (IPALR) repeatedly.
+ *
+ * Input Parameters:
+ *   startaddr - The first address to be invalidated
+ *   endaddr   - The last address to be invalidated
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_invalidate(uintptr_t startaddr, uintptr_t endaddr)
+{
+  uintptr_t invalsize;
+  uintptr_t gulpend;
+  irqstate_t flags;
+
+  /* Check if the start address is aligned with a cacheline */
+
+  flags = irqsave();
+  if ((startaddr & PL310_CACHE_LINE_MASK) != 0)
+    {
+      /* No.. align down and flush the cache line by writing the address to
+       * the Clean Invalidate Physical Address Line Register (CIPALR).
+       */
+
+      startaddr &= ~PL310_CACHE_LINE_MASK;
+      putreg32(startaddr, L2CC_CIPALR);
+
+      /* Then start invalidating at the next cache line */
+
+      startaddr += PL310_CACHE_LINE_SIZE;
+    }
+
+  /* Check if the end address is aligned with a cache line */
+
+  if ((endaddr & PL310_CACHE_LINE_MASK) != 0)
+    {
+      /* No.. align down and flush cache line by writing the address to
+       * the Clean Invalidate Physical Address Line Register (CIPALR).
+       */
+
+      endaddr &= ~PL310_CACHE_LINE_MASK;
+      putreg32(endaddr, L2CC_CIPALR);
+    }
+
+  irqrestore(flags);
+
+  /* Loop, invalidated the address range by cache line.  Interrupts are re-
+   * enabled momentarily every PL310_GULP_SIZE bytes.
+   */
+
+  while (startaddr < endaddr)
+    {
+      /* Get the size of the next gulp of cache lines to invalidate.  We do
+       * this in small chunks so that we do not have to keep interrupts
+       * disabled throughout the whole flush.
+       */
+
+      invalsize = endaddr - startaddr;
+      gulpend   = startaddr + MIN(invalsize, PL310_GULP_SIZE);
+
+      /* Disable interrupts and invalidate the gulp */
+
+      flags = irqsave();
+      while (startaddr < gulpend)
+        {
+          /* Invalidate the cache line by writing the address to the
+           * Invalidate Physical Address Line Register (IPALR).
+           */
+
+          putreg32(startaddr, L2CC_IPALR);
+
+          /* Start of the next cache line */
+
+          startaddr += PL310_CACHE_LINE_SIZE;
+        }
+
+      /* Enable interrupts momentarily */
+
+      irqrestore(flags);
+    }
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+ 
+  flags = irqsave();
+  putreg32(0, L2CC_CSR);
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_clean_all
+ *
+ * Description:
+ *   Clean all ways by using the Clean Ways Register (CWR).
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_clean_all(void)
+{
+  irqstate_t flags;
+
+  /* Clean all ways by writing the set of ways to be cleaned to the Clean
+   * Ways Register (CWR).
+   */
+
+  flags = irqsave();
+  putreg32(PL310_WAY_MASK, L2CC_CWR);
+
+  /* Wait for cache operation by way to complete */
+
+  while ((getreg32(L2CC_CWR) & PL310_WAY_MASK) != 0);
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+ 
+  putreg32(0, L2CC_CSR);
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_clean
+ *
+ * Description:
+ *   Clean the cache line over a range of addresses uing the Clean Physical
+ *   Address Line Register (CPALR) repeatedly.
+ *
+ * Input Parameters:
+ *   startaddr - The first address to be cleaned
+ *   endaddr   - The last address to be cleaned
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr)
+{
+  uintptr_t cleansize;
+  uintptr_t gulpend;
+  irqstate_t flags;
+
+  /* If the range of addresses to clean is as large or larger the L2 cache,
+   * then just clean the whole thing.
+   */
+
+  cleansize = endaddr - startaddr;
+  if (cleansize >= PL310_CACHE_SIZE)
+    {
+      l2cc_clean_all();
+      return;
+    }
+
+  /* Align the starting address to a cache line boundary */
+
+  startaddr &= ~PL310_CACHE_LINE_MASK;
+
+  /* Clean the L2 cache by cache line, enabling interrupts momentarily
+   * every PL310_GULP_SIZE bytes.
+   */
+
+  while (startaddr < endaddr)
+    {
+      /* Get the size of the next gulp of cache lines to flush.  We do
+       * this in small chunks so that we do not have to keep interrupts
+       * disabled throughout the whole flush.
+       */
+ 
+      cleansize = endaddr - startaddr;
+      gulpend   = startaddr + MIN(cleansize, PL310_GULP_SIZE);
+
+      /* Disable interrupts and clean the gulp */
+
+      flags = irqsave();
+      while (startaddr < gulpend)
+        {
+          /* Clean the cache line by writing the address to the Clean
+           * Physical Address Line Register (CPALR).
+           */
+
+          putreg32(startaddr, L2CC_CPALR);
+
+          /* Start of the next cache line */
+
+          startaddr += PL310_CACHE_LINE_SIZE;
+        }
+
+      /* Enable interrupts momentarily */
+
+      irqrestore(flags);
+    }
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+ 
+  flags = irqsave();
+  putreg32(0, L2CC_CSR);
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_flush_all
+ *
+ * Description:
+ *   Flush all ways using the Clean Invalidate Way Register (CIWR).
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_flush_all(void)
+{
+  irqstate_t flags;
+
+  /* Flush all ways using the Clean Invalidate Way Register (CIWR). */
+
+  flags = irqsave();
+  pl310_flush_all();
+  irqrestore(flags);
+}
+
+/***************************************************************************
+ * Name: l2cc_flush
+ *
+ * Description:
+ *   Flush a range of address by using the Clean Invalidate Physical Address
+ *   Line Register (CIPALR) repeatedly.
+ *
+ * Input Parameters:
+ *   startaddr - The first address to be flushed
+ *   endaddr   - The last address to be flushed
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_flush(uint32_t startaddr, uint32_t endaddr)
+{
+  uintptr_t  flushsize;
+  uintptr_t  gulpend;
+  irqstate_t flags;
+
+  /* If the range of addresses to flush is as large or larger the L2 cache,
+   * then just flush the whole thing.
+   */
+
+  flushsize = endaddr - startaddr;
+  if (flushsize >= PL310_CACHE_SIZE)
+    {
+      l2cc_flush_all();
+      return;
+    }
+
+  /* Align the starting address to a cache line boundary */
+
+  startaddr &= ~PL310_CACHE_LINE_MASK;
+
+  /* Flush the L2 cache by cache line, enabling interrupts momentarily
+   * every PL310_GULP_SIZE bytes.
+   */
+
+  while (startaddr < endaddr)
+    {
+      /* Get the size of the next gulp of cache lines to flush.  We do
+       * this in small chunks so that we do not have to keep interrupts
+       * disabled throughout the whole flush.
+       */
+ 
+      flushsize = endaddr - startaddr;
+      gulpend   = startaddr + MIN(flushsize, PL310_GULP_SIZE);
+
+      /* Disable interrupts and flush the gulp */
+
+      flags = irqsave();
+      while (startaddr < gulpend)
+        {
+          /* Flush the cache line by writing the address to the Clean
+           * Invalidate Physical Address Line Register (CIPALR).
+           */
+
+          putreg32(startaddr, L2CC_CIPALR);
+
+          /* Start of the next cache line */
+
+          startaddr += PL310_CACHE_LINE_SIZE;
+        }
+
+      /* Enable interrupts momentarily */
+
+      irqrestore(flags);
+    }
+
+  /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
+   * EB, are empty.
+   */
+ 
+  flags = irqsave();
+  putreg32(0, L2CC_CSR);
+  irqrestore(flags);
+}
+
+#endif /* CONFIG_ARMV7A_L2CC_PL310 */
diff --git a/nuttx/arch/arm/src/armv7-a/l2cc.h b/nuttx/arch/arm/src/armv7-a/l2cc.h
new file mode 100644
index 000000000..6fc59d1bb
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-a/l2cc.h
@@ -0,0 +1,242 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/l2cc.h
+ * Non-CP15 Registers
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_H
+#define __ARCH_ARM_SRC_ARMV7_A_L2CC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifdef CONFIG_ARMV7A_L2CC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/***************************************************************************
+ * Name: l2cc_initialize
+ *
+ * Description:
+ *   One time configuration of the L2 cache.  The L2 cache will be enabled
+ *   upon return.
+ *
+ * Input Parameters:
+ *   None.  The L2 cache configuration is controlled by configuration
+ *   settings.
+ *
+ * Returned Value:
+ *   Always returns OK.
+ *
+ ***************************************************************************/
+
+int l2cc_initialize(void);
+
+/***************************************************************************
+ * Name: l2cc_enable
+ *
+ * Description:
+ *    Re-enable the L2CC-P310 L2 cache by setting the enable bit in the
+ *    Control Register (CR)
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    None
+ *
+ ***************************************************************************/
+
+void l2cc_enable(void);
+
+/***************************************************************************
+ * Name: l2cc_disable
+ *
+ * Description:
+ *    Disable the L2 cache
+ *
+ * Input Parameters:
+ *    None
+ *
+ * Returned Value:
+ *    None
+ *
+ ***************************************************************************/
+
+void l2cc_disable(void);
+
+/***************************************************************************
+ * Name: l2cc_sync
+ *
+ * Description:
+ *   Drain the L2 cache.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_sync(void);
+
+/***************************************************************************
+ * Name: l2cc_invalidate_all
+ *
+ * Description:
+ *   Invalidate the entire L2 cache.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+static void l2cc_invalidate_all(void);
+
+/***************************************************************************
+ * Name: l2cc_invalidate
+ *
+ * Description:
+ *   Invalidate a range of addresses in the L2 cache
+ *
+ * Input Parameters:
+ *   startaddr - The first address to be invalidated
+ *   endaddr   - The last address to be invalidated
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_invalidate(uintptr_t startaddr, uintptr_t endaddr);
+
+/***************************************************************************
+ * Name: l2cc_clean_all
+ *
+ * Description:
+ *   Clean the entire L2 cache.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_clean_all(void);
+
+/***************************************************************************
+ * Name: l2cc_clean
+ *
+ * Description:
+ *   Clean a range of address within the L2 cache.
+ *
+ * Input Parameters:
+ *   startaddr - The first address to be cleaned
+ *   endaddr   - The last address to be cleaned
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr);
+
+/***************************************************************************
+ * Name: l2cc_flush_all
+ *
+ * Description:
+ *   Flush the entire L2 cache.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_flush_all(void);
+
+/***************************************************************************
+ * Name: l2cc_flush
+ *
+ * Description:
+ *   Flush a range of address within the L2 cache.
+ *
+ * Input Parameters:
+ *   startaddr - The first address to be flushed
+ *   endaddr   - The last address to be flushed
+ *
+ * Returned Value:
+ *   None
+ *
+ ***************************************************************************/
+
+void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARMV7A_L2CC */
+#endif  /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */
diff --git a/nuttx/arch/arm/src/armv7-a/l2cc_pl310.h b/nuttx/arch/arm/src/armv7-a/l2cc_pl310.h
index 164fa77aa..16d8f723c 100644
--- a/nuttx/arch/arm/src/armv7-a/l2cc_pl310.h
+++ b/nuttx/arch/arm/src/armv7-a/l2cc_pl310.h
@@ -7,6 +7,9 @@
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
+ * Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
+ *   Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -56,7 +59,7 @@
  ************************************************************************************/
 /* General Definitions **************************************************************/
 
-#define CACHE_LINE_SIZE            32
+#define PL310_CACHE_LINE_SIZE      32
 
 #ifdef CONFIG_PL310_LOCKDOWN_BY_MASTER
 #  define PL310_NLOCKREGS          8
@@ -191,28 +194,37 @@
 
 /* Auxiliary Control Register */
 
-#define L2CC_ACR_HPSO              (1 << 10) /* Bit 10:  High Priority for SO and Dev Reads Enable */
-#define L2CC_ACR_SBDLE             (1 << 11) /* Bit 11:  Store Buffer Device Limitation Enable */
-#define L2CC_ACR_EXCC              (1 << 12) /* Bit 12:  Exclusive Cache Configuration */
-#define L2CC_ACR_SAIE              (1 << 13) /* Bit 13:  Shared Attribute Invalidate Enable */
-#define L2CC_ACR_ASS               (1 << 16) /* Bit 16:  Associativity */
+#define L2CC_ACR_FLZE              (1 << 0)  /* Bit 0:  Full line zero enable */
+#define L2CC_ACR_HPSO              (1 << 10) /* Bit 10: High Priority for SO and Dev Reads Enable */
+#define L2CC_ACR_SBDLE             (1 << 11) /* Bit 11: Store Buffer Device Limitation Enable */
+#define L2CC_ACR_EXCC              (1 << 12) /* Bit 12: Exclusive Cache Configuration */
+#define L2CC_ACR_SAIE              (1 << 13) /* Bit 13: Shared Attribute Invalidate Enable */
+#define L2CC_ACR_ASS               (1 << 16) /* Bit 16: Associativity */
 #define L2CC_ACR_WAYSIZE_SHIFT     (17)      /* Bits 17-19: Way Size */
 #define L2CC_ACR_WAYSIZE_MASK      (7 << L2CC_ACR_WAYSIZE_SHIFT)
 #  define L2CC_ACR_WAYSIZE_16KB    (1 << L2CC_ACR_WAYSIZE_SHIFT)
-#define L2CC_ACR_EMBEN             (1 << 20) /* Bit 20:  Event Monitor Bus Enable */
-#define L2CC_ACR_PEN               (1 << 21) /* Bit 21:  Parity Enable */
-#define L2CC_ACR_SAOEN             (1 << 22) /* Bit 22:  Shared Attribute Override Enable */
+#  define L2CC_ACR_WAYSIZE_32KB    (2 << L2CC_ACR_WAYSIZE_SHIFT)
+#  define L2CC_ACR_WAYSIZE_64KB    (3 << L2CC_ACR_WAYSIZE_SHIFT)
+#  define L2CC_ACR_WAYSIZE_128KB   (4 << L2CC_ACR_WAYSIZE_SHIFT)
+#  define L2CC_ACR_WAYSIZE_256KB   (5 << L2CC_ACR_WAYSIZE_SHIFT)
+#  define L2CC_ACR_WAYSIZE_512KB   (6 << L2CC_ACR_WAYSIZE_SHIFT)
+#define L2CC_ACR_EMBEN             (1 << 20) /* Bit 20: Event Monitor Bus Enable */
+#define L2CC_ACR_PEN               (1 << 21) /* Bit 21: Parity Enable */
+#define L2CC_ACR_SAOEN             (1 << 22) /* Bit 22: Shared Attribute Override Enable */
 #define L2CC_ACR_FWA_SHIFT         (23)      /* Bits 23-24:  Force Write Allocate */
 #define L2CC_ACR_FWA_MASK          (3 << L2CC_ACR_FWA_SHIFT)
 #  define L2CC_ACR_FWA_AWCACHE     (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
 #  define L2CC_ACR_FWA_NOALLOC     (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
 #  define L2CC_ACR_FWA_OVERRIDE    (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
 #  define L2CC_ACR_FWA_MAPPED      (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
-#define L2CC_ACR_CRPOL             (1 << 25) /* Bit 25:  Cache Replacement Policy */
-#define L2CC_ACR_NSLEN             (1 << 26) /* Bit 26:  Non-Secure Lockdown Enable */
-#define L2CC_ACR_NSIAC             (1 << 27) /* Bit 27:  Non-Secure Interrupt Access Control */
-#define L2CC_ACR_DPEN              (1 << 28) /* Bit 28:  Data Prefetch Enable */
-#define L2CC_ACR_IPEN              (1 << 29) /* Bit 29:  Instruction Prefetch Enable */
+#define L2CC_ACR_CRPOL             (1 << 25) /* Bit 25: Cache Replacement Policy */
+#define L2CC_ACR_NSLEN             (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
+#define L2CC_ACR_NSIAC             (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
+#define L2CC_ACR_DPEN              (1 << 28) /* Bit 28: Data Prefetch Enable */
+#define L2CC_ACR_IPEN              (1 << 29) /* Bit 29: Instruction Prefetch Enable */
+#define L2CC_ACR_EBRESP            (1 << 30) /* Bit 30: Early BRESP enable */
+
+#define L2CC_ACR_SBZ               (0x8000c1fe)
 
 /* Tag RAM Control Register */
 
@@ -450,6 +462,7 @@
 #ifdef PL310_ADDRESS_FILTERING
 #  define L2CC_FLSTRT_ENABLE       (1 << 0)     /* Bit 0: Address filter enable */
 #  define L2CC_FLSTRT_MASK         (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */
+#endif
 
 /* Address filter end */
 
@@ -465,9 +478,9 @@
 
 /* Prefetch Control Register */
 
-#define L2CC_PCR_OFFSET_SHIFT      (0)       /* Bits 0-4: Prefetch Offset */
-#define L2CC_PCR_OFFSET_MASK       (31 << L2CC_PCR_OFFSET_SHIFT)
-#  define L2CC_PCR_OFFSET(n)       ((uint32_t)(n) << L2CC_PCR_OFFSET_SHIFT)
+#define L2CC_PCR_SHIFT             (0)       /* Bits 0-4: Prefetch Offset */
+#define L2CC_PCR_MASK              (31 << L2CC_PCR_SHIFT)
+#  define L2CC_PCR_PREFETCH(n)     ((uint32_t)(n) << L2CC_PCR_SHIFT)
 #define L2CC_PCR_NSIDEN            (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */
 #define L2CC_PCR_IDLEN             (1 << 23) /* Bit 23: INCR Double Linefill Enable */
 #define L2CC_PCR_PDEN              (1 << 24) /* Bit 24: Prefetch Drop Enable */
diff --git a/nuttx/arch/arm/src/sama5/Make.defs b/nuttx/arch/arm/src/sama5/Make.defs
index b6253c0ed..16ddf12ee 100644
--- a/nuttx/arch/arm/src/sama5/Make.defs
+++ b/nuttx/arch/arm/src/sama5/Make.defs
@@ -54,6 +54,8 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S
 CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
 CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
 
+# Configuration dependent assembly language files
+
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS += arm_memcpy.S
 endif
@@ -71,7 +73,11 @@ CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c
 CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
 CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c
 
-# Configuration dependent C and assembly language files
+# Configuration dependent C files
+
+ifeq ($(CONFIG_ARMV7A_L2CC_PL310),y)
+CMN_CSRCS += arm_l2cc_pl310.c
+endif
 
 ifeq ($(CONFIG_PAGING),y)
 CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c