For all SAM Ethernet, need to enable management interface before reading PHY regisers in IOCTL

4 files changed, 99 insertions, 0 deletions

diff --git a/nuttx/arch/arm/src/sam34/sam_emac.c b/nuttx/arch/arm/src/sam34/sam_emac.c
index 3e4a9b92d..5073db1d6 100644
--- a/nuttx/arch/arm/src/sam34/sam_emac.c
+++ b/nuttx/arch/arm/src/sam34/sam_emac.c
@@ -1826,14 +1826,40 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
   case SIOCGMIIREG: /* Get register from MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      uint32_t regval;
+
+      /* Enable management port */
+
+      regval = sam_getreg(priv, SAM_EMAC_NCR);
+      sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+
+      /* Read from the requested register */
+
       ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+
+      /* Disable management port (probably) */
+
+      sam_putreg(priv, SAM_EMAC_NCR, regval);
     }
     break;
 
   case SIOCSMIIREG: /* Set register in MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      uint32_t regval;
+
+      /* Enable management port */
+
+      regval = sam_getreg(priv, SAM_EMAC_NCR);
+      sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+
+      /* Write to the requested register */
+
       ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+
+      /* Disable management port (probably) */
+
+      sam_putreg(priv, SAM_EMAC_NCR, regval);
     }
     break;
 
diff --git a/nuttx/arch/arm/src/sama5/sam_emaca.c b/nuttx/arch/arm/src/sama5/sam_emaca.c
index 74c39fc7b..61da3490f 100644
--- a/nuttx/arch/arm/src/sama5/sam_emaca.c
+++ b/nuttx/arch/arm/src/sama5/sam_emaca.c
@@ -1867,14 +1867,40 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
   case SIOCGMIIREG: /* Get register from MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      uint32_t regval;
+
+      /* Enable management port */
+
+      regval = sam_getreg(priv, SAM_EMAC_NCR);
+      sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+
+      /* Read from the requested register */
+
       ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+
+      /* Disable management port (probably) */
+
+      sam_putreg(priv, SAM_EMAC_NCR, regval);
     }
     break;
 
   case SIOCSMIIREG: /* Set register in MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      uint32_t regval;
+
+      /* Enable management port */
+
+      regval = sam_getreg(priv, SAM_EMAC_NCR);
+      sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
+
+      /* Write to the requested register */
+
       ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+
+      /* Disable management port (probably) */
+
+      sam_putreg(priv, SAM_EMAC_NCR, regval);
     }
     break;
 
diff --git a/nuttx/arch/arm/src/sama5/sam_emacb.c b/nuttx/arch/arm/src/sama5/sam_emacb.c
index 2f9441cc5..428251d8f 100644
--- a/nuttx/arch/arm/src/sama5/sam_emacb.c
+++ b/nuttx/arch/arm/src/sama5/sam_emacb.c
@@ -2242,14 +2242,40 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
   case SIOCGMIIREG: /* Get register from MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      uint32_t regval;
+
+      /* Enable management port */
+
+      regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+      sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
+
+      /* Read from the requested register */
+
       ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+
+      /* Disable management port (probably) */
+
+      sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
     }
     break;
 
   case SIOCSMIIREG: /* Set register in MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      uint32_t regval;
+
+      /* Enable management port */
+
+      regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
+      sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
+
+      /* Write to the requested register */
+
       ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+
+      /* Disable management port (probably) */
+
+      sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
     }
     break;
 
diff --git a/nuttx/arch/arm/src/sama5/sam_gmac.c b/nuttx/arch/arm/src/sama5/sam_gmac.c
index 02b39319e..5f72bae26 100644
--- a/nuttx/arch/arm/src/sama5/sam_gmac.c
+++ b/nuttx/arch/arm/src/sama5/sam_gmac.c
@@ -1822,14 +1822,35 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
   case SIOCGMIIREG: /* Get register from MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+
+      /* Enable the management port */
+
+      sam_enablemdio(priv);
+
+      /* Read from the requested register */
+
       ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+
+      /* Disable the management port */
+
+      sam_disablemdio(priv);
     }
     break;
 
   case SIOCSMIIREG: /* Set register in MII PHY */
     {
       struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+      /* Enable the management port */
+
+      sam_enablemdio(priv);
+
+      /* Write to the requested register */
+
       ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+
+      /* Disable the management port */
+
+      sam_disablemdio(priv);
     }
     break;