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authorGregory Nutt <gnutt@nuttx.org>2014-03-26 16:32:16 -0600
committerGregory Nutt <gnutt@nuttx.org>2014-03-26 16:32:16 -0600
commit70b49fe5db7ed1ffbb92373d8dab81d09003470d (patch)
tree4adf63608aa1dba8b13d38a7e9251b32d4369fad
parent62057880ff8fa0150248d7e3123b4371311860ae (diff)
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SAM4E CMCC: Fix some errors introducted in last check-in
-rw-r--r--nuttx/arch/arm/src/sam34/chip/sam_cmcc.h3
-rw-r--r--nuttx/arch/arm/src/sam34/sam_cmcc.c33
2 files changed, 23 insertions, 13 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h b/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h
index 440ea72c1..0d0d96b91 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_cmcc.h
@@ -51,6 +51,9 @@
****************************************************************************************/
/* This information is available in the Cache Type Register. How every, it is more
* efficient if we do not to do the decoding on each cache access.
+ *
+ * CacheSize = CacheLineSize * NCacheLines * NWays
+ * CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays
*/
#ifdef CONFIG_ARCH_CHIP_SAM4E
diff --git a/nuttx/arch/arm/src/sam34/sam_cmcc.c b/nuttx/arch/arm/src/sam34/sam_cmcc.c
index 1dd8f660c..3ffee6947 100644
--- a/nuttx/arch/arm/src/sam34/sam_cmcc.c
+++ b/nuttx/arch/arm/src/sam34/sam_cmcc.c
@@ -39,6 +39,7 @@
#include <nuttx/config.h>
+#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
@@ -144,24 +145,31 @@ void sam_cmcc_invalidate(uintptr_t start, uintptr_t end)
{
uintptr_t addr;
uint32_t regval;
- uint32_t way
- uint32_t index;
- size_t size;
- int nlines;
+ ssize_t size;
+ int index;
+ int way;
- /* Get the aligned addresses and size for the memory region to be
- * invalidated.
+ /* Get the aligned addresses and size (in bytes) for the memory region
+ * to be invalidated.
*/
start = ALIGN_DOWN(start);
- end = ALIGN_up(end);
- size = end - start;
+ end = ALIGN_UP(end);
+ size = end - start + 1;
/* If this is a large region (as big as the cache), then just invalidate
* the entire cache the easy way.
+ *
+ * CacheSize = CacheLineSize * NCacheLines * NWays
+ * CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays
+ *
+ * Example: CacheSize = 2048, CacheLineSize=16, NWays=4:
+ *
+ * CacheAddressRange = 2048 / 4 = 512
+ * NCacheLines = 32
*/
- if (size >= (CMCC_CACHE_SIZE / CMCC_CACHE_LINE_SIZE / CMCC_NWAYS)
+ if (size >= (CMCC_CACHE_SIZE / CMCC_NWAYS))
{
sam_cmcc_invalidateall();
return;
@@ -189,10 +197,9 @@ void sam_cmcc_invalidate(uintptr_t start, uintptr_t end)
/* Invalidate the address region */
- index = (start >> CMCC_SHIFT)
- nlines = ((end - start) >> CMCC_SHIFT);
-
- for (addr = start; addr < end; addr += CMCC_CACHE_LINE_SIZE, index++)
+ for (addr = start, index = (int)(start >> CMCC_SHIFT);
+ addr <= end;
+ addr += CMCC_CACHE_LINE_SIZE, index++)
{
regval = CMCC_MAINT1_INDEX(index);
for (way = 0; way < CMCC_NWAYS; way++)