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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-12-02 10:19:37 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-12-02 10:19:37 -0600 |
| commit | 7785482af417aca238e638a94df14df3fec0c6cf (patch) | |
| tree | 75078b7f20a3cae326a291cabb3b26e3fa0aa91f | |
| parent | e027890619865e5af0a2d7c8def703f3787117a8 (diff) | |
| download | nuttx-7785482af417aca238e638a94df14df3fec0c6cf.tar.gz nuttx-7785482af417aca238e638a94df14df3fec0c6cf.tar.bz2 nuttx-7785482af417aca238e638a94df14df3fec0c6cf.zip | |
STM32: Add MCO configuration for the STM32L1xx. From Jussi Kivilinna
| -rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_rcc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h index 80eac8d0a..3c20e031e 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.h +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h @@ -153,6 +153,42 @@ static inline void stm32_mcoconfig(uint32_t source) } #endif +/************************************************************************************ + * Name: stm32_mcodivconfig + * + * Description: + * Selects the clock source to output and clock divider on MC pin (PA4) for + * stm32l1xxx. PA4 should be configured in alternate function mode. + * + * Input Parameters: + * source - One of the definitions for the RCC_CFGR_MCOSEL definitions from + * chip/stm32l15xxx_rcc.h {RCC_CFGR_MCOSEL_DISABLED, RCC_CFGR_MCOSEL_SYSCLK, + * RCC_CFGR_MCOSEL_HSICLK, RCC_CFGR_MCOSEL_MSICLK, RCC_CFGR_MCOSEL_HSECLK, + * RCC_CFGR_MCOSEL_PLLCLK, RCC_CFGR_MCOSEL_LSICLK, RCC_CFGR_MCOSEL_LSECLK} + * divider - One of the definitions for the RCC_CFGR_MCOPRE definitions from + * chip/stm32l15xxx_rcc.h {RCC_CFGR_MCOPRE_DIV1, RCC_CFGR_MCOPRE_DIV2, + * RCC_CFGR_MCOPRE_DIV4, RCC_CFGR_MCOPRE_DIV8, RCC_CFGR_MCOPRE_DIV16} + * + * Returned Value: + * None + * + ************************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) +{ + uint32_t regval; + + /* Set MCO source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCOSEL_MASK); + regval |= (source & RCC_CFGR_MCOSEL_MASK); + regval &= ~(RCC_CFGR_MCOPRE_MASK); + regval |= (divider & RCC_CFGR_MCOPRE_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif /************************************************************************************ * Name: stm32_mco2config |