SAM4E: USART/USART header files and drivers updated to support the SAM4E

4 files changed, 43 insertions, 26 deletions

diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h b/nuttx/arch/arm/src/sam34/chip/sam_uart.h
index a5281d342..c1feac078 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_uart.h
@@ -1,9 +1,9 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam3u_uart.h
+ * arch/arm/src/sam34/chip/sam_uart.h
  * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous
- * Receiver Transmitter (USART) definitions for the SAM3U, SAM3X, SAM3A and SAM4S
+ * Receiver Transmitter (USART) definitions for the SAM3U, SAM3X, SAM3A, SAM4S and SAM4E
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -35,8 +35,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H
 
 /************************************************************************************************
  * Included Files
@@ -80,7 +80,7 @@
 #define SAM_UART_WPMR_OFFSET         0x00e4 /* Write Protect Mode Register (USART only) */
 #define SAM_UART_WPSR_OFFSET         0x00e8 /* Write Protect Status Register (USART only) */
                                             /* 0x005c-0xf8: Reserved (USART) */
-#define SAM_UART_VERSION_OFFSET      0x00fc /* Version Register (USART only) */
+#define SAM_UART_VERSION_OFFSET      0x00fc /* Version Register (USART only, Not SAM4E) */
                                             /* 0x0100-0x0124: PDC Area (Common) */
 
 /* UART register adresses ***********************************************************************/
@@ -313,7 +313,7 @@
 #define UART_MR_OVER                 (1 << 19) /* Bit 19: Oversampling Mode (USART only) */
 #define UART_MR_INACK                (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define UART_MR_WRDBT              (1 << 20) /* Bit 20: Wait Read Data Before Transfer (SPI mode only) */
 #endif
 
@@ -322,6 +322,7 @@
 #define UART_MR_INVDATA              (1 << 23) /* Bit 23: INverted Data (USART only) */
 #define UART_MR_MAXITER_SHIFT        (24)      /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */
 #define UART_MR_MAXITER_MASK         (7 << UART_MR_MAXITER_SHIFT)
+#  define UART_MR_MAXITER(n)         ((uint32_t)(n) << UART_MR_MAXITER_SHIFT)
 #define UART_MR_FILTER               (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */
 #define UART_MR_MAN                  (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */
 #define UART_MR_MODSYNC              (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */
@@ -353,7 +354,7 @@
 #  define UART_INT_LINTC             (1 << 15) /* Bit 15: LIN Transfer Completed Interrupt */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define UART_INT_RIIC              (1 << 16) /* Bit 16: Ring Indicator Input Change */
 #  define UART_INT_DSRIC             (1 << 17) /* Bit 17: Data Set Ready Input Change */
 #  define UART_INT_DCDIC             (1 << 18) /* Bit 18: Data Carrier Detect Input Change Interrupt */
@@ -361,7 +362,7 @@
 
 #define UART_INT_CTSIC               (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define UART_SR_RI                 (1 << 20) /* Bit 20: Image of RI Input */
 #  define UART_SR_DSR                (1 << 21) /* Bit 21: Image of DSR Input */
 #  define UART_SR_DCD                (1 << 22) /* Bit 22: Image of DCD Input */
@@ -430,8 +431,13 @@
 
 /* USART FI DI RATIO Register (USART only) */
 
-#define UART_FIDI_RATIO_SHIFT        (0)       /* Bits 0-10: FI Over DI Ratio Value (USART only) */
-#define UART_FIDI_RATIO_MASK         (0x7ff << UART_FIDI_RATIO_SHIFT)
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define UART_FIDI_RATIO_SHIFT      (0)       /* Bits 0-15: FI Over DI Ratio Value (USART only) */
+#  define UART_FIDI_RATIO_MASK       (0xffff << UART_FIDI_RATIO_SHIFT)
+#else
+#  define UART_FIDI_RATIO_SHIFT      (0)       /* Bits 0-10: FI Over DI Ratio Value (USART only) */
+#  define UART_FIDI_RATIO_MASK       (0x7ff << UART_FIDI_RATIO_SHIFT)
+#endif
 
 /* USART Number of Errors Register (USART only) */
 
@@ -447,6 +453,7 @@
 
 #define UART_MAN_TXPL_SHIFT          (0)       /* Bits 0-3: Transmitter Preamble Length (USART only) */
 #define UART_MAN_TXPL_MASK           (15 << UART_MAN_TXPL_SHIFT)
+#  define UART_MAN_TXPL(n)           ((uint32_t)(n) << UART_MAN_TXPL_SHIFT)
 #define UART_MAN_TXPP_SHIFT          (8)       /* Bits 8-9: Transmitter Preamble Pattern (USART only) */
 #define UART_MAN_TXPP_MASK           (3 << UART_MAN_TXPP_SHIFT)
 #  define UART_MAN_TXPP_ALLONE       (0 << UART_MAN_TXPP_SHIFT) /* ALL_ONE */
@@ -456,6 +463,7 @@
 #define UART_MAN_TXMPOL              (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */
 #define UART_MAN_RXPL_SHIFT          (16)      /* Bits 16-19: Receiver Preamble Length (USART only) */
 #define UART_MAN_RXPL_MASK           (15 << UART_MAN_RXPL_SHIFT)
+#  define UART_MAN_RXPL(n)           ((uint32_t)(n) << UART_MAN_RXPL_SHIFT)
 #define UART_MAN_RXPP_SHIFT          (24)      /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */
 #define UART_MAN_RXPP_MASK           (3 << UART_MAN_RXPP_SHIFT)
 #  define UART_MAN_RXPP_ALLONE       (0 << UART_MAN_RXPP_SHIFT) /* ALL_ONE */
@@ -464,13 +472,12 @@
 #  define UART_MAN_RXPP_ONEZERO      (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */
 #define UART_MAN_RXMPOL              (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define UART_MAN_ONE               (1 << 29) /* Bit 29: Must Be Set to 1 */
 #endif
 
 #define UART_MAN_DRIFT               (1 << 30) /* Bit 30: Drift compensation (USART only) */
 
-
 /* LIN Mode Register (USART only) */
 
 #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -529,4 +536,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H */
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H */
diff --git a/nuttx/arch/arm/src/sam34/sam_lowputc.c b/nuttx/arch/arm/src/sam34/sam_lowputc.c
index aa1538441..63021309c 100644
--- a/nuttx/arch/arm/src/sam34/sam_lowputc.c
+++ b/nuttx/arch/arm/src/sam34/sam_lowputc.c
@@ -1,7 +1,7 @@
 /**************************************************************************
  * arch/arm/src/sam34/sam_lowputc.c
  *
- *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,8 +52,9 @@
 #include "sam_lowputc.h"
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
-    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
-#  include "chip/sam3u_uart.h"
+    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
+    defined(CONFIG_ARCH_CHIP_SAM4E)
+#  include "chip/sam_uart.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #  include "chip/sam4l_usart.h"
 #else
@@ -142,14 +143,16 @@
 
 /* Select MCU-specific settings
  *
- * For the SAM3U, SAM3A, and SAM3X the USARTs are driven by the main clock
- *   (This could be the MCK/8 but that option has not yet been necessary).
+ * For the SAM3U, SAM3A, SAM3X, SAM4E and SAM4S the USARTs are driven by the
+ *   main clock.  (This could also be the MCK/8 or an external clock but
+ *   those options have not yet been necessary).
  * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is
  *   selected by the PBADIVMASK register.
  */
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
-    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
+    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \\
+    defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define SAM_MR_USCLKS    UART_MR_USCLKS_MCK   /* Source = Main clock */
 #  define SAM_USART_CLOCK  BOARD_MCK_FREQUENCY  /* Frequency of the main clock */
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c
index 38106db4e..62805922e 100644
--- a/nuttx/arch/arm/src/sam34/sam_serial.c
+++ b/nuttx/arch/arm/src/sam34/sam_serial.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/sam34/sam_serial.c
  *
- *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2012-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -62,8 +62,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
-    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
-#  include "chip/sam3u_uart.h"
+    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
+    defined(CONFIG_ARCH_CHIP_SAM4E)
+#  include "chip/sam_uart.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
 #  include "chip/sam4l_usart.h"
 #else
@@ -311,14 +312,16 @@
 
 /* Select MCU-specific settings
  *
- * For the SAM3U, SAM3A, and SAM3X the USARTs are driven by the main clock
- *   (This could be the MCK/8 but that option has not yet been necessary).
+ * For the SAM3U, SAM3A, SAM3X, SAM4E and SAM4S the USARTs are driven by the
+ *   main clock.  (This could also be the MCK/8 or an external clock but
+ *   those options have not yet been necessary).
  * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is
  *   selected by the PBADIVMASK register.
  */
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
-    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
+    defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S) || \\
+    defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define SAM_MR_USCLKS    UART_MR_USCLKS_MCK   /* Source = Main clock */
 #  define SAM_USART_CLOCK  BOARD_MCK_FREQUENCY  /* Frequency of the main clock */
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
diff --git a/nuttx/configs/sama5d3x-ek/README.txt b/nuttx/configs/sama5d3x-ek/README.txt
index e306af9a2..42894e1e2 100644
--- a/nuttx/configs/sama5d3x-ek/README.txt
+++ b/nuttx/configs/sama5d3x-ek/README.txt
@@ -3155,6 +3155,10 @@ To-Do List
    appear to work with Windows.  Reformatting on Windows can resolve this.
    NOTE:  This is not a SAMA5Dx issue.
 
+   UPDATE: Two important bugs were recently fixed in the NuttX FAT
+   formatting function (mkfatfs).  It is likely that these fixes will
+   eliminate this issue, but that has not yet been verified.
+
 6) CAN testing has not yet been performed due to issues with cabling.  I
    just do not have a good test bed (or sufficient CAN knowledge) for
    good CAN testing.