Paging update

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2869 42af7a65-404d-4744-a932-0658087f49c3

5 files changed, 137 insertions, 49 deletions

diff --git a/nuttx/arch/arm/src/arm/arm.h b/nuttx/arch/arm/src/arm/arm.h
index 3c4ee051f..1a7bab92e 100644
--- a/nuttx/arch/arm/src/arm/arm.h
+++ b/nuttx/arch/arm/src/arm/arm.h
@@ -193,7 +193,17 @@
                                         /* Bits 11:9:  Should be zero */
 #define PMD_FINE_TEX_MASK   0xfffff000  /* Bits 31:12: v5, Physical page */
 
-/* Level 2 Table Descriptor (PTE).  -- All tables */
+/* Level 2 Table Descriptor (PTE).  A section descriptor provides the base address
+ * of a 1MB block of memory. The page table descriptors provide the base address of
+ * a page table that contains second-level descriptors. There are two sizes of page
+ * table:
+ *   - Coarse page tables have 256 entries, splitting the 1MB that the table
+ *     describes into 4KB blocks
+ *   - Fine/tiny page tables have 1024 entries, splitting the 1MB that the table
+ *     describes into 1KB blocks.
+ *
+ * The following definitions apply to all L2 tables:
+ */
 
 #define PTE_TYPE_MASK       (3 << 0)    /* Bits: 1:0:  Type of mapping */
 #define PTE_TYPE_FAULT      (0 << 0)    /*   None */
@@ -226,7 +236,9 @@
 #define PTE_SMALL_AP_URW_SRW (0xff << 4)
 #define PTE_SMALL_TEX_MASK   0xfffff000  /* Bits: 31:12: Physical page */
 
-/* Tiny page -- 1Kb */
+#define PTE_SMALL_NPAGES     256         /* 256 Coarse PTE's per section */
+
+/* Fine/Tiny page -- 1Kb */
 
                                         /* Bits: 1:0:  Type of mapping */
                                         /* Bits: 3:2:  Bufferable/cacheable */
@@ -238,6 +250,8 @@
                                         /* Bits: 9:6:  Should be zero */
 #define PTE_TINY_TEX_MASK    0xfffffc00 /* Bits: 31:10: Physical page */
 
+#define PTE_TINY_NPAGES      1024        /* 1024 Tiny PTE's per section */
+
 /* Default MMU flags for memory and IO */
 
 #define MMU_MEMFLAGS \
@@ -253,9 +267,11 @@
 
 #define SECTION_SIZE          (1 << 20)   /* 1Mb */
 
-/* We place the page tables 16K below the beginning of .text.  The
- * following value is assume to be the (virtual) start address of
- * .text.
+/* CP15 register c2 contains a pointer to the base address of a paged table in
+ * physical memory.  Only bits 14-31 of the page table address is retained there;
+ * The full 30-bit address is formed by ORing in bits 2-13 or the virtual address
+ * (MVA).  As a consequence, the page table must be aligned to a 16Kb address in
+ * physical memory and could require up to 16Kb of memory.
  */
 
 #define PGTABLE_SIZE          0x00004000
diff --git a/nuttx/arch/arm/src/arm/pg_macros.h b/nuttx/arch/arm/src/arm/pg_macros.h
index bf79ba32a..8b05d5949 100644
--- a/nuttx/arch/arm/src/arm/pg_macros.h
+++ b/nuttx/arch/arm/src/arm/pg_macros.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/arm/pg_macros.S
+ * arch/arm/src/arm/pg_macros.h
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -41,6 +41,7 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
+#include <nuttx/page.h>
 
 #include "arm.h"
 
@@ -48,11 +49,42 @@
  * Definitions
  ****************************************************************************/
 
+/* Configuration ************************************************************/
+
+#ifdef CONFIG_PAGING
+  /* Sanity check -- we cannot be using a ROM page table and supporting on-
+   * demand paging.
+   */
+#  ifdef CONFIG_ARCH_ROMPGTABLE
+#    error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE"
+#  endif
+
+  /* Create some friendly definitions to handle some differences between
+   * small and tiny pages.
+   */
+
+#  if CONFIG_PAGING_PAGESIZE == 1024
+#    define PTE_NPAGES PTE_TINY_NPAGES
+#  elif CONFIG_PAGING_PAGESIZE == 4096
+#    define PTE_NPAGES PTE_SMALL_NPAGES
+#  else
+#    error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
+#  endif
+
+#define PT_SIZE (PTE_NPAGES * 4)
+#endif /* CONFIG_PAGING */
+
 /****************************************************************************
  * Assembly Macros
  ****************************************************************************/
 
-/* Write one L2 entry for a coarse page table entry.
+#ifdef __ASSEMBLY
+
+/****************************************************************************
+ * Name: wrpte_coarse
+ *
+ * Description:
+ *   Write one L2 entry for a coarse PTE.
  *
  * Inputs (unmodified):
  *   ctab  - Register containing the address of the coarse page table
@@ -61,9 +93,11 @@
  *   mmuflags - the MMU flags to use in the mapping
  *
  * Scratch registers (modified): tmp1, tmp2
- */
+ *
+ ****************************************************************************/
  
-	.macro	wrl2coarse, ctab, paddr, vaddr, mmuflags, tmp1, tmp2
+#ifdef CONFIG_PAGING
+	.macro	wrpte_coarse, ctab, paddr, vaddr, mmuflags, tmp1, tmp2
 	
 	/* Get tmp1 = (paddr | mmuflags), the value to write into the table */
 
@@ -79,8 +113,13 @@
 
 	str	\tmp1, [\ctab, \tmp2, lsr #10]
 	.endm
+#endif /* CONFIG_PAGING */
 
-/* Write one L1 entry for a coarse page table.
+/****************************************************************************
+ * Name: wrpmd_coarse
+ *
+ * Description:
+ *   Write one L1 entry for a coarse page table.
  *
  * Inputs (unmodified unless noted):
  *   paddr - Physical address of the section (modified)
@@ -88,9 +127,11 @@
  *   mmuflags - MMU flags to use in the section mapping
  *
  * Scratch registers (modified): tmp1, tmp2, tmp3
- */
+ *
+ ****************************************************************************/
 
-	.macro	wrl1coarse, paddr, vaddr, mmuflags, tmp1, tmp2
+#ifdef CONFIG_PAGING
+	.macro	wrpmd_coarse, paddr, vaddr, mmuflags, tmp1, tmp2
 	/* tmp1 = the base of the L1 page table */
 
    	ldr	\tmp1, =PGTABLE_BASE_VADDR
@@ -106,9 +147,14 @@
 	lsr	\tmp2, \vaddr, #20
 	str	\paddr, [\tmp1, \tmp2, lsl #2]
 	.endm
+#endif /* CONFIG_PAGING */
 
-/* Write one coarse L1 entry and all assocated L2 entries for a
- * coarse page table.
+/****************************************************************************
+ * Name: wr_coarse
+ *
+ * Description:
+ *   Write one coarse L1 entry and all assocated L2 entries for a coarse
+ *   page table.
  *
  * Inputs:
  *   offset - coarse page table offset (unmodified)
@@ -120,8 +166,11 @@
  *
  * On return, paddr and vaddr refer to the beginning of the
  * next section.
- */
-	.macro	wrcoarse, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PAGING
+	.macro	wr_coarse, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
 
 	/* tmp1 = address of L2 table; tmp2 = MMU flags */
 
@@ -132,14 +181,14 @@
 1:
 	/* Write that L2 entry into the coarse page table */
 
-	wrl2coarse \tmp1, \paddr, \vaddr, \tmp2, \tmp3, \tmp4
+	wrpte_coarse \tmp1, \paddr, \vaddr, \tmp2, \tmp3, \tmp4
 
 	/* Update the physical and virtual addresses that will
 	 * correspond to the next table entry.
 	 */
 
-	add	\paddr, \paddr, #4096
-	add	\vaddr, \vaddr, #4096
+	add	\paddr, \paddr, #CONFIG_PAGING_PAGESIZE
+	add	\vaddr, \vaddr, #CONFIG_PAGING_PAGESIZE
 2:
 	/* Check if all of the pages have been written.  If not, then
 	 * loop and write the next entry.
@@ -156,12 +205,17 @@
 	ldr	\tmp1, =PGTABLE_COARSE_BASE_PADDR
 	ldr	\tmp2, =MMU_L1_VECTORFLAGS
 	add	\tmp1, \offset, \tmp1
-	wrl1coarse \tmp1, \vaddr, \tmp2, \tmp3, \tmp4
+	wrpmd_coarse \tmp1, \vaddr, \tmp2, \tmp3, \tmp4
 	.endm
+#endif /* CONFIG_PAGING */
 
-/* Write several, contiguous coarse L1 page table entries (and all
- * associated L2 page table entries).  As many entries will be
- * written as many as needed to span npages.
+/****************************************************************************
+ * Name: wr_sections
+ *
+ * Description:
+ *   Write several, contiguous coarse L1 page table entries (and all
+ *   associated L2 page table entries).  As many entries will be written as
+ *   many as needed to span npages.
  *
  * Inputs:
  *   offset - coarse page table offset (modified)
@@ -170,28 +224,34 @@
  *   npages - Number of pages to write in the section
  *
  * Scratch registers (modified): tmp1, tmp2, tmp3, tmp4, tmp5
- */
+ *
+ ****************************************************************************/
 
-	.macro	wrsections, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
+#ifdef CONFIG_PAGING
+	.macro	wr_sections, offset, paddr, vaddr, npages, tmp1, tmp2, tmp3, tmp4
 	b	2f
 1:
-	/* Select the number of coarse, 4Kb pages to write in this section.
-	 * This number will be 256 unless there are fewer than 256 pages
-	 * remaining to be mapped.
+	/* Select the number of pages to write in this section. This number
+	 * will be 256 for coarse page tables or 1024 for fine/tiny page
+	 * tables (unless the npages argument indicates that there are fewer
+	 * than pages remaining to be mapped).
 	 */
 
-	cmp	\npages, #255		/* Check if <= 255 */
-	movls	\tmp1, \npages		/* YES.. tmp1 = npages */
-	movls	\npages, #0		/*       npages = 0 */
-	movhi	\tmp1, #256		/* NO..  tmp1 = 256 */
-	subhi	\npages, \npages, #256	/*       npages -= 256 */
+	cmp	\npages, #(PTE_NPAGES-1)	/* Check if npages < PTE_NPAGES */
+	movls	\tmp1, \npages			/* YES.. tmp1 = npages */
+	movls	\npages, #0			/*       npages = 0 */
+	movhi	\tmp1, #PTE_NPAGES		/* NO..  tmp1 = PTE_NPAGES */
+	subhi	\npages, \npages, #PTE_NPAGES	/*       npages -= PTE_NPAGES */
 
 	/* Write the L2 entries for this section */
 
-	wrcoarse \offset, \paddr, \vaddr, \tmp1, \tmp1, \tmp2, \tmp3, \tmp4
-	add	\offset, \offset, #1024
+	wr_coarse \offset, \paddr, \vaddr, \tmp1, \tmp1, \tmp2, \tmp3, \tmp4
+	add	\offset, \offset, #PT_SIZE
 2:
 	cmp	\npages, #0
 	bne	1b
 	.endm
+#endif /* CONFIG_PAGING */
+
+#endif /* __ASSEMBLY */
 #endif /* __ARCH_ARM_SRC_ARM_PG_MACROS_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_memorymap.h b/nuttx/arch/arm/src/dm320/dm320_memorymap.h
index 17afa183d..1f1e49d43 100644
--- a/nuttx/arch/arm/src/dm320/dm320_memorymap.h
+++ b/nuttx/arch/arm/src/dm320/dm320_memorymap.h
@@ -173,18 +173,16 @@
 #define PGTABLE_BASE_PADDR          DM320_SDRAM_PADDR
 #define PGTABLE_SDRAM_PADDR         PGTABLE_BASE_PADDR
 #define PGTABLE_COARSE_BASE_PADDR   (PGTABLE_BASE_PADDR+0x00000800)
-#define PGTABLE_COARSE_END_PADDR    (PGTABLE_BASE_PADDR+0x00003000)
-#define PTTABLE_PERIPHERALS_PADDR   (PGTABLE_BASE_PADDR+0x00003000)
+#define PGTABLE_COARSE_END_PADDR    (PGTABLE_BASE_PADDR+0x00004000)
 #define PGTABLE_END_PADDR           (PGTABLE_BASE_PADDR+0x00004000)
 
 #define PGTABLE_BASE_VADDR          DM320_SDRAM_VADDR
 #define PGTABLE_SDRAM_VADDR         PGTABLE_BASE_VADDR
 #define PGTABLE_COARSE_BASE_VADDR   (PGTABLE_BASE_VADDR+0x00000800)
-#define PGTABLE_COARSE_END_VADDR    (PGTABLE_BASE_VADDR+0x00003000)
-#define PTTABLE_PERIPHERALS_VADDR   (PGTABLE_BASE_VADDR+0x00003000)
+#define PGTABLE_COARSE_END_VADDR    (PGTABLE_BASE_VADDR+0x00004000)
 #define PGTABLE_END_VADDR           (PGTABLE_BASE_VADDR+0x00004000)
 
-#define PGTBALE_COARSE_TABLE_SIZE   (4*256)
+#define PGTABLE_COARSE_TABLE_SIZE   (4*256)
 #define PGTABLE_COARSE_ALLOC        (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR)
 #define PGTABLE_NCOARSE_TABLES      (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
 
diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h
index 23a88d2b5..d656b2f80 100644
--- a/nuttx/arch/arm/src/imx/imx_memorymap.h
+++ b/nuttx/arch/arm/src/imx/imx_memorymap.h
@@ -247,7 +247,7 @@
 #define PTTABLE_PERIPHERALS_VBASE (PGTABLE_VBASE+0x00003000)
 #define PGTABLE_VEND              (PGTABLE_VBASE+0x00004000)
 
-#define PGTBALE_COARSE_TABLE_SIZE (4*256)
+#define PGTABLE_COARSE_TABLE_SIZE (4*256)
 #define PGTABLE_COARSE_ALLOC      (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE)
 #define PGTABLE_NCOARSE_TABLES    (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
 
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h b/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h
index 4889f486a..39e218a46 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_memorymap.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lpc313x/chip.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,6 +48,7 @@
 
 /* LPC313X Physical (unmapped) Memory Map */
 
+#define LPC313X_FIRST_PSECTION         0x00000000 /* Beginning of the physical address space */
 #define LPC313X_SHADOWSPACE_PSECTION   0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
                                                   /* 0x00001000-0xff027fff: Reserved */
 #define LPC313X_INTSRAM_PSECTION       0x11028000 /*                        Internal SRAM 0+1 192Kb */
@@ -78,6 +79,12 @@
                                                   /* 0x60001000-0x6fffffff: Reserved */
 #define LPC313X_NAND_PSECTION          0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
                                                   /* 0x70000800-0xffffffff: Reserved */
+#ifdef CONDFIG_LPC313X_EXTNAND                    /* End of the physical address space */
+#  define LPC313X_LAST_PSECTION        (LPC313X_NAND_PSECTION + (1 << 20))
+#else
+#  define LPC313X_LAST_PSECTION        (LPC313X_INTC_PSECTION + (1 << 20))
+#endif
+
 /* APB0-4 Domain Offsets */
 
 #define LPC313X_APB0_EVNTRTR_OFFSET    0x00000000 /* Event Router */
@@ -204,6 +211,7 @@
  */
 
 #ifndef CONFIG_ARCH_ROMPGTABLE
+# defined LPC313X_FIRST_VSECTION       0x00000000 /* Beginning of the virtual address space */
 #  define LPC313X_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
 #  define LPC313X_INTSRAM_VSECTION     0x11028000 /*                        Internal SRAM 96Kb-192Kb */
 #    define LPC313X_INTSRAM0_VADDR     0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
@@ -224,6 +232,12 @@
 #  define LPC313X_EXTSDRAM0_VSECTION   0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
 #  define LPC313X_INTC_VSECTION        0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
 #  define LPC313X_NAND_VSECTION        0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
+#
+#  ifdef CONDFIG_LPC313X_EXTNAND                  /* End of the virtual address space */
+#    define LPC313X_LAST_VSECTION      (LPC313X_NAND_VSECTION + (1 << 20))
+#  else
+#    define LPC313X_LAST_VSECTION      (LPC313X_INTC_VSECTION + (1 << 20))
+#  endif
 #endif
 
 /* The boot logic will create a temporarily mapping based on where NuttX is
@@ -304,17 +318,17 @@
  * normal operation). We will reuse this memory for coarse page tables as follows:
  */
 
-#define PGTABLE_COARSE_BASE_PADDR   (PGTABLE_BASE_PADDR+0x00000800)
-#define PGTABLE_COARSE_END_PADDR    (PGTABLE_BASE_PADDR+0x00003000)
-#define PTTABLE_PERIPHERALS_PADDR   (PGTABLE_BASE_PADDR+0x00003000)
+#define PGTABLE_COARSE_POFFSET      ((LPC313X_LAST_PSECTION >> 20) << 2)
+#define PGTABLE_COARSE_BASE_PADDR   (PGTABLE_BASE_PADDR+PGTABLE_COARSE_POFFSET)
+#define PGTABLE_COARSE_END_PADDR    (PGTABLE_BASE_PADDR+0x00004000)
 #define PGTABLE_END_PADDR           (PGTABLE_BASE_PADDR+0x00004000)
 
-#define PGTABLE_COARSE_BASE_VADDR   (PGTABLE_BASE_VADDR+0x00000800)
-#define PGTABLE_COARSE_END_VADDR    (PGTABLE_BASE_VADDR+0x00003000)
-#define PTTABLE_PERIPHERALS_VADDR   (PGTABLE_BASE_VADDR+0x00003000)
+#define PGTABLE_COARSE_VOFFSET      ((LPC313X_LAST_VSECTION >>20) << 2)
+#define PGTABLE_COARSE_BASE_VADDR   (PGTABLE_BASE_VADDR+PGTABLE_COARSE_VOFFSET)
+#define PGTABLE_COARSE_END_VADDR    (PGTABLE_BASE_VADDR+0x00004000)
 #define PGTABLE_END_VADDR           (PGTABLE_BASE_VADDR+0x00004000)
 
-#define PGTBALE_COARSE_TABLE_SIZE   (4*256)
+#define PGTABLE_COARSE_TABLE_SIZE   (4*256)
 #define PGTABLE_COARSE_ALLOC        (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR)
 #define PGTABLE_NCOARSE_TABLES      (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)