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authorGregory Nutt <gnutt@nuttx.org>2013-04-16 18:00:59 -0600
committerGregory Nutt <gnutt@nuttx.org>2013-04-16 18:00:59 -0600
commit9255670a9d9fab07e941008aa9e9edbf5b460c0b (patch)
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parent82b1ed85155de4cac47551adb2363cc36b8806d0 (diff)
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Fix major misthink in Cortex-M0 port: The Cortex-M0 has no BASEPRI register. We have to revert to using the nasty PRIMASK register
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contributed by Alan Carvalho de Assis. NOTE: This is still
very much a work inprogress as of this initial commit
(2013-04-16).
+ * arm/arm/src/armv6-m and arch/arm/include/armv6-m: Ooops. Fix
+ a major screw-up: The Cortex-M0 has no BASEPRI register but
+ the current logic was using it to manage interrupts. Switch
+ to using the PRIMASK. This means that hardfaults will (again)
+ occur when SVC instructions are executed (2013-4-16).