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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-08-03 08:22:37 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-08-03 08:22:37 -0600 |
| commit | b74587a3f2161d1092ccf813bafe1246dbcf5365 (patch) | |
| tree | 5ef5533c147c7ca3c131bb26d7b50204e459edc5 /nuttx/ChangeLog | |
| parent | 711d0c577726b0cce1fa37d961fc3f192aa8e70d (diff) | |
| download | nuttx-b74587a3f2161d1092ccf813bafe1246dbcf5365.tar.gz nuttx-b74587a3f2161d1092ccf813bafe1246dbcf5365.tar.bz2 nuttx-b74587a3f2161d1092ccf813bafe1246dbcf5365.zip | |
Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts
Diffstat (limited to 'nuttx/ChangeLog')
| -rw-r--r-- | nuttx/ChangeLog | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 8dcf73971..15dab15c5 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5269,5 +5269,8 @@ After initialization, the page table entries are modified so that DRAM is fully cache-able (2018-8-2). * arch/arm/src/sama5/chip/sam_mpddrc.h: Correct typos in the - SAMA5 DDR controller register definitions (2013-9-2013). - + SAMA5 DDR controller register definitions (2013-8-2). + * arch/arm/src/sama5/sam_irq.c: Correct handling of spurious + interrupts (2013-8-3). + * arch/*/src/*/*_irq.c: Standardize configuration variables used + to enable interrupt controller debug output (2013-8-3). |