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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-16 16:32:19 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-02-16 16:32:19 +0000 |
| commit | b78eb3e4bbd9a44cb38e6cd5f7fdde4e22a183f4 (patch) | |
| tree | 82e3a9b70e21bda79f4a26bf36dd755dcb4160a9 /nuttx/arch/arm/src/armv6-m | |
| parent | 54c9fa75c9466f4676d12105dbf4026aeb92adb7 (diff) | |
| download | nuttx-b78eb3e4bbd9a44cb38e6cd5f7fdde4e22a183f4.tar.gz nuttx-b78eb3e4bbd9a44cb38e6cd5f7fdde4e22a183f4.tar.bz2 nuttx-b78eb3e4bbd9a44cb38e6cd5f7fdde4e22a183f4.zip | |
First cut at support for Cortex-M0
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5655 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/armv6-m')
27 files changed, 4480 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/armv6-m/Kconfig b/nuttx/arch/arm/src/armv6-m/Kconfig new file mode 100644 index 000000000..3dea706d4 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/Kconfig @@ -0,0 +1,59 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +comment "ARMV6M Configuration Options" + +choice + prompt "Toolchain Selection" + default ARMV6M_TOOLCHAIN_CODESOURCERYW if HOST_WINDOWS + default ARMV6M_TOOLCHAIN_GNU_EABI if !HOST_WINDOWS + +config ARMV6M_TOOLCHAIN_ATOLLIC + bool "Atollic Lite/Pro for Windows" + depends on HOST_WINDOWS + +config ARMV6M_TOOLCHAIN_BUILDROOT + bool "Buildroot (Cygwin or Linux)" + depends on !WINDOWS_NATIVE + +config ARMV6M_TOOLCHAIN_CODEREDL + bool "CodeRed for Linux" + depends on HOST_LINUX + +config ARMV6M_TOOLCHAIN_CODEREDW + bool "CodeRed for Windows" + depends on HOST_WINDOWS + +config ARMV6M_TOOLCHAIN_CODESOURCERYL + bool "CodeSourcery GNU toolchain under Linux" + depends on HOST_LINUX + +config ARMV6M_TOOLCHAIN_CODESOURCERYW + bool "CodeSourcery GNU toolchain under Windows" + depends on HOST_WINDOWS + +config ARMV6M_TOOLCHAIN_DEVKITARM + bool "devkitARM GNU toolchain" + depends on HOST_WINDOWS + +config ARMV6M_TOOLCHAIN_GNU_EABI + bool "Generic GNU EABI toolchain" + ---help--- + This option should work for any modern GNU toolchain (GCC 4.5 or newer) + configured for arm-none-eabi. + +config ARMV6M_TOOLCHAIN_RAISONANCE + bool "STMicro Raisonance for Windows" + depends on HOST_WINDOWS + +endchoice + +config ARMV6M_OABI_TOOLCHAIN + bool "OABI (vs EABI)" + default y + depends on ARMV6M_TOOLCHAIN_BUILDROOT + ---help--- + Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi- + diff --git a/nuttx/arch/arm/src/armv6-m/Toolchain.defs b/nuttx/arch/arm/src/armv6-m/Toolchain.defs new file mode 100644 index 000000000..064517014 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/Toolchain.defs @@ -0,0 +1,185 @@ +############################################################################ +# arch/arm/src/armv6-m/Toolchain.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Setup for the selected toolchain + +# +# Handle old-style chip-specific toolchain names in the absence of +# a new-style toolchain specification, force the selection of a single +# toolchain and allow the selected toolchain to be overridden by a +# command-line selection. +# + +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_ATOLLIC)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= ATOLLIC +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= BUILDROOT +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_CODEREDL)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= CODEREDL +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_CODEREDW)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= CODEREDW +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= CODESOURCERYL +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= CODESOURCERYW +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_DEVKITARM)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= DEVKITARM +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_GNU_EABI)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= GNU_EABI +endif +ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_RAISONANCE)),y) + CONFIG_ARMV6M_TOOLCHAIN ?= RAISONANCE +endif + +# +# Supported toolchains +# +# TODO - It's likely that all of these toolchains now support the +# CortexM0. Since they are all GCC-based, we could almost +# certainly simplify this further. +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCROSSDEV If required, an alternative prefix used when +# invoking ar and nm. +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + +# Atollic toolchain under Windows + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),ATOLLIC) + CROSSDEV ?= arm-atollic-eabi- + ARCROSSDEV ?= arm-atollic-eabi- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif + ARCHCPUFLAGS = -mcpu=cortex_m0 -mthumb -march=armv6e-m -mfloat-abi=soft +endif + +# NuttX buildroot under Linux or Cygwin + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),BUILDROOT) +ifeq ($(CONFIG_ARMV6M_OABI_TOOLCHAIN),y) + CROSSDEV ?= arm-nuttx-elf- + ARCROSSDEV ?= arm-nuttx-elf- + ARCHCPUFLAGS = -mtune=cortex-m0 -march=armv6-m -mfloat-abi=soft +else + CROSSDEV ?= arm-nuttx-eabi- + ARCROSSDEV ?= arm-nuttx-eabi- + ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft +endif +MAXOPTIMIZATION = -Os +endif + +# Code Red RedSuite under Linux + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODEREDL) + CROSSDEV ?= arm-none-eabi- + ARCROSSDEV ?= arm-none-eabi- + ARCHCPUFLAGS = -mcpu=cortex_m0 -mthumb -march=armv6-m -mfloat-abi=soft +endif + +# Code Red RedSuite under Windows + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODEREDW) + CROSSDEV ?= arm-none-eabi- + ARCROSSDEV ?= arm-none-eabi- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif + ARCHCPUFLAGS = -mcpu=cortex_m0 -mthumb -march=armv6e-m -mfloat-abi=soft +endif + +# CodeSourcery under Linux + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODESOURCERYL) + CROSSDEV ?= arm-none-eabi- + ARCROSSDEV ?= arm-none-eabi- + ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft + MAXOPTIMIZATION = -O2 +endif + +# CodeSourcery under Windows + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CODESOURCERYW) + CROSSDEV ?= arm-none-eabi- + ARCROSSDEV ?= arm-none-eabi- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif + ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft +endif + +# devkitARM under Windows + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),DEVKITARM) + CROSSDEV ?= arm-eabi- + ARCROSSDEV ?= arm-eabi- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif + ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft +endif + +# Generic GNU EABI toolchain on OS X, Linux or any typical Posix system + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABI) + CROSSDEV ?= arm-none-eabi- + ARCROSSDEV ?= arm-none-eabi- + MAXOPTIMIZATION = -O3 + ARCHCPUFLAGS = -mcpu=cortex_m0 -mthumb -march=armv6e-m -mfloat-abi=soft +endif + +# Raisonance RIDE7 under Windows + +ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),RAISONANCE) + CROSSDEV ?= arm-none-eabi- + ARCROSSDEV ?= arm-none-eabi- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif + ARCHCPUFLAGS = -mcpu=cortex-m0 -mthumb -mfloat-abi=soft +endif diff --git a/nuttx/arch/arm/src/armv6-m/exc_return.h b/nuttx/arch/arm/src/armv6-m/exc_return.h new file mode 100644 index 000000000..e779df505 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/exc_return.h @@ -0,0 +1,120 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/exc_return.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV6_M_EXC_RETURN_H +#define __ARCH_ARM_SRC_ARMV6_M_EXC_RETURN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The processor saves an EXC_RETURN value to the LR on exception entry. The + * exception mechanism relies on this value to detect when the processor has + * completed an exception handler. + * + * Bits [31:28] of an EXC_RETURN value are always 1. When the processor loads a + * value matching this pattern to the PC it detects that the operation is a not + * a normal branch operation and instead, that the exception is complete. + * Therefore, it starts the exception return sequence. + * + * Bits[4:0] of the EXC_RETURN value indicate the required return stack and eventual + * processor mode. The remaining bits of the EXC_RETURN value should be set to 1. + */ + +/* EXC_RETURN_BASE: Bits that are always set in an EXC_RETURN value. */ + +#define EXC_RETURN_BASE 0xffffffe1 + +/* EXC_RETURN_PROCESS_STACK: The exception saved (and will restore) the hardware + * context using the process stack pointer (if not set, the context was saved + * using the main stack pointer) + */ + +#define EXC_RETURN_PROCESS_BITNO (2) +#define EXC_RETURN_PROCESS_STACK (1 << EXC_RETURN_PROCESS_BITNO) + +/* EXC_RETURN_THREAD_MODE: The exception will return to thread mode (if not set, + * return stays in handler mode) + */ + +#define EXC_RETURN_THREAD_BITNO (3) +#define EXC_RETURN_THREAD_MODE (1 << EXC_RETURN_THREAD_BITNO) + +/* EXC_RETURN_STD_CONTEXT: The state saved on the stack does not include the + * volatile FP registers and FPSCR. If this bit is clear, the state does include + * these registers. + */ + +#define EXC_RETURN_STD_BITNO (4) +#define EXC_RETURN_STD_CONTEXT (1 << EXC_RETURN_STD_BITNO) + +/* EXC_RETURN_HANDLER: Return to handler mode. Exception return gets state from + * the main stack. Execution uses MSP after return. + */ + +#define EXC_RETURN_HANDLER 0xfffffff1 + +/* EXC_RETURN_PRIVTHR: Return to privileged thread mode. Exception return gets + * state from the main stack. Execution uses MSP after return. + */ + +#define EXC_RETURN_PRIVTHR 0xfffffff9 + +/* EXC_RETURN_UNPRIVTHR: Return to unprivileged thread mode. Exception return gets + * state from the process stack. Execution uses PSP after return. + */ + +#define EXC_RETURN_UNPRIVTHR 0xfffffffd + +/* In the kernel build is not selected, then all threads run in privileged thread + * mode. + */ + +#ifdef CONFIG_NUTTX_KERNEL +# define EXC_RETURN 0xfffffff9 +#endif + +/************************Th************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_ARMV6_M_EXC_RETURN_H */ + diff --git a/nuttx/arch/arm/src/armv6-m/nvic.h b/nuttx/arch/arm/src/armv6-m/nvic.h new file mode 100644 index 000000000..5d21c4666 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/nvic.h @@ -0,0 +1,372 @@ +/**************************************************************************************************** + * arch/arm/src/armv6-m/nvic.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_ARMV6_M_NVIC_H +#define __ARCH_ARM_SRC_COMMON_ARMV6_M_NVIC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include <nuttx/config.h> + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Base addresses ***********************************************************************************/ + +#define ARMV6M_SYSCON1_BASE 0xe000e008 /* 0xe000e008-0xe000e00f System Control Block */ + /* 0xe000e010-0xe000e01f Reserved */ +#define ARMV6M_SYSTICK_BASE 0xe000e010 /* 0xe000e010-0xe000e01f SysTick system timer */ +#define ARMV6M_NVIC1_BASE 0xe000e100 /* 0xe000e100-0xe000e4ef Nested Vectored Interrupt Controller */ +#define ARMV6M_SYSCON2_BASE 0xe000ed00 /* 0xe000ed00-0xe000ed3f System Control Block */ +#define ARMV6M_NVIC2_BASE 0xe000ef00 /* 0xe000ef00-0xe000ef03 Nested Vectored Interrupt Controller */ + +/* NVIC register offsets ****************************************************************************/ +/* NVIC register offsets (all relative to ARMV6M_NVIC1_BASE) */ + +#define ARMV6M_NVIC_ISER_OFFSET 0x0100 /* Interrupt set-enable register */ +#define ARMV6M_NVIC_ICER_OFFSET 0x0180 /* Interrupt clear-enable register */ +#define ARMV6M_NVIC_ISPR_OFFSET 0x0200 /* Interrupt set-pending register */ +#define ARMV6M_NVIC_ICPR_OFFSET 0x0280 /* Interrupt clear-pending register */ +#define ARMV6M_NVIC_IPR_OFFSET(n) (0x0400 + ((n) << 2)) +# define ARMV6M_NVIC_IPR0_OFFSET 0x0400 /* Interrupt priority register 0 */ +# define ARMV6M_NVIC_IPR1_OFFSET 0x0404 /* Interrupt priority register 1 */ +# define ARMV6M_NVIC_IPR2_OFFSET 0x0408 /* Interrupt priority register 2 */ +# define ARMV6M_NVIC_IPR3_OFFSET 0x040c /* Interrupt priority register 3 */ +# define ARMV6M_NVIC_IPR4_OFFSET 0x0410 /* Interrupt priority register 4 */ +# define ARMV6M_NVIC_IPR5_OFFSET 0x0414 /* Interrupt priority register 5 */ +# define ARMV6M_NVIC_IPR6_OFFSET 0x0418 /* Interrupt priority register 6 */ +# define ARMV6M_NVIC_IPR7_OFFSET 0x041c /* Interrupt priority register 7 */ + +/* System control register offsets (all relative to ARMV6M_SYSCON2_BASE) */ + +#define ARMV6M_SYSCON_CPUID_OFFSET 0x0000 /* CPUID Register */ +#define ARMV6M_SYSCON_ICSR_OFFSET 0x0004 /* Interrupt control and state register */ +#define ARMV6M_SYSCON_AIRCR_OFFSET 0x000c /* Application interrupt and reset control register */ +#define ARMV6M_SYSCON_SCR_OFFSET 0x0010 /* System control register */ +#define ARMV6M_SYSCON_CCR_OFFSET 0x0014 /* Configuration and control register */ +#define ARMV6M_SYSCON_SHPR2_OFFSET 0x001c /* System handler priority register 2 */ +#define ARMV6M_SYSCON_SHPR3_OFFSET 0x0020 /* System handler priority register 3 */ + +/* SYSTICK register offsets (all relatvive to ARMV6M_SYSTICK_BASE) */ + +#define ARMV6M_SYSTICK_CSR_OFFSET 0x0000 /* SysTick control and status register */ +#define ARMV6M_SYSTICK_RVR_OFFSET 0x0004 /* SysTick reload value register */ +#define ARMV6M_SYSTICK_CVR_OFFSET 0x0008 /* SysTick current value register */ +#define ARMV6M_SYSTICK_CALIB_OFFSET 0x000c /* SysTick calibration value register */ + +/* Register addresses *******************************************************************************/ +/* NVIC register addresses */ + +#define ARMV6M_NVIC_ISER (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_ISER_OFFSET) +#define ARMV6M_NVIC_ICER (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_ICER_OFFSET) +#define ARMV6M_NVIC_ISPR (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_ISPR_OFFSET) +#define ARMV6M_NVIC_ICPR (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_ICPR_OFFSET) +#define ARMV6M_NVIC_IPR(n) (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR_OFFSET(n)) +# define ARMV6M_NVIC_IPR0 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR0_OFFSET) +# define ARMV6M_NVIC_IPR1 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR1_OFFSET) +# define ARMV6M_NVIC_IPR2 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR2_OFFSET) +# define ARMV6M_NVIC_IPR3 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR3_OFFSET) +# define ARMV6M_NVIC_IPR4 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR4_OFFSET) +# define ARMV6M_NVIC_IPR5 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR5_OFFSET) +# define ARMV6M_NVIC_IPR6 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR6_OFFSET) +# define ARMV6M_NVIC_IPR7 (ARMV6M_NVIC1_BASE+ARMV6M_NVIC_IPR7_OFFSET) + +/* System control register addresses */ + +#define ARMV6M_SYSCON_CPUID (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_CPUID_OFFSET) +#define ARMV6M_SYSCON_ICSR (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_ICSR_OFFSET) +#define ARMV6M_SYSCON_AIRCR (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_AIRCR_OFFSET) +#define ARMV6M_SYSCON_SCR (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_SCR_OFFSET) +#define ARMV6M_SYSCON_CCR (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_CCR_OFFSET) +#define ARMV6M_SYSCON_SHPR2 (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_SHPR2_OFFSET) +#define ARMV6M_SYSCON_SHPR3 (ARMV6M_SYSCON2_BASE+ARMV6M_SYSCON_SHPR3_OFFSET) + +/* SYSTICK register addresses */ + +#define ARMV6M_SYSTICK_CSR (ARMV6M_SYSTICK_BASE+ARMV6M_SYSTICK_CSR_OFFSET) +#define ARMV6M_SYSTICK_RVR (ARMV6M_SYSTICK_BASE+ARMV6M_SYSTICK_RVR_OFFSET) +#define ARMV6M_SYSTICK_CVR (ARMV6M_SYSTICK_BASE+ARMV6M_SYSTICK_CVR_OFFSET) +#define ARMV6M_SYSTICK_CALIB (ARMV6M_SYSTICK_BASE+ARMV6M_SYSTICK_CALIB_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* Interrupt set-enable register */ + +#define NVIC_ISER(n) (1 << (n)) /* n=0..31 */ + +/* Interrupt clear-enable register */ + +#define NVIC_ICER(n) (1 << (n)) /* n=0..31 */ + +/* Interrupt set-pending register */ + +#define NVIC_ISPR(n) (1 << (n)) /* n=0..31 */ + +/* Interrupt clear-pending register */ + +#define NVIC_ICPR(n) (1 << (n)) /* n=0..31 */ + +/* Interrupt priority registers 0-7 */ + +#define NVIC_IPR_0_SHIFT (0) /* Bits 0-7: PRI_(4n) */ +#define NVIC_IPR_0_MASK (0xff << NVIC_IPR_0_SHIFT) +# define NVIC_IPR_0(p) ((p) << NVIC_IPR_0_SHIFT) +#define NVIC_IPR_1_SHIFT (8) /* Bits 8-15: PRI_(4n+1) */ +#define NVIC_IPR_1_MASK (0xff << NVIC_IPR_1_SHIFT) +# define NVIC_IPR_1(p) ((p) << NVIC_IPR_1_SHIFT) +#define NVIC_IPR_2_SHIFT (16) /* Bits 16-23: PRI_(4n+2) */ +#define NVIC_IPR_2_MASK (0xff << NVIC_IPR_2_SHIFT) +# define NVIC_IPR_2(p) ((p) << NVIC_IPR_2_SHIFT) +#define NVIC_IPR_3_SHIFT (24) /* Bits 24-31: PRI_(4n+3) */ +#define NVIC_IPR_3_MASK (0xff << NVIC_IPR_3_SHIFT) +# define NVIC_IPR_3(p) ((p) << NVIC_IPR_3_SHIFT) + +#define NVIC_IPR0_0_SHIFT (0) /* Bits 0-7: PRI_0 */ +#define NVIC_IPR0_0_MASK (0xff << NVIC_IPR0_0_SHIFT) +# define NVIC_IPR0_0(p) ((p) << NVIC_IPR0_0_SHIFT) +#define NVIC_IPR0_1_SHIFT (8) /* Bits 8-15: PRI_1 */ +#define NVIC_IPR0_1_MASK (0xff << NVIC_IPR0_1_SHIFT) +# define NVIC_IPR0_1(p) ((p) << NVIC_IPR0_1_SHIFT) +#define NVIC_IPR0_2_SHIFT (16) /* Bits 16-23: PRI_2 */ +#define NVIC_IPR0_2_MASK (0xff << NVIC_IPR0_2_SHIFT) +# define NVIC_IPR0_2(p) ((p) << NVIC_IPR0_2_SHIFT) +#define NVIC_IPR0_3_SHIFT (24) /* Bits 24-31: PRI_3 */ +#define NVIC_IPR0_3_MASK (0xff << NVIC_IPR0_3_SHIFT) +# define NVIC_IPR0_3(p) ((p) << NVIC_IPR0_3_SHIFT) + +#define NVIC_IPR1_4_SHIFT (0) /* Bits 0-7: PRI_4 */ +#define NVIC_IPR1_4_MASK (0xff << NVIC_IPR1_4_SHIFT) +# define NVIC_IPR1_4(p) ((p) << NVIC_IPR1_4_SHIFT) +#define NVIC_IPR1_5_SHIFT (8) /* Bits 8-15: PRI_5 */ +#define NVIC_IPR1_5_MASK (0xff << NVIC_IPR1_5_SHIFT) +# define NVIC_IPR1_5(p) ((p) << NVIC_IPR1_5_SHIFT) +#define NVIC_IPR1_6_SHIFT (16) /* Bits 16-23: PRI_6 */ +#define NVIC_IPR1_6_MASK (0xff << NVIC_IPR1_6_SHIFT) +# define NVIC_IPR1_6(p) ((p) << NVIC_IPR1_6_SHIFT) +#define NVIC_IPR1_7_SHIFT (24) /* Bits 24-31: PRI_7 */ +#define NVIC_IPR1_7_MASK (0xff << NVIC_IPR1_7_SHIFT) +# define NVIC_IPR1_7(p) ((p) << NVIC_IPR1_7_SHIFT) + +#define NVIC_IPR2_8_SHIFT (0) /* Bits 0-7: PRI_8 */ +#define NVIC_IPR2_8_MASK (0xff << NVIC_IPR2_8_SHIFT) +# define NVIC_IPR2_8(p) ((p) << NVIC_IPR2_8_SHIFT) +#define NVIC_IPR2_9_SHIFT (8) /* Bits 8-15: PRI_9 */ +#define NVIC_IPR2_9_MASK (0xff << NVIC_IPR2_9_SHIFT) +# define NVIC_IPR2_9(p) ((p) << NVIC_IPR2_9_SHIFT) +#define NVIC_IPR2_10_SHIFT (16) /* Bits 16-23: PRI_10 */ +#define NVIC_IPR2_10_MASK (0xff << NVIC_IPR2_10_SHIFT) +# define NVIC_IPR2_10(p) ((p) << NVIC_IPR2_10_SHIFT) +#define NVIC_IPR2_11_SHIFT (24) /* Bits 24-31: PRI_11 */ +#define NVIC_IPR2_11_MASK (0xff << NVIC_IPR2_11_SHIFT) +# define NVIC_IPR2_11(p) ((p) << NVIC_IPR2_11_SHIFT) + +#define NVIC_IPR3_12_SHIFT (0) /* Bits 0-7: PRI_12 */ +#define NVIC_IPR3_12_MASK (0xff << NVIC_IPR3_12_SHIFT) +# define NVIC_IPR3_12(p) ((p) << NVIC_IPR3_12_SHIFT) +#define NVIC_IPR3_13_SHIFT (8) /* Bits 8-15: PRI_13 */ +#define NVIC_IPR3_13_MASK (0xff << NVIC_IPR3_13_SHIFT) +# define NVIC_IPR3_13(p) ((p) << NVIC_IPR3_13_SHIFT) +#define NVIC_IPR3_14_SHIFT (16) /* Bits 16-23: PRI_14 */ +#define NVIC_IPR3_14_MASK (0xff << NVIC_IPR3_14_SHIFT) +# define NVIC_IPR3_14(p) ((p) << NVIC_IPR3_14_SHIFT) +#define NVIC_IPR3_15_SHIFT (24) /* Bits 24-31: PRI_15 */ +#define NVIC_IPR3_15_MASK (0xff << NVIC_IPR3_15_SHIFT) +# define NVIC_IPR3_15(p) ((p) << NVIC_IPR3_15_SHIFT) + +#define NVIC_IPR4_16_SHIFT (0) /* Bits 0-7: PRI_16 */ +#define NVIC_IPR4_16_MASK (0xff << NVIC_IPR4_16_SHIFT) +# define NVIC_IPR4_16(p) ((p) << NVIC_IPR4_16_SHIFT) +#define NVIC_IPR4_17_SHIFT (8) /* Bits 8-15: PRI_17 */ +#define NVIC_IPR4_17_MASK (0xff << NVIC_IPR4_17_SHIFT) +# define NVIC_IPR4_17(p) ((p) << NVIC_IPR4_17_SHIFT) +#define NVIC_IPR4_18_SHIFT (16) /* Bits 16-23: PRI_18 */ +#define NVIC_IPR4_18_MASK (0xff << NVIC_IPR4_18_SHIFT) +# define NVIC_IPR4_18(p) ((p) << NVIC_IPR4_18_SHIFT) +#define NVIC_IPR4_19_SHIFT (24) /* Bits 24-31: PRI_19 */ +#define NVIC_IPR4_19_MASK (0xff << NVIC_IPR4_19_SHIFT) +# define NVIC_IPR4_19(p) ((p) << NVIC_IPR4_19_SHIFT) + +#define NVIC_IPR5_20_SHIFT (0) /* Bits 0-7: PRI_20 */ +#define NVIC_IPR5_20_MASK (0xff << NVIC_IPR5_20_SHIFT) +# define NVIC_IPR5_20(p) ((p) << NVIC_IPR5_20_SHIFT) +#define NVIC_IPR5_21_SHIFT (8) /* Bits 8-15: PRI_21 */ +#define NVIC_IPR5_21_MASK (0xff << NVIC_IPR5_21_SHIFT) +# define NVIC_IPR5_21(p) ((p) << NVIC_IPR5_21_SHIFT) +#define NVIC_IPR5_22_SHIFT (16) /* Bits 16-23: PRI_22 */ +#define NVIC_IPR5_22_MASK (0xff << NVIC_IPR5_22_SHIFT) +# define NVIC_IPR5_22(p) ((p) << NVIC_IPR5_22_SHIFT) +#define NVIC_IPR5_23_SHIFT (24) /* Bits 24-31: PRI_23 */ +#define NVIC_IPR5_23_MASK (0xff << NVIC_IPR5_23_SHIFT) +# define NVIC_IPR5_23(p) ((p) << NVIC_IPR5_23_SHIFT) + +#define NVIC_IPR6_24_SHIFT (0) /* Bits 0-7: PRI_24 */ +#define NVIC_IPR6_24_MASK (0xff << NVIC_IPR6_24_SHIFT) +# define NVIC_IPR6_24(p) ((p) << NVIC_IPR6_24_SHIFT) +#define NVIC_IPR6_25_SHIFT (8) /* Bits 8-15: PRI_25 */ +#define NVIC_IPR6_25_MASK (0xff << NVIC_IPR6_25_SHIFT) +# define NVIC_IPR6_25(p) ((p) << NVIC_IPR6_25_SHIFT) +#define NVIC_IPR6_26_SHIFT (16) /* Bits 16-23: PRI_26 */ +#define NVIC_IPR6_26_MASK (0xff << NVIC_IPR6_26_SHIFT) +# define NVIC_IPR6_26(p) ((p) << NVIC_IPR6_26_SHIFT) +#define NVIC_IPR6_27_SHIFT (24) /* Bits 24-31: PRI_27 */ +#define NVIC_IPR6_27_MASK (0xff << NVIC_IPR6_27_SHIFT) +# define NVIC_IPR6_27(p) ((p) << NVIC_IPR6_27_SHIFT) + +#define NVIC_IPR7_28_SHIFT (0) /* Bits 0-7: PRI_28 */ +#define NVIC_IPR7_28_MASK (0xff << NVIC_IPR7_28_SHIFT) +# define NVIC_IPR7_28(p) ((p) << NVIC_IPR7_28_SHIFT) +#define NVIC_IPR7_29_SHIFT (8) /* Bits 8-15: PRI_29 */ +#define NVIC_IPR7_29_MASK (0xff << NVIC_IPR7_29_SHIFT) +# define NVIC_IPR7_29(p) ((p) << NVIC_IPR7_29_SHIFT) +#define NVIC_IPR7_30_SHIFT (16) /* Bits 16-23: PRI_30 */ +#define NVIC_IPR7_30_MASK (0xff << NVIC_IPR7_30_SHIFT) +# define NVIC_IPR7_30(p) ((p) << NVIC_IPR7_30_SHIFT) +#define NVIC_IPR7_31_SHIFT (24) /* Bits 24-31: PRI_31 */ +#define NVIC_IPR7_31_MASK (0xff << NVIC_IPR7_31_SHIFT) +# define NVIC_IPR7_31(p) ((p) << NVIC_IPR7_31_SHIFT) + +/* System control register addresses */ + +/* CPUID Register */ + +#define SYSCON_CPUID_REVISION_SHIFT (0) /* Bits 0-3: Revision number */ +#define SYSCON_CPUID_REVISION_MASK (15 << SYSCON_CPUID_REVISION_SHIFT) +#define SYSCON_CPUID_PARTNO_SHIFT (4) /* Bits 4-15: Part number of the processor */ +#define SYSCON_CPUID_PARTNO_MASK (0x0fff << SYSCON_CPUID_PARTNO_SHIFT) +# define SYSCON_CPUID_PARTNO_CORTEXM0 (0x0c20 << SYSCON_CPUID_PARTNO_SHIFT) +#define SYSCON_CPUID_CONSTANT_SHIFT (16) /* Bits 16-19: Constant that defines the architecture + * of the processor */ +#define SYSCON_CPUID_CONSTANT_MASK (15 << SYSCON_CPUID_CONSTANT_SHIFT) +# define SYSCON_CPUID_CONSTANT_ARMV6M (12 << SYSCON_CPUID_PARTNO_SHIFT) +#define SYSCON_CPUID_VARIANT_SHIFT (20) /* Bits 20-23: Variant number, the r value in the + * rnpn product revision identifier */ +#define SYSCON_CPUID_VARIANT_MASK (15 << SYSCON_CPUID_VARIANT_SHIFT) +#define SYSCON_CPUID_IMPLEMENTER_SHIFT (24) /* Bits 24-31: Implementer code */ +#define SYSCON_CPUID_IMPLEMENTER_MASK (0xff << SYSCON_CPUID_IMPLEMENTER_SHIFT) +# define SYSCON_CPUID_IMPLEMENTER_ARM (0x41 << SYSCON_CPUID_IMPLEMENTER_SHIFT) + +/* Interrupt control and state register */ + +#define SYSCON_ICSR_VECTACTIVE_SHIFT (0) /* Bits 0-5: Contains the active exception number */ +#define SYSCON_ICSR_VECTACTIVE_MASK (63 << SYSCON_ICSR_VECTACTIVE_SHIFT) +#define SYSCON_ICSR_VECTPENDING_SHIFT (12) /* Bits 12-17: Indicates the exception number of + * the highest priority pending enabled + * exception */ +#define SYSCON_ICSR_VECTPENDING_MASK (63 << SYSCON_ICSR_VECTPENDING_SHIFT) +#define SYSCON_ICSR_ISRPENDING (1 << 22) /* Bit 22: Interrupt pending flag, excluding NMI + * and Faults */ +#define SYSCON_ICSR_PENDSTCLR (1 << 25) /* Bit 25: SysTick exception clear-pending bit */ +#define SYSCON_ICSR_PENDSTSET (1 << 26) /* Bit 26: SysTick exception set-pending bit */ +#define SYSCON_ICSR_PENDSVCLR (1 << 27) /* Bit 27: PendSV clear-pending bit */ +#define SYSCON_ICSR_PENDSVSET (1 << 28) /* Bit 28: PendSV set-pending bit */ +#define SYSCON_ICSR_NMIPENDSET (1 << 31) /* Bit 31: NMI set-pending bit */ + +/* Application interrupt and reset control register */ + +#define SYSCON_AIRCR_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */ +#define SYSCON_AIRCR_SYSRESETREQ (1 << 2) /* Bit 2: System reset request */ +#define SYSCON_AIRCR_ENDIANESS (1 << 15) /* Bit 15: Data endianness implemented */ +#define SYSCON_AIRCR_VECTKEY_SHIFT (16) /* Bits 16-31: Register key */ +#define SYSCON_AIRCR_VECTKEY_MASK (0xffff << SYSCON_AIRCR_VECTKEY_SHIFT) +# define SYSCON_AIRCR_VECTKEY(n) ((n) << SYSCON_AIRCR_VECTKEY_SHIFT) + +/* System control register */ + +#define SYSCON_SCR_SLEEPONEXIT (1 << 1) /* Bit 1: Sleep-on-exit when returning from handler + * to thread mode */ +#define SYSCON_SCR_SLEEPDEEP (1 << 2) /* Bit 2: Use deep sleep as the low power mode */ +#define SYSCON_SCR_SEVONPEND (1 << 4) /* Bit 4: Send event on pending bit */ + +/* Configuration and control register */ + +#define SYSCON_CCR_UNALIGN_TRP (1 << 3) /* Bit 3: Unaligned accesses generate a hardfault */ +#define SYSCON_CCR_STKALIGN (1 << 9) /* Bit 9: 8-byte stack alignment on exception entry */ + +/* System handler priority register 2 */ + +#define SYSCON_SHPR2_PRI_11_SHIFT (24) /* Bits 24-31: Priority of system handler 11, + * SVCall */ +#define SYSCON_SHPR2_PRI_11_MASK (0xff << SYSCON_SHPR2_PRI_11_SHIFT) + +/* System handler priority register 3 */ + +#define SYSCON_SHPR3_PRI_14_SHIFT (16) /* Bits 16-23: Priority of system handler 14, + * PendSV */ +#define SYSCON_SHPR3_PRI_14_MASK (0xff << SYSCON_SHPR3_PRI_14_SHIFT) +#define SYSCON_SHPR3_PRI_15_SHIFT (24) /* Bits 24-31: Priority of system handler 15, + * SysTick exception */ +#define SYSCON_SHPR3_PRI_15_MASK (0xff << SYSCON_SHPR3_PRI_15_SHIFT) + +/* SYSTICK register addresses */ + +/* SysTick control and status register */ + +#define SYSTICK_CSR_ENABLE (1 << 0) /* Bit 0: Enables the counter */ +#define SYSTICK_CSR_TICKINT (1 << 1) /* Bit 1: Enables SysTick exception request */ +#define SYSTICK_CSR_CLKSOURCE (1 << 2) /* Bit 2: Selects the SysTick timer clock source */ +#define SYSTICK_CSR_COUNTFLAG (1 << 16) /* Bit 16: Returns 1 if timer counted to 0 since + * the last read of this register */ + +/* SysTick reload value register */ + +#define SYSTICK_RVR_MASK (0x0fffffff) /* Bits 0-23 */ + +/* SysTick current value register */ + +#define SYSTICK_CVR_MASK (0x0fffffff) /* Bits 0-23 */ + +/* SysTick calibration value register */ + +#define SYSTICK_CALIB_TENMS_SHIFT (0) /* Bits 0-23: Reload value for 10ms (100Hz) timing */ +#define SYSTICK_CALIB_TENMS_MASK (0x0fffffff << SYSTICK_CALIB_TENMS_SHIFT) +#define SYSTICK_CALIB_SKEW (1 << 30) /* Bit 30: TENMS value is exact */ +#define SYSTICK_CALIB_NOREF (1 << 31) /* Bit 31: Device provides a reference clock */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_ARMV6_M_NVIC_H */ diff --git a/nuttx/arch/arm/src/armv6-m/psr.h b/nuttx/arch/arm/src/armv6-m/psr.h new file mode 100644 index 000000000..eeb541a00 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/psr.h @@ -0,0 +1,77 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/psr.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_ARMV6_M_PSR_H +#define __ARCH_ARM_SRC_COMMON_ARMV6_M_PSR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Application Program Status Register (APSR) */ + +#define ARMV6M_APSR_V (1 << 28) /* Bit 28: Overflow flag */ +#define ARMV6M_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */ +#define ARMV6M_APSR_Z (1 << 30) /* Bit 30: Zero flag */ +#define ARMV6M_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */ + +/* Interrupt Program Status Register (IPSR) */ + +#define ARMV6M_IPSR_ISR_SHIFT 0 /* Bits 5-0: ISR number */ +#define ARMV6M_IPSR_ISR_MASK (31 << ARMV6M_IPSR_ISR_SHIFT) + +/* Execution PSR Register (EPSR) */ + +#define ARMV6M_EPSR_T (1 << 24) /* Bit 24: T-bit */ + +/* Save xPSR bits */ + +#define ARMV6M_XPSR_ISR_SHIFT ARMV6M_IPSR_ISR_SHIFT +#define ARMV6M_XPSR_ISR_MASK ARMV6M_IPSR_ISR_MASK +#define ARMV6M_XPSR_T ARMV6M_EPSR_T +#define ARMV6M_XPSR_V ARMV6M_APSR_V +#define ARMV6M_XPSR_C ARMV6M_APSR_C +#define ARMV6M_XPSR_Z ARMV6M_APSR_Z +#define ARMV6M_XPSR_N ARMV6M_APSR_N + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_ARMV6_M_PSR_H */ diff --git a/nuttx/arch/arm/src/armv6-m/svcall.h b/nuttx/arch/arm/src/armv6-m/svcall.h new file mode 100644 index 000000000..38c672ff6 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/svcall.h @@ -0,0 +1,94 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/svcall.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_SVCALL_H +#define __ARCH_ARM_SRC_COMMON_CORTEXM_SVCALL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#ifdef CONFIG_NUTTX_KERNEL +# include <syscall.h> +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* This logic uses three system calls {0,1,2} for context switching. The first three + * syscall values must be reserved. + */ + +#ifdef CONFIG_NUTTX_KERNEL +# ifndef CONFIG_SYS_RESERVED +# error "CONFIG_SYS_RESERVED must be defined to the value 3" +# elif CONFIG_SYS_RESERVED != 3 +# error "CONFIG_SYS_RESERVED must have the value 3" +# endif +#endif + +/* Cortex M0 system calls ***********************************************************/ + +/* SYS call 0: + * + * int up_saveusercontext(uint32_t *saveregs); + */ + +#define SYS_save_context (0) + +/* SYS call 1: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) + +/* SYS call 2: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + */ + +#define SYS_switch_context (2) + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM_SVCALL_H */ + diff --git a/nuttx/arch/arm/src/armv6-m/up_assert.c b/nuttx/arch/arm/src/armv6-m/up_assert.c new file mode 100644 index 000000000..dd3eed1e3 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_assert.c @@ -0,0 +1,335 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_assert.c + * + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdlib.h> +#include <assert.h> +#include <debug.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Output debug info if stack dump is selected -- even if + * debug is not selected. + */ + +#ifdef CONFIG_ARCH_STACKDUMP +# undef lldbg +# define lldbg lowsyslog +#endif + +/* The following is just intended to keep some ugliness out of the mainline + * code. We are going to print the task name if: + * + * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name + * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used) + * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used + */ + +#undef CONFIG_PRINT_TASKNAME +#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP)) +# define CONFIG_PRINT_TASKNAME 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getsp + ****************************************************************************/ + +/* I don't know if the builtin to get SP is enabled */ + +static inline uint32_t up_getsp(void) +{ + uint32_t sp; + __asm__ + ( + "\tmov %0, sp\n\t" + : "=r"(sp) + ); + return sp; +} + +/**************************************************************************** + * Name: up_stackdump + ****************************************************************************/ + +#ifdef CONFIG_ARCH_STACKDUMP +static void up_stackdump(uint32_t sp, uint32_t stack_base) +{ + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t*)stack; + lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} +#else +# define up_stackdump() +#endif + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +#ifdef CONFIG_ARCH_STACKDUMP +static inline void up_registerdump(void) +{ + /* Are user registers available from interrupt processing? */ + + if (current_regs) + { + /* Yes.. dump the interrupt registers */ + + lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + current_regs[REG_R0], current_regs[REG_R1], + current_regs[REG_R2], current_regs[REG_R3], + current_regs[REG_R4], current_regs[REG_R5], + current_regs[REG_R6], current_regs[REG_R7]); + lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + current_regs[REG_R8], current_regs[REG_R9], + current_regs[REG_R10], current_regs[REG_R11], + current_regs[REG_R12], current_regs[REG_R13], + current_regs[REG_R14], current_regs[REG_R15]); + lldbg("xPSR: %08x BASEPRI: %08x\n", + current_regs[REG_XPSR], current_regs[REG_BASEPRI]); + } +} +#else +# define up_registerdump() +#endif + +/**************************************************************************** + * Name: up_dumpstate + ****************************************************************************/ + +#ifdef CONFIG_ARCH_STACKDUMP +static void up_dumpstate(void) +{ + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + uint32_t sp = up_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) + { + ustackbase = g_heapbase - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + lldbg("sp: %08x\n", sp); + lldbg("IRQ stack:\n"); + lldbg(" base: %08x\n", istackbase); + lldbg(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + up_stackdump(sp, istackbase); + } + + /* Extract the user stack pointer if we are in an interrupt handler. + * If we are not in an interrupt handler. Then sp is the user stack + * pointer (and the above range check should have failed). + */ + + if (current_regs) + { + sp = current_regs[REG_R13]; + lldbg("sp: %08x\n", sp); + } + + lldbg("User stack:\n"); + lldbg(" base: %08x\n", ustackbase); + lldbg(" size: %08x\n", ustacksize); + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp <= ustackbase && sp > ustackbase - ustacksize) + { + up_stackdump(sp, ustackbase); + } +#else + lldbg("sp: %08x\n", sp); + lldbg("stack base: %08x\n", ustackbase); + lldbg("stack size: %08x\n", ustacksize); + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { + lldbg("ERROR: Stack pointer is not within allocated stack\n"); + } + else + { + up_stackdump(sp, ustackbase); + } +#endif + + /* Then dump the registers (if available) */ + + up_registerdump(); +} +#else +# define up_dumpstate() +#endif + +/**************************************************************************** + * Name: _up_assert + ****************************************************************************/ + +static void _up_assert(int errorcode) noreturn_function; +static void _up_assert(int errorcode) +{ + /* Are we in an interrupt handler or the idle task? */ + + if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0) + { + (void)irqsave(); + for(;;) + { +#ifdef CONFIG_ARCH_LEDS + up_ledon(LED_PANIC); + up_mdelay(250); + up_ledoff(LED_PANIC); + up_mdelay(250); +#endif + } + } + else + { + exit(errorcode); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_assert + ****************************************************************************/ + +void up_assert(const uint8_t *filename, int lineno) +{ +#ifdef CONFIG_PRINT_TASKNAME + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; +#endif + + up_ledon(LED_ASSERTION); +#ifdef CONFIG_PRINT_TASKNAME + lldbg("Assertion failed at file:%s line: %d task: %s\n", + filename, lineno, rtcb->name); +#else + lldbg("Assertion failed at file:%s line: %d\n", + filename, lineno); +#endif + up_dumpstate(); + _up_assert(EXIT_FAILURE); +} + +/**************************************************************************** + * Name: up_assert_code + ****************************************************************************/ + +void up_assert_code(const uint8_t *filename, int lineno, int errorcode) +{ +#ifdef CONFIG_PRINT_TASKNAME + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; +#endif + + up_ledon(LED_ASSERTION); +#ifdef CONFIG_PRINT_TASKNAME + lldbg("Assertion failed at file:%s line: %d task: %s error code: %d\n", + filename, lineno, rtcb->name, errorcode); +#else + lldbg("Assertion failed at file:%s line: %d error code: %d\n", + filename, lineno, errorcode); +#endif + up_dumpstate(); + _up_assert(errorcode); +} diff --git a/nuttx/arch/arm/src/armv6-m/up_blocktask.c b/nuttx/arch/arm/src/armv6-m/up_blocktask.c new file mode 100644 index 000000000..a332cbefd --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_blocktask.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_blocktask.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> +#include <sched.h> +#include <debug.h> + +#include <nuttx/arch.h> + +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_block_task + * + * Description: + * The currently executing task at the head of the ready to run list must + * be stopped. Save its context and move it to the inactive list specified + * by task_state. + * + * Inputs: + * tcb: Refers to a task in the ready-to-run list (normally the task at + * the head of the list). It most be stopped, its context saved and + * moved into one of the waiting task lists. It it was the task at the + * head of the ready-to-run list, then a context to the new ready to run + * task must be performed. + * task_state: Specifies which waiting task list should be hold the + * blocked task TCB. + * + ****************************************************************************/ + +void up_block_task(struct tcb_s *tcb, tstate_t task_state) +{ + /* Verify that the context switch can be performed */ + + if ((tcb->task_state < FIRST_READY_TO_RUN_STATE) || + (tcb->task_state > LAST_READY_TO_RUN_STATE)) + { + PANIC(OSERR_BADBLOCKSTATE); + } + else + { + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + bool switch_needed; + + /* Remove the tcb task from the ready-to-run list. If we + * are blocking the task at the head of the task list (the + * most likely case), then a context switch to the next + * ready-to-run task is needed. In this case, it should + * also be true that rtcb == tcb. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Add the task to the specified blocked task list */ + + sched_addblocked(tcb, (tstate_t)task_state); + + /* If there are any pending tasks, then add them to the g_readytorun + * task list now + */ + + if (g_pendingtasks.head) + { + switch_needed |= sched_mergepending(); + } + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* Are we in an interrupt handler? */ + + if (current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the g_readytorun task list. + */ + + rtcb = (struct tcb_s*)g_readytorun.head; + + /* Then switch contexts */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } + } +} diff --git a/nuttx/arch/arm/src/armv6-m/up_copystate.c b/nuttx/arch/arm/src/armv6-m/up_copystate.c new file mode 100644 index 000000000..b7736fb8f --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_copystate.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_copystate.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> + +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void up_copystate(uint32_t *dest, uint32_t *src) +{ + int i; + + /* In the Cortex-M3 model, the state is copied from the stack to the TCB, + * but only a reference is passed to get the state from the TCB. So the + * following check avoids copying the TCB save area onto itself: + */ + + if (src != dest) + { + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } + } +} + diff --git a/nuttx/arch/arm/src/armv6-m/up_doirq.c b/nuttx/arch/arm/src/armv6-m/up_doirq.c new file mode 100644 index 000000000..7dec21152 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_doirq.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_doirq.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <assert.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t *up_doirq(int irq, uint32_t *regs) +{ + up_ledon(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(OSERR_ERREXCEPTION); +#else + uint32_t *savestate; + + /* Nested interrupts are not supported in this implementation. If you want + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). + */ + + /* Current regs non-zero indicates that we are processing an interrupt; + * current_regs is also used to manage interrupt level context switches. + */ + + savestate = (uint32_t*)current_regs; + current_regs = regs; + + /* Mask and acknowledge the interrupt */ + + up_maskack_irq(irq); + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + + /* If a context switch occurred while processing the interrupt then + * current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t*)current_regs; + + /* Restore the previous value of current_regs. NULL would indicate that + * we are no longer in an interrupt handler. It will be non-NULL if we + * are returning from a nested interrupt. + */ + + current_regs = savestate; + + /* Unmask the last interrupt (global interrupts are still disabled) */ + + up_enable_irq(irq); +#endif + up_ledoff(LED_INIRQ); + return regs; +} diff --git a/nuttx/arch/arm/src/armv6-m/up_elf.c b/nuttx/arch/arm/src/armv6-m/up_elf.c new file mode 100644 index 000000000..367c93515 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_elf.c @@ -0,0 +1,450 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_elf.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdlib.h> +#include <elf32.h> +#include <errno.h> +#include <debug.h> + +#include <arch/elf.h> +#include <nuttx/arch.h> +#include <nuttx/binfmt/elf.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arch_checkarch + * + * Description: + * Given the ELF header in 'hdr', verify that the ELF file is appropriate + * for the current, configured architecture. Every architecture that uses + * the ELF loader must provide this function. + * + * Input Parameters: + * hdr - The ELF header read from the ELF file. + * + * Returned Value: + * True if the architecture supports this ELF file. + * + ****************************************************************************/ + +bool arch_checkarch(FAR const Elf32_Ehdr *ehdr) +{ + /* Make sure it's an ARM executable */ + + if (ehdr->e_machine != EM_ARM) + { + bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine); + return -ENOEXEC; + } + + /* Make sure that 32-bit objects are supported */ + + if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) + { + bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + return -ENOEXEC; + } + + /* Verify endian-ness */ + +#ifdef CONFIG_ENDIAN_BIG + if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB) +#else + if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) +#endif + { + bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + return -ENOEXEC; + } + + /* TODO: Check ABI here. */ + return OK; +} + +/**************************************************************************** + * Name: arch_relocate and arch_relocateadd + * + * Description: + * Perform on architecture-specific ELF relocation. Every architecture + * that uses the ELF loader must provide this function. + * + * Input Parameters: + * rel - The relocation type + * sym - The ELF symbol structure containing the fully resolved value. + * addr - The address that requires the relocation. + * + * Returned Value: + * Zero (OK) if the relocation was successful. Otherwise, a negated errno + * value indicating the cause of the relocation failure. + * + ****************************************************************************/ + +int arch_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, + uintptr_t addr) +{ + int32_t offset; + uint32_t upper_insn; + uint32_t lower_insn; + + switch (ELF32_R_TYPE(rel->r_info)) + { + case R_ARM_NONE: + { + /* No relocation */ + } + break; + + case R_ARM_PC24: + case R_ARM_CALL: + case R_ARM_JUMP24: + { + bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr), + sym, (long)sym->st_value); + + offset = (*(uint32_t*)addr & 0x00ffffff) << 2; + if (offset & 0x02000000) + { + offset -= 0x04000000; + } + + offset += sym->st_value - addr; + if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) + { + bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + ELF32_R_TYPE(rel->r_info), offset); + + return -EINVAL; + } + + offset >>= 2; + + *(uint32_t*)addr &= 0xff000000; + *(uint32_t*)addr |= offset & 0x00ffffff; + } + break; + + case R_ARM_ABS32: + case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */ + { + bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + (long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value); + + *(uint32_t*)addr += sym->st_value; + } + break; + + case R_ARM_THM_CALL: + case R_ARM_THM_JUMP24: + { + uint32_t S; + uint32_t J1; + uint32_t J2; + + /* Thumb BL and B.W instructions. Encoding: + * + * upper_insn: + * + * 1 1 1 1 1 1 + * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +----------+---+-------------------------------+--------------+ + * |1 1 1 |OP1| OP2 | | 32-Bit Instructions + * +----------+---+--+-----+----------------------+--------------+ + * |1 1 1 | 1 0| S | imm10 | BL Instruction + * +----------+------+-----+-------------------------------------+ + * + * lower_insn: + * + * 1 1 1 1 1 1 + * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +---+---------------------------------------------------------+ + * |OP | | 32-Bit Instructions + * +---+--+---+---+---+------------------------------------------+ + * |1 1 |J1 | 1 |J2 | imm11 | BL Instruction + * +------+---+---+---+------------------------------------------+ + * + * The branch target is encoded in these bits: + * + * S = upper_insn[10] + * imm10 = upper_insn[0:9] + * imm11 = lower_insn[0:10] + * J1 = lower_insn[13] + * J2 = lower_insn[11] + */ + + upper_insn = (uint32_t)(*(uint16_t*)addr); + lower_insn = (uint32_t)(*(uint16_t*)(addr + 2)); + + bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn, + sym, (long)sym->st_value); + + /* Extract the 25-bit offset from the 32-bit instruction: + * + * offset[24] = S + * offset[23] = ~(J1 ^ S) + * offset[22] = ~(J2 ^ S)] + * offset[12:21] = imm10 + * offset[1:11] = imm11 + * offset[0] = 0 + */ + + S = (upper_insn >> 10) & 1; + J1 = (lower_insn >> 13) & 1; + J2 = (lower_insn >> 11) & 1; + + offset = (S << 24) | /* S - > offset[24] */ + ((~(J1 ^ S) & 1) << 23) | /* J1 -> offset[23] */ + ((~(J2 ^ S) & 1) << 22) | /* J2 -> offset[22] */ + ((upper_insn & 0x03ff) << 12) | /* imm10 -> offset[12:21] */ + ((lower_insn & 0x07ff) << 1); /* imm11 -> offset[1:11] */ + /* 0 -> offset[0] */ + + /* Sign extend */ + + if (offset & 0x01000000) + { + offset -= 0x02000000; + } + + /* And perform the relocation */ + + bvdbg(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n", + S, J1, J2, (long)offset, offset + sym->st_value - addr); + + offset += sym->st_value - addr; + + /* Is this a function symbol? If so, then the branch target must be + * an odd Thumb address + */ + + if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0) + { + bdbg(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n", + ELF32_R_TYPE(rel->r_info), offset); + + return -EINVAL; + } + + /* Check the range of the offset */ + + if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000) + { + bdbg(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n", + ELF32_R_TYPE(rel->r_info), offset); + + return -EINVAL; + } + + /* Now, reconstruct the 32-bit instruction using the new, relocated + * branch target. + */ + + S = (offset >> 24) & 1; + J1 = S ^ (~(offset >> 23) & 1); + J2 = S ^ (~(offset >> 22) & 1); + + upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff)); + *(uint16_t*)addr = (uint16_t)upper_insn; + + lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff)); + *(uint16_t*)(addr + 2) = (uint16_t)lower_insn; + + bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n", + S, J1, J2, (int)upper_insn, (int)lower_insn); + } + break; + + case R_ARM_V4BX: + { + bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n", + (long)addr, (long)(*(uint32_t*)addr)); + + /* Preserve only Rm and the condition code */ + + *(uint32_t*)addr &= 0xf000000f; + + /* Change instruction to 'mov pc, Rm' */ + + *(uint32_t*)addr |= 0x01a0f000; + } + break; + + case R_ARM_PREL31: + { + bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + (long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value); + + offset = *(uint32_t*)addr + sym->st_value - addr; + *(uint32_t*)addr = offset & 0x7fffffff; + } + break; + + case R_ARM_MOVW_ABS_NC: + case R_ARM_MOVT_ABS: + { + bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr), + sym, (long)sym->st_value); + + offset = *(uint32_t*)addr; + offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); + offset = (offset ^ 0x8000) - 0x8000; + + offset += sym->st_value; + if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS) + { + offset >>= 16; + } + + *(uint32_t*)addr &= 0xfff0f000; + *(uint32_t*)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff); + } + break; + + case R_ARM_THM_MOVW_ABS_NC: + case R_ARM_THM_MOVT_ABS: + { + /* Thumb BL and B.W instructions. Encoding: + * + * upper_insn: + * + * 1 1 1 1 1 1 + * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +----------+---+-------------------------------+--------------+ + * |1 1 1 |OP1| OP2 | | 32-Bit Instructions + * +----------+---+--+-----+----------------------+--------------+ + * |1 1 1 | 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction + * +----------+------+-----+----------------------+--------------+ + * + * lower_insn: + * + * 1 1 1 1 1 1 + * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +---+---------------------------------------------------------+ + * |OP | | 32-Bit Instructions + * +---+----------+--------------+-------------------------------+ + * |0 | imm3 | Rd | imm8 | MOVT Instruction + * +---+----------+--------------+-------------------------------+ + * + * The 16-bit immediate value is encoded in these bits: + * + * i = imm16[11] = upper_insn[10] + * imm4 = imm16[12:15] = upper_insn[3:0] + * imm3 = imm16[8:10] = lower_insn[14:12] + * imm8 = imm16[0:7] = lower_insn[7:0] + */ + + upper_insn = (uint32_t)(*(uint16_t*)addr); + lower_insn = (uint32_t)(*(uint16_t*)(addr + 2)); + + bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n", + ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn, + sym, (long)sym->st_value); + + /* Extract the 16-bit offset from the 32-bit instruction */ + + offset = ((upper_insn & 0x000f) << 12) | /* imm4 -> imm16[8:10] */ + ((upper_insn & 0x0400) << 1) | /* i -> imm16[11] */ + ((lower_insn & 0x7000) >> 4) | /* imm3 -> imm16[8:10] */ + (lower_insn & 0x00ff); /* imm8 -> imm16[0:7] */ + + /* Sign extend */ + + offset = (offset ^ 0x8000) - 0x8000; + + /* And perform the relocation */ + + bvdbg(" offset=%08lx branch target=%08lx\n", + (long)offset, offset + sym->st_value); + + offset += sym->st_value; + + /* Update the immediate value in the instruction. For MOVW we want the bottom + * 16-bits; for MOVT we want the top 16-bits. + */ + + if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) + { + offset >>= 16; + } + + upper_insn = ((upper_insn & 0xfbf0) | ((offset & 0xf000) >> 12) | ((offset & 0x0800) >> 1)); + *(uint16_t*)addr = (uint16_t)upper_insn; + + lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff)); + *(uint16_t*)(addr + 2) = (uint16_t)lower_insn; + + bvdbg(" insn [%04x %04x]\n", + (int)upper_insn, (int)lower_insn); + } + break; + + default: + bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + return -EINVAL; + } + + return OK; +} + +int arch_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym, + uintptr_t addr) +{ + bdbg("RELA relocation not supported\n"); + return -ENOSYS; +} + diff --git a/nuttx/arch/arm/src/armv6-m/up_exception.S b/nuttx/arch/arm/src/armv6-m/up_exception.S new file mode 100644 index 000000000..ef399b5e7 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_exception.S @@ -0,0 +1,227 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/up_exception.S + * + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2012 Michael Smith. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <arch/irq.h> +#include "exc_return.h" + +#include "chip.h" + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .globl exception_common + + .cpu cortex-m0 + .file "up_exception.S" + +/************************************************************************************ + * .text + ************************************************************************************/ + +/* Common exception handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: + * + * REG_XPSR + * REG_R15 + * REG_R14 + * REG_R12 + * REG_R3 + * REG_R2 + * REG_R1 + * MSP->REG_R0 + * + * And + * IPSR contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP + */ + + .text + .align 2 + .code 16 + .thumb_func + .type exception_common, function +exception_common: + + mrs r0, ipsr /* R0=exception number */ + + /* Complete the context save */ + + /* The EXC_RETURN value tells us whether the context is on the MSP or PSP */ + + mov r0, r14 /* Copy high register to low register */ + lsl r1, r0, #(31 - EXC_RETURN_PROCESS_BITNO) /* Move to bit 31 */ + bmi 1f /* Test bit 31 */ + mrs r1, msp /* R1=The main stack pointer */ + b 2f + +1: + mrs r1, psp /* R1=The process stack pointer */ + +2: + mov r2, #XCPTCONTEXT_SIZE /* R2=Size of context array */ + sub r0, r1, r2 /* R0=Beginning of context array on the stack */ + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ + /* (ignoring the xPSR[9] alignment bit) */ + mrs r3, basepri /* R3=Current BASEPRI setting */ + + stmia r0!, {r2-r7} /* Save the SP, BASEPRI, and R4-R7 */ + mov r2, r8 /* Copy high registers to low */ + mov r3, r9 + mov r4, r10 + mov r5, r11 + mov r6, r14 + stmia r0!, {r2-r6} /* Save the high registers r8-r11 and r14 */ + + /* Disable interrupts, select the stack to use for interrupt handling + * and call up_doirq to handle the interrupt + */ + + cpsid i /* Disable further interrupts */ + + /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt + * stack pointer. The way that this is done here prohibits nested interrupts! + * Otherwise, we will use the stack that was current when the interrupt was taken. + */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + ldr sp, =g_intstackbase + push {r1} /* Save the MSP on the interrupt stack */ + bl up_doirq /* R0=IRQ, R1=register save area on stack */ + pop {r1} /* Recover R1=main stack pointer */ +#else + msr msp, r1 /* We are using the main stack pointer */ + bl up_doirq /* R0=IRQ, R1=register save area on stack */ + mrs r1, msp /* Recover R1=main stack pointer */ +#endif + + /* On return from up_doirq, r0 will hold a pointer to register context + * array to use for the interrupt return. If that return value is the same + * as current stack pointer, then things are relatively easy. + */ + + cmp r0, r1 /* Context switch? */ + beq 3f /* Branch if no context switch */ + + /* We are returning with a pending context switch. This case is different + * because in this case, the register save structure does not lie on the + * stack but, rather within a TCB structure. We'll have to copy some + * values to the stack. + */ + + /* Copy the hardware-saved context to the new stack */ + + mov r2, #SW_XCPT_SIZE /* R2=Size of sofware-saved portion of the context array */ + add r1, r0, r2 /* R1=Address of HW save area in reg array */ + ldr r2, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ + sub r2, #HW_XCPT_SIZE /* R1=Address of HW save area on stack */ + ldmia r1!, {r4-r7} /* Fetch four registers from the HW save area */ + stmia r2!, {r4-r7} /* Copy four registers to the return stack */ + ldmia r1!, {r4-r7} /* Fetch four registers from the HW save area */ + stmia r2!, {r4-r7} /* Copy four registers to the return stack */ + + /* Restore the register contents */ + + mov r1, r0 + +3: + /* We are returning with no context switch. We simply need to "unwind" + * the same stack frame that we created at entry. + */ + + mov r2, #(4*REG_R8) /* R2=Offset to R8 storage */ + sub r0, r1, r2 /* R0=Address of R8 storage */ + ldmia r0!, {r2-r6} /* Recover R8-R11 and R14 */ + mov r8, r2 /* Move to position in high registers */ + mov r9, r3 + mov r10, r4 + mov r11, r5 + mov r14, r6 + ldmia r1!, {r2-r7} /* Recover R4-R7 + 2 temp values */ + + /* The EXC_RETURN value tells us whether the context is on the MSP or PSP */ + + mov r0, r14 /* Copy high register to low register */ + lsl r1, r0, #(31 - EXC_RETURN_PROCESS_BITNO) /* Move to bit 31 */ + bmi 5f /* Test bit 31 */ + mrs r1, msp /* R1=The main stack pointer */ + b 6f + +5: + mrs r1, psp /* R1=The process stack pointer */ + +6: + /* Restore the interrupt state */ + + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ + + /* Always return with R14 containing the special value that will: (1) + * return to thread mode, and (2) select the correct stack. + */ + + bx r14 /* And return */ + + .size exception_common, .-exception_common + +/************************************************************************************ + * Name: up_interruptstack/g_intstackbase + * + * Description: + * Shouldn't happen + * + ************************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + .bss + .global g_intstackbase + .align 4 +up_interruptstack: + .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) +g_intstackbase: + .size up_interruptstack, .-up_interruptstack +#endif + + .end + diff --git a/nuttx/arch/arm/src/armv6-m/up_fullcontextrestore.S b/nuttx/arch/arm/src/armv6-m/up_fullcontextrestore.S new file mode 100644 index 000000000..d09afb020 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_fullcontextrestore.S @@ -0,0 +1,96 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/up_fullcontextrestore.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/irq.h> + +#include "nvic.h" +#include "svcall.h" + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .cpu cortex-m0 + .file "up_fullcontextrestore.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_fullcontextrestore + * + * Description: + * Restore the current thread context. Full prototype is: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * + * Return: + * None + * + ************************************************************************************/ + + .align 2 + .code 16 + .thumb_func + .globl up_fullcontextrestore + .type up_fullcontextrestore, function +up_fullcontextrestore: + + /* Perform the System call with R0=1 and R1=regs */ + + mov r1, r0 /* R1: regs */ + mov r0, #SYS_restore_context /* R0: restore context */ + svc 0 /* Force synchronous SVCall (or Hard Fault) */ + + /* This call should not return */ + + bx lr /* Unnecessary ... will not return */ + .size up_fullcontextrestore, .-up_fullcontextrestore + .end + diff --git a/nuttx/arch/arm/src/armv6-m/up_hardfault.c b/nuttx/arch/arm/src/armv6-m/up_hardfault.c new file mode 100644 index 000000000..48eecb947 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_hardfault.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_hardfault.c + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <debug.h> + +#include <arch/irq.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "nvic.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_HARDFAULT +# define hfdbg(format, arg...) lldbg(format, ##arg) +#else +# define hfdbg(x...) +#endif + +#define INSN_SVC0 0xdf00 /* insn: svc 0 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_hardfault + * + * Description: + * This is Hard Fault exception handler. It also catches SVC call + * exceptions that are performed in bad contexts. + * + ****************************************************************************/ + +int up_hardfault(int irq, FAR void *context) +{ +#if defined(CONFIG_DEBUG_HARDFAULT) + uint32_t *regs = (uint32_t*)context; +#endif + + /* Dump some hard fault info */ + + hfdbg("\nHard Fault:\n"); + hfdbg(" IRQ: %d regs: %p\n", irq, regs); + hfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x\n", + getbasepri(), getprimask(), getipsr()); + hfdbg(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n", + getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS), + getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR), + getreg32(NVIC_AFAULTS)); + hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + hfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n", + current_regs[REG_XPSR], current_regs[REG_BASEPRI]); + + (void)irqsave(); + lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); + PANIC(OSERR_UNEXPECTEDISR); + return OK; +} diff --git a/nuttx/arch/arm/src/armv6-m/up_initialstate.c b/nuttx/arch/arm/src/armv6-m/up_initialstate.c new file mode 100644 index 000000000..6b2c98e67 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_initialstate.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_initialstate.c + * + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <string.h> + +#include <nuttx/arch.h> + +#include "up_internal.h" +#include "up_arch.h" + +#include "psr.h" +#include "exc_return.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the intial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Save the initial stack pointer */ + + xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* Save the task entry point (stripping off the thumb bit) */ + + xcp->regs[REG_PC] = (uint32_t)tcb->start & ~1; + + /* Specify thumb mode */ + + xcp->regs[REG_XPSR] = ARMV6M_XPSR_T; + + /* If this task is running PIC, then set the PIC base register to the + * address of the allocated D-Space region. + */ + +#ifdef CONFIG_PIC + if (tcb->dspace != NULL) + { + /* Set the PIC base register (probably R10) to the address of the + * alloacated D-Space region. + */ + + xcp->regs[REG_PIC] = (uint32_t)tcb->dspace->region; + } + + /* Make certain that bit 0 is set in the main entry address. This + * is only an issue when NXFLAT is enabled. NXFLAT doesn't know + * anything about thumb; the addresses that NXFLAT sets are based + * on file header info and won't have bit 0 set. + */ + +#ifdef CONFIG_NXFLAT + tcb->entry.main = (main_t)((uint32_t)tcb->entry.main | 1); +#endif +#endif /* CONFIG_PIC */ + + /* Set privileged- or unprivileged-mode, depending on how NuttX is + * configured and what kind of thread is being started. + * + * If the kernel build is not selected, then all threads run in + * privileged thread mode. + */ + + xcp->regs[REG_EXC_RETURN] = EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE; + xcp->regs[REG_EXC_RETURN] |= EXC_RETURN_STD_CONTEXT; + +#ifdef CONFIG_NUTTX_KERNEL + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) + { + /* It is a normal task or a pthread. Set user mode */ + + xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PROCESS_STACK; + } +#endif /* CONFIG_NUTTX_KERNEL */ + + /* Enable or disable interrupts, based on user configuration */ + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + xcp->regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#endif /* CONFIG_SUPPRESS_INTERRUPTS */ +} diff --git a/nuttx/arch/arm/src/armv6-m/up_memfault.c b/nuttx/arch/arm/src/armv6-m/up_memfault.c new file mode 100644 index 000000000..d04a9acf8 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_memfault.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_memfault.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <assert.h> +#include <debug.h> + +#include <arch/irq.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "nvic.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef DEBUG_MEMFAULTS /* Define to debug memory management faults */ + +#ifdef DEBUG_MEMFAULTS +# define mfdbg(format, arg...) lldbg(format, ##arg) +#else +# define mfdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_memfault + * + * Description: + * This is Memory Management Fault exception handler. Normally we get here + * when the Cortex M3 MPU is enabled and an MPU fault is detected. However, + * I understand that there are other error conditions that can also generate + * memory management faults. + * + ****************************************************************************/ + +int up_memfault(int irq, FAR void *context) +{ + /* Dump some memory management fault info */ + + (void)irqsave(); + lldbg("PANIC!!! Memory Management Fault:\n"); + mfdbg(" IRQ: %d context: %p\n", irq, regs); + lldbg(" CFAULTS: %08x MMFAR: %08x\n", + getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR)); + mfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + mfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + mfdbg(" PSR=%08x\n", regs[REG_XPSR]); + + PANIC(OSERR_UNEXPECTEDISR); + return OK; +} diff --git a/nuttx/arch/arm/src/armv6-m/up_releasepending.c b/nuttx/arch/arm/src/armv6-m/up_releasepending.c new file mode 100644 index 000000000..08c87ae47 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_releasepending.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_releasepending.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sched.h> +#include <debug.h> +#include <nuttx/arch.h> + +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_pending + * + * Description: + * Release and ready-to-run tasks that have + * collected in the pending task list. This can call a + * context switch if a new task is placed at the head of + * the ready to run list. + * + ****************************************************************************/ + +void up_release_pending(void) +{ + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + + slldbg("From TCB=%p\n", rtcb); + + /* Merge the g_pendingtasks list into the g_readytorun task list */ + + /* sched_lock(); */ + if (sched_mergepending()) + { + /* The currently active task has changed! We will need to switch + * contexts. First check if we are operating in interrupt context. + */ + + if (current_regs) + { + /* Yes, then we have to do things differently. Just copy the + * current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the g_readytorun task list. + */ + + rtcb = (struct tcb_s*)g_readytorun.head; + slldbg("New Active Task TCB=%p\n", rtcb); + + /* Then switch contexts */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c b/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c new file mode 100644 index 000000000..bbe43e8c2 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_reprioritizertr.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_reprioritizertr.c + * + * Copyright (C) 2007-2009, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <sched.h> +#include <debug.h> +#include <nuttx/arch.h> + +#include "os_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_reprioritize_rtr + * + * Description: + * Called when the priority of a running or + * ready-to-run task changes and the reprioritization will + * cause a context switch. Two cases: + * + * 1) The priority of the currently running task drops and the next + * task in the ready to run list has priority. + * 2) An idle, ready to run task's priority has been raised above the + * the priority of the current, running task and it now has the + * priority. + * + * Inputs: + * tcb: The TCB of the task that has been reprioritized + * priority: The new task priority + * + ****************************************************************************/ + +void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) +{ + /* Verify that the caller is sane */ + + if (tcb->task_state < FIRST_READY_TO_RUN_STATE || + tcb->task_state > LAST_READY_TO_RUN_STATE +#if SCHED_PRIORITY_MIN > 0 + || priority < SCHED_PRIORITY_MIN +#endif +#if SCHED_PRIORITY_MAX < UINT8_MAX + || priority > SCHED_PRIORITY_MAX +#endif + ) + { + PANIC(OSERR_BADREPRIORITIZESTATE); + } + else + { + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + bool switch_needed; + + slldbg("TCB=%p PRI=%d\n", tcb, priority); + + /* Remove the tcb task from the ready-to-run list. + * sched_removereadytorun will return true if we just removed the head + * of the ready to run list. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Setup up the new task priority */ + + tcb->sched_priority = (uint8_t)priority; + + /* Return the task to the ready-to-run task list. sched_addreadytorun + * will return true if the task was added to the head of ready-to-run + * list. We will need to perform a context switch only if the + * EXCLUSIVE or of the two calls is non-zero (i.e., one and only one + * the calls changes the head of the ready-to-run list). + */ + + switch_needed ^= sched_addreadytorun(tcb); + + /* Now, perform the context switch if one is needed (i.e. if the head + * of the ready-to-run list is no longer the same). + */ + + if (switch_needed) + { + /* If we are going to do a context switch, then now is the right + * time to add any pending tasks back into the ready-to-run list. + * task list now + */ + + if (g_pendingtasks.head) + { + sched_mergepending(); + } + + /* Are we in an interrupt handler? */ + + if (current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the g_readytorun task list. + */ + + rtcb = (struct tcb_s*)g_readytorun.head; + slldbg("New Active Task TCB=%p\n", rtcb); + + /* Then switch contexts */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } + } +} diff --git a/nuttx/arch/arm/src/armv6-m/up_saveusercontext.S b/nuttx/arch/arm/src/armv6-m/up_saveusercontext.S new file mode 100644 index 000000000..7bc14e4c4 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_saveusercontext.S @@ -0,0 +1,106 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/up_saveusercontext.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/irq.h> + +#include "nvic.h" +#include "svcall.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .cpu cortex-m0 + .file "up_saveusercontext.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_saveusercontext + * + * Description: + * Save the current thread context. Full prototype is: + * + * int up_saveusercontext(uint32_t *saveregs); + * + * Return: + * 0: Normal return + * 1: Context switch return + * + ************************************************************************************/ + + .text + .align 2 + .code 16 + .thumb_func + .globl up_saveusercontext + .type up_saveusercontext, function +up_saveusercontext: + + /* Perform the System call with R0=0 and R1=regs */ + + mov r1, r0 /* R1: regs */ + mov r0, #SYS_save_context /* R0: save context (also return value) */ + svc 0 /* Force synchronous SVCall (or Hard Fault) */ + + /* There are two return conditions. On the first return, R0 (the + * return value will be zero. On the second return we need to + * force R0 to be 1. + */ + + mov r3, #(4*REG_R0) /* R3=Offset to R0 storage */ + add r2, r1, r3 /* R2=Address of R0 storage */ + mov r3, #1 /* R3=Return value of one */ + str r3, [r2, #0] /* Save return value */ + bx lr /* "normal" return with r0=0 or + * context switch with r0=1 */ + .size up_saveusercontext, .-up_saveusercontext + .end + diff --git a/nuttx/arch/arm/src/armv6-m/up_schedulesigaction.c b/nuttx/arch/arm/src/armv6-m/up_schedulesigaction.c new file mode 100644 index 000000000..4ebb0ac37 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_schedulesigaction.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_schedulesigaction.c + * + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <sched.h> +#include <debug.h> + +#include <nuttx/arch.h> + +#include "psr.h" +#include "os_internal.h" +#include "up_internal.h" +#include "up_arch.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'igdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + /* Refuse to handle nested signal actions */ + + sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + if (!tcb->xcp.sigdeliver) + { + irqstate_t flags; + + /* Make sure that interrupts are disabled */ + + flags = irqsave(); + + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + sdbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs); + + if (tcb == (struct tcb_s*)g_readytorun.head) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (!current_regs) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * current_regs does not refer to the thread at g_readytorun.head! + */ + + else + { + /* Save the return lr and cpsr and one scratch register + * These will be restored by the signal trampoline after + * the signals have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = current_regs[REG_PC]; + tcb->xcp.saved_basepri = current_regs[REG_BASEPRI]; + tcb->xcp.saved_xpsr = current_regs[REG_XPSR]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + current_regs[REG_PC] = (uint32_t)up_sigdeliver; + current_regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; + current_regs[REG_XPSR] = ARMV6M_XPSR_T; + + /* And make sure that the saved context in the TCB + * is the same as the interrupt return context. + */ + + up_savestate(tcb->xcp.regs); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return lr and cpsr and one scratch register + * These will be restored by the signal trampoline after + * the signals have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; + tcb->xcp.saved_basepri = tcb->xcp.regs[REG_BASEPRI]; + tcb->xcp.saved_xpsr = tcb->xcp.regs[REG_XPSR]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; + tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; + tcb->xcp.regs[REG_XPSR] = ARMV6M_XPSR_T; + } + + irqrestore(flags); + } +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/nuttx/arch/arm/src/armv6-m/up_sigdeliver.c b/nuttx/arch/arm/src/armv6-m/up_sigdeliver.c new file mode 100644 index 000000000..a69d64bf4 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_sigdeliver.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_sigdeliver.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <sched.h> +#include <debug.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "os_internal.h" +#include "up_internal.h" +#include "up_arch.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void up_sigdeliver(void) +{ + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + up_ledon(LED_SIGNAL); + + sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + ASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + up_copystate(regs, rtcb->xcp.regs); + regs[REG_PC] = rtcb->xcp.saved_pc; + regs[REG_BASEPRI] = rtcb->xcp.saved_basepri; + regs[REG_XPSR] = rtcb->xcp.saved_xpsr; + + /* Get a local copy of the sigdeliver function pointer. We do this so that + * we can nullify the sigdeliver function pointer in the TCB and accept + * more signal deliveries while processing the current pending signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + + /* Then restore the task interrupt state */ + + irqrestore((uint8_t)regs[REG_BASEPRI]); + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sdbg("Resuming\n"); + (void)irqsave(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of + * execution. + */ + + up_ledoff(LED_SIGNAL); + up_fullcontextrestore(regs); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ + diff --git a/nuttx/arch/arm/src/armv6-m/up_svcall.c b/nuttx/arch/arm/src/armv6-m/up_svcall.c new file mode 100644 index 000000000..c1e35d6ab --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_svcall.c @@ -0,0 +1,357 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_svcall.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <debug.h> + +#include <arch/irq.h> +#include <nuttx/sched.h> + +#ifdef CONFIG_NUTTX_KERNEL +# include <syscall.h> +#endif + +#include "svcall.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#undef SYSCALL_INTERRUPTIBLE +#if defined(CONFIG_NUTTX_KERNEL) +# if CONFIG_ARCH_INTERRUPTSTACK > 3 +# warning "CONFIG_ARCH_INTERRUPTSTACK and CONFIG_NUTTX_KERNEL are incompatible" +# warning "options as currently implemented. Interrupts will have to be disabled" +# warning "during SYScall processing to avoid un-handled nested interrupts" +# else +# define SYSCALL_INTERRUPTIBLE 1 +# endif +#endif + +/* Debug ********************************************************************/ +/* Debug output from this file may interfere with context switching! To get + * debug output you must enabled the following in your NuttX configuration: + * + * CONFIG_DEBUG and CONFIG_DEBUG_SCHED + * + * And you must explicitly define DEBUG_SVCALL below: + */ + +#undef DEBUG_SVCALL /* Define to debug SVCall */ +#ifdef DEBUG_SVCALL +# define svcdbg(format, arg...) slldbg(format, ##arg) +#else +# define svcdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dispatch_syscall + * + * Description: + * Dispatch a system call to the appropriate handling logic. + * + ****************************************************************************/ + +#ifdef CONFIG_NUTTX_KERNEL +static inline void dispatch_syscall(uint32_t *regs) +{ + uint32_t cmd = regs[REG_R0]; + FAR struct tcb_s *rtcb = sched_self(); + uintptr_t ret = (uintptr_t)ERROR; + + /* Verify the the SYS call number is within range */ + + if (cmd < SYS_maxsyscall) + { + /* Report error and return ERROR */ + + slldbg("ERROR: Bad SYS call: %d\n", cmd); + } + else + { + /* The index into the syscall table is offset by the number of architecture- + * specific reserved entries at the beginning of the SYS call number space. + */ + + int index = cmd - CONFIG_SYS_RESERVED; + + /* Enable interrupts while the SYSCALL executes */ + +#ifdef SYSCALL_INTERRUPTIBLE + irqenable(); +#endif + + /* Call the correct stub for each SYS call, based on the number of parameters */ + + svcdbg("Calling stub%d at %p\n", index, g_stubloopkup[index].stub0); + + switch (g_stubnparms[index]) + { + /* No parameters */ + + case 0: + ret = g_stublookup[index].stub0(); + break; + + /* Number of parameters: 1 */ + + case 1: + ret = g_stublookup[index].stub1(regs[REG_R1]); + break; + + /* Number of parameters: 2 */ + + case 2: + ret = g_stublookup[index].stub2(regs[REG_R1], regs[REG_R2]); + break; + + /* Number of parameters: 3 */ + + case 3: + ret = g_stublookup[index].stub3(regs[REG_R1], regs[REG_R2], + regs[REG_R3]); + break; + + /* Number of parameters: 4 */ + + case 4: + ret = g_stublookup[index].stub4(regs[REG_R1], regs[REG_R2], + regs[REG_R3], regs[REG_R4]); + break; + + /* Number of parameters: 5 */ + + case 5: + ret = g_stublookup[index].stub5(regs[REG_R1], regs[REG_R2], + regs[REG_R3], regs[REG_R4], + regs[REG_R5]); + break; + + /* Number of parameters: 6 */ + + case 6: + ret = g_stublookup[index].stub6(regs[REG_R1], regs[REG_R2], + regs[REG_R3], regs[REG_R4], + regs[REG_R5], regs[REG_R6]); + break; + + /* Unsupported number of paramters. Report error and return ERROR */ + + default: + slldbg("ERROR: Bad SYS call %d number parameters %d\n", + cmd, g_stubnparms[index]); + break; + } + +#ifdef SYSCALL_INTERRUPTIBLE + irqdisable(); +#endif + } + + /* Set up the return value. First, check if a context switch occurred. + * In this case, regs will no longer be the same as current_regs. In + * the case of a context switch, we will have to save the return value + * in the TCB where it can be returned later when the task is restarted. + */ + + if (regs != current_regs) + { + regs = rtcb->xcp.regs; + } + + /* Then return the result in R0 */ + + svcdbg("Return value regs: %p value: %d\n", regs, ret); + regs[REG_R0] = (uint32_t)ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_svcall + * + * Description: + * This is SVCall exception handler that performs context switching + * + ****************************************************************************/ + +int up_svcall(int irq, FAR void *context) +{ + uint32_t *regs = (uint32_t*)context; + + DEBUGASSERT(regs && regs == current_regs); + + /* The SVCall software interrupt is called with R0 = system call command + * and R1..R7 = variable number of arguments depending on the system call. + */ + + svcdbg("SVCALL Entry: regs: %p cmd: %d\n", regs, regs[REG_R0]); + svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcdbg(" PSR=%08x\n", regs[REG_XPSR]); + + /* Handle the SVCall according to the command in R0 */ + + switch (regs[REG_R0]) + { + /* R0=SYS_save_context: This is a save context command: + * + * int up_saveusercontext(uint32_t *saveregs); + * + * At this point, the following values are saved in context: + * + * R0 = SYS_save_context + * R1 = saveregs + * + * In this case, we simply need to copy the current regsters to the + * save register space references in the saved R1 and return. + */ + + case SYS_save_context: + { + DEBUGASSERT(regs[REG_R1] != 0); + memcpy((uint32_t*)regs[REG_R1], regs, XCPTCONTEXT_SIZE); + } + break; + + /* R0=SYS_restore_context: This a restore context command: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * + * At this point, the following values are saved in context: + * + * R0 = SYS_restore_context + * R1 = restoreregs + * + * In this case, we simply need to set current_regs to restore register + * area referenced in the saved R1. context == current_regs is the normal + * exception return. By setting current_regs = context[R1], we force + * the return to the saved context referenced in R1. + */ + + case SYS_restore_context: + { + DEBUGASSERT(regs[REG_R1] != 0); + current_regs = (uint32_t*)regs[REG_R1]; + } + break; + + /* R0=SYS_switch_context: This a switch context command: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * + * At this point, the following values are saved in context: + * + * R0 = 1 + * R1 = saveregs + * R2 = restoreregs + * + * In this case, we do both: We save the context registers to the save + * register area reference by the saved contents of R1 and then set + * current_regs to to the save register area referenced by the saved + * contents of R2. + */ + + case SYS_switch_context: + { + DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0); + memcpy((uint32_t*)regs[REG_R1], regs, XCPTCONTEXT_SIZE); + current_regs = (uint32_t*)regs[REG_R2]; + } + break; + + /* This is not an architecture-specific system call. If NuttX is built + * as a standalone kernel with a system call interface, then all of the + * additional system calls must be handled as in the default case. + */ + + default: +#ifdef CONFIG_NUTTX_KERNEL + dispatch_syscall(regs); +#else + slldbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]); +#endif + break; + } + + /* Report what happened. That might difficult in the case of a context switch */ + + if (regs != current_regs) + { + svcdbg("SVCall Return: Context switch!\n"); + svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + current_regs[REG_R0], current_regs[REG_R1], current_regs[REG_R2], current_regs[REG_R3], + current_regs[REG_R4], current_regs[REG_R5], current_regs[REG_R6], current_regs[REG_R7]); + svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + current_regs[REG_R8], current_regs[REG_R9], current_regs[REG_R10], current_regs[REG_R11], + current_regs[REG_R12], current_regs[REG_R13], current_regs[REG_R14], current_regs[REG_R15]); + svcdbg(" PSR=%08x\n", current_regs[REG_XPSR]); + } + else + { + svcdbg("SVCall Return: %d\n", regs[REG_R0]); + } + + return OK; +} diff --git a/nuttx/arch/arm/src/armv6-m/up_switchcontext.S b/nuttx/arch/arm/src/armv6-m/up_switchcontext.S new file mode 100644 index 000000000..ce0984bc8 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_switchcontext.S @@ -0,0 +1,98 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/up_switchcontext.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/irq.h> + +#include "nvic.h" +#include "svcall.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .cpu cortex-m0 + .file "up_switchcontext.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_switchcontext + * + * Description: + * Save the current thread context and restore the specified context. + * Full prototype is: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * + * Return: + * None + * + ************************************************************************************/ + + .align 2 + .code 16 + .thumb_func + .globl up_switchcontext + .type up_switchcontext, function +up_switchcontext: + + /* Perform the System call with R0=1, R1=saveregs, R2=restoreregs */ + + mov r2, r1 /* R2: restoreregs */ + mov r1, r0 /* R1: saveregs */ + mov r0, #SYS_switch_context /* R0: context switch */ + svc 0 /* Force synchronous SVCall (or Hard Fault) */ + + /* This call should not return */ + + bx lr /* Unnecessary ... will not return */ + .size up_switchcontext, .-up_switchcontext + .end + diff --git a/nuttx/arch/arm/src/armv6-m/up_systemreset.c b/nuttx/arch/arm/src/armv6-m/up_systemreset.c new file mode 100644 index 000000000..a02a0abd2 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_systemreset.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_systemreset.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * Darcy Gong + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> + +#include "up_arch.h" +#include "nvic.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + + /**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public functions + ****************************************************************************/ + +void up_systemreset(void) +{ + uint32_t regval; + + /* Set up for the system reset, retaining the priority group from the + * the AIRCR register. + */ + + regval = ((0x5fa << SYSCON_AIRCR_VECTKEY_SHIFT) | SYSCON_AIRCR_SYSRESETREQ); + putreg32(regval, ARMV6M_SYSCON_AIRCR); + + /* Ensure completion of memory accesses */ + + __asm volatile ("dsb"); + + /* Wait for the reset */ + + for (;;); +} diff --git a/nuttx/arch/arm/src/armv6-m/up_unblocktask.c b/nuttx/arch/arm/src/armv6-m/up_unblocktask.c new file mode 100644 index 000000000..c496a8f43 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_unblocktask.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_unblocktask.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sched.h> +#include <debug.h> +#include <nuttx/arch.h> + +#include "os_internal.h" +#include "clock_internal.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_unblock_task + * + * Description: + * A task is currently in an inactive task list but has been prepped to + * execute. Move the TCB to the ready-to-run list, restore its context, + * and start execution. + * + * Inputs: + * tcb: Refers to the tcb to be unblocked. This tcb is in one of the + * waiting tasks lists. It must be moved to the ready-to-run list and, + * if it is the highest priority ready to run taks, executed. + * + ****************************************************************************/ + +void up_unblock_task(struct tcb_s *tcb) +{ + /* Verify that the context switch can be performed */ + + if ((tcb->task_state < FIRST_BLOCKED_STATE) || + (tcb->task_state > LAST_BLOCKED_STATE)) + { + PANIC(OSERR_BADUNBLOCKSTATE); + } + else + { + struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head; + + /* Remove the task from the blocked task list */ + + sched_removeblocked(tcb); + + /* Reset its timeslice. This is only meaningful for round + * robin tasks but it doesn't here to do it for everything + */ + +#if CONFIG_RR_INTERVAL > 0 + tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK; +#endif + + /* Add the task in the correct location in the prioritized + * g_readytorun task list + */ + + if (sched_addreadytorun(tcb)) + { + /* The currently active task has changed! We need to do + * a context switch to the new task. + * + * Are we in an interrupt handler? + */ + + if (current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the g_readytorun task list. + */ + + rtcb = (struct tcb_s*)g_readytorun.head; + + /* Then switch contexts */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head; + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } + } +} diff --git a/nuttx/arch/arm/src/armv6-m/up_vectors.c b/nuttx/arch/arm/src/armv6-m/up_vectors.c new file mode 100644 index 000000000..bb98b0a79 --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/up_vectors.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/arm/src/armv6-m/up_vectors.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Cloned from the ARMv7-M version: + * + * Copyright (C) 2012 Michael Smith. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +#define IDLE_STACK ((unsigned)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) + +#ifndef ARMV6M_PERIPHERAL_INTERRUPTS +# error ARMV6M_PERIPHERAL_INTERRUPTS must be defined to the number of I/O interrupts to be supported +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Chip-specific entrypoint */ + +extern void __start(void); + +/* Common exception entrypoint */ + +extern void exception_common(void); + +/************************************************************************************ + * Public data + ************************************************************************************/ + +/* Provided by the linker script to indicate the end of the BSS */ + +extern char _ebss; + +/* The v7m vector table consists of an array of function pointers, with the first + * slot (vector zero) used to hold the initial stack pointer. + * + * As all exceptions (interrupts) are routed via exception_common, we just need to + * fill this array with pointers to it. + * + * Note that the [ ... ] desginated initialiser is a GCC extension. + */ + +unsigned _vectors[] __attribute__((section(".vectors"))) = + { + /* Initial stack */ + + IDLE_STACK, + + /* Reset exception handler */ + + (unsigned)&__start, + + /* Vectors 2 - n point directly at the generic handler */ + + [2 ... (15 + ARMV6M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common + }; diff --git a/nuttx/arch/arm/src/armv6-m/vfork.S b/nuttx/arch/arm/src/armv6-m/vfork.S new file mode 100644 index 000000000..0e9b9790d --- /dev/null +++ b/nuttx/arch/arm/src/armv6-m/vfork.S @@ -0,0 +1,144 @@ +/************************************************************************************ + * arch/arm/src/armv6-m/vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "up_vfork.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .cpu cortex-m0 + .file "vfork.S" + .globl up_vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling up_vfork() with the vfork() + * context as an argument. The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .align 2 + .code 16 + .thumb_func + .globl vfork + .type vfork, function +vfork: + /* Create a stack frame */ + + mov r0, sp /* Save the value of the stack on entry */ + sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ + + /* CPU registers */ + /* Save the volatile registers */ + + mov r1, sp + stmia r1!, {r4-r7} /* Save r4-r7 in the structure */ + mov r4, r8 /* Copy high registers to low registers */ + mov r5, r9 + mov r6, r10 + mov r7, fp + stmia r1!, {r4-r7} /* Save r8-r10 and fp in the structure */ + str r0, [r1, #0] /* Save the stack pointer in the structure */ + mov r0, r14 /* Copy lr to a low registers */ + str r0, [r1, #0] /* Save the stack pointer in the structure */ + + /* Then, call up_vfork(), passing it a pointer to the stack structure */ + + mov r0, sp + bl up_vfork + + /* Recover r4-r7 that were destroyed before up_vfork was called */ + + mov r1, sp + ldmia r1!, {r4-r7} + + /* Release the stack data and return the value returned by up_vfork */ + + ldr r1, [sp, #VFORK_LR_OFFSET] + mov r14, r1 + add sp, sp, #VFORK_SIZEOF + bx lr + .size vfork, .-vfork + .end + |