diff options
| author | Gregory Nutt <gnutt@nuttx.org> | 2013-12-18 09:01:43 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-12-18 09:01:43 -0600 |
| commit | 335c06f67d51c670c8244a82f13363161ee13e7d (patch) | |
| tree | b8f791265602721b5f6dccba3620b5d3a53cd736 /nuttx/arch/arm/src/armv7-a/arm_pghead.S | |
| parent | aecb26ec375c973784961bbf4416d2b068a4d06c (diff) | |
| download | nuttx-335c06f67d51c670c8244a82f13363161ee13e7d.tar.gz nuttx-335c06f67d51c670c8244a82f13363161ee13e7d.tar.bz2 nuttx-335c06f67d51c670c8244a82f13363161ee13e7d.zip | |
Cortex-A: Fix start-up cache invalidation logi
Diffstat (limited to 'nuttx/arch/arm/src/armv7-a/arm_pghead.S')
| -rw-r--r-- | nuttx/arch/arm/src/armv7-a/arm_pghead.S | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/nuttx/arch/arm/src/armv7-a/arm_pghead.S b/nuttx/arch/arm/src/armv7-a/arm_pghead.S index fcf449e9b..a11570515 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_pghead.S +++ b/nuttx/arch/arm/src/armv7-a/arm_pghead.S @@ -343,8 +343,11 @@ __start: */ mov r0, #0 - mcr CP15_ICIALLUIS(r0) /* Invalidate entire instruction cache Inner Shareable */ - mcr CP15_TLBIALLIS(r0) /* Invalidate entire Unified TLB Inner Shareable */ + mcr CP15_TLBIALL(r0,c7) /* Invalidate the entire unified TLB */ + mcr CP15_TLBIALL(r0,c6) + mcr CP15_TLBIALL(r0,c5) + mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */ + mcr CP15_ICIALLU(r0) /* Invalidate I-cache */ /* Load the page table address. * @@ -360,8 +363,9 @@ __start: * r4 = Address of the base of the L1 table */ - mcr CP15_TTBR0(r4) - mcr CP15_TTBR1(r4) + orr r1, r4, #0x48 + mcr CP15_TTBR0(r1) + mcr CP15_TTBR1(r1) /* Set the TTB control register (TTBCR) to indicate that we are using * TTBR0. r0 still holds the value of zero. @@ -421,8 +425,11 @@ __start: * SCTLR_Z Bit 11: Program flow prediction control always enabled on A5 */ - orr r0, r0, #(SCTLR_M /* | SCTLR_Z */) - + orr r0, r0, #(SCTLR_M) +#ifndef CONFIG_ARCH_CORTEXA5 + orr r0, r0, #(SCTLR_Z) +#endif + /* Position vectors to 0xffff0000 if so configured. * * SCTLR_V Bit 13: High vectors @@ -438,7 +445,8 @@ __start: * replacement strategy. */ -#ifndef CPU_CACHE_ROUND_ROBIN +#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5) + orr r0, r0, #(SCTLR_RR) #endif /* Dcache enable |