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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-04-02 16:27:00 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-04-02 16:27:00 -0600 |
| commit | febd235e77df36985b82064d31911fc29e0265ad (patch) | |
| tree | 3c4c905489f39dae9af8a4560394369460c81572 /nuttx/arch/arm/src/armv7-a/cache.h | |
| parent | 4da3d71a5b619a314689f8978763b83e20e32300 (diff) | |
| download | nuttx-febd235e77df36985b82064d31911fc29e0265ad.tar.gz nuttx-febd235e77df36985b82064d31911fc29e0265ad.tar.bz2 nuttx-febd235e77df36985b82064d31911fc29e0265ad.zip | |
SAMA5: Make sure the MMU and caches are disabled on power up; flush the vector region D-Cache after copying interrupt vectors; make sure that D-Cache, I-Cache, and TLBs are invalidated after modifying the AXI MATRIX remapping
Diffstat (limited to 'nuttx/arch/arm/src/armv7-a/cache.h')
| -rw-r--r-- | nuttx/arch/arm/src/armv7-a/cache.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/armv7-a/cache.h b/nuttx/arch/arm/src/armv7-a/cache.h index ec27b0f8f..6d121bd45 100644 --- a/nuttx/arch/arm/src/armv7-a/cache.h +++ b/nuttx/arch/arm/src/armv7-a/cache.h @@ -210,7 +210,7 @@ .macro cp15_disable_dcache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Updagte the SCTLR */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm /************************************************************************************ @@ -231,7 +231,7 @@ mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Updagte the SCTLR */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm /************************************************************************************ @@ -501,7 +501,7 @@ static inline void cp15_disable_dcache(void) ( "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Updagte the SCTLR */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ : : : "r0", "memory" @@ -529,7 +529,7 @@ static inline void cp15_disable_caches(void) "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Updagte the SCTLR */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ : : : "r0", "memory" |