Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A

11 files changed, 431 insertions, 105 deletions

diff --git a/nuttx/arch/arm/src/armv7-a/arm_copyarmstate.c b/nuttx/arch/arm/src/armv7-a/arm_copyarmstate.c
new file mode 100644
index 000000000..219d01a1e
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-a/arm_copyarmstate.c
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_copyarmstate.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_copyarmstate
+ ****************************************************************************/
+
+/* A little faster than most memcpy's */
+
+void up_copyarmstate(uint32_t *dest, uint32_t *src)
+{
+  int i;
+
+  /* In the Cortex-M3 model, the state is copied from the stack to the TCB,
+   * but only a reference is passed to get the state from the TCB.  So the
+   * following check avoids copying the TCB save area onto itself:
+   */
+
+  if (src != dest)
+    {
+      for (i = 0; i < ARM_CONTEXT_REGS; i++)
+        {
+          *dest++ = *src++;
+        }
+    }
+}
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/nuttx/arch/arm/src/armv7-a/arm_copystate.c b/nuttx/arch/arm/src/armv7-a/arm_copyfullstate.c
index 42c46628d..cdc43a9bd 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_copystate.c
+++ b/nuttx/arch/arm/src/armv7-a/arm_copyfullstate.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-a/arm_copystate.c
+ * arch/arm/src/armv7-a/arm_copyfullstate.c
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -61,12 +61,16 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: up_copystate
+ * Name: up_copyfullstate
+ *
+ * Description:
+ *    Copy the entire register save area (including the floating point
+ *    registers if applicable).  This is a little faster than most memcpy's
+ *    since it does 32-bit transfers.
+ *
  ****************************************************************************/
 
-/* A little faster than most memcpy's */
-
-void up_copystate(uint32_t *dest, uint32_t *src)
+void up_copyfullstate(uint32_t *dest, uint32_t *src)
 {
   int i;
 
@@ -79,4 +83,3 @@ void up_copystate(uint32_t *dest, uint32_t *src)
       *dest++ = *src++;
     }
 }
-
diff --git a/nuttx/arch/arm/src/armv7-a/arm_doirq.c b/nuttx/arch/arm/src/armv7-a/arm_doirq.c
index eec228b91..d7ec6fc91 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_doirq.c
+++ b/nuttx/arch/arm/src/armv7-a/arm_doirq.c
@@ -76,21 +76,14 @@ void up_doirq(int irq, uint32_t *regs)
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
   PANIC();
 #else
-  uint32_t *savestate;
-
-  /* Nested interrupts are not supported in this implementation.  If you want
-   * to implement nested interrupts, you would have to (1) change the way that
-   * current_regs is handled and (2) the design associated with
-   * CONFIG_ARCH_INTERRUPTSTACK.  The savestate variable will not work for
-   * that purpose as implemented here because only the outermost nested
-   * interrupt can result in a context switch (it can probably be deleted).
-   */
+  /* Nested interrupts are not supported */
+
+  DEBUGASSERT(current_regs == NULL);
 
   /* Current regs non-zero indicates that we are processing an interrupt;
    * current_regs is also used to manage interrupt level context switches.
    */
 
-  savestate    = (uint32_t*)current_regs;
   current_regs = regs;
 
   /* Mask and acknowledge the interrupt */
@@ -101,12 +94,24 @@ void up_doirq(int irq, uint32_t *regs)
 
   irq_dispatch(irq, regs);
 
-  /* Restore the previous value of current_regs.  NULL would indicate that
-   * we are no longer in an interrupt handler.  It will be non-NULL if we
-   * are returning from a nested interrupt.
+  /* Check for a context switch.  If a context switch occured, then
+   * current_regs will have a different value than it did on entry.  If an
+   * interrupt level context switch has occurred, then restore the floating
+   * point state before returning from the interrupt.
+   */
+
+  if (regs != current_regs)
+    {
+      /* Restore floating point registers */
+
+      up_restorefpu((uint32_t*)current_regs);
+    }
+
+  /* Set current_regs to NULL to indicate that we are no longer in an
+   * interrupt handler.
    */
 
-  current_regs = savestate;
+  current_regs = NULL;
 
   /* Unmask the last interrupt (global interrupts are still disabled) */
 
diff --git a/nuttx/arch/arm/src/armv7-a/arm_fullcontextrestore.S b/nuttx/arch/arm/src/armv7-a/arm_fullcontextrestore.S
index 6b0125612..1f10b8dde 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_fullcontextrestore.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_fullcontextrestore.S
@@ -74,16 +74,41 @@
 
 	.globl	up_fullcontextrestore
 	.type	up_fullcontextrestore, function
+
 up_fullcontextrestore:
 
-	/* On entry, a1 (r0) holds address of the register save area */
+	/* On entry, a1 (r0) holds address of the register save area.  All other
+	 * registers are available for use.
+	 */
+
+#ifdef CONFIG_ARCH_FPU
+	/* First, restore the floating point registers.  Lets do this before we
+	 * restore the arm registers so that we have plentry of registers to
+	 * work with.
+	 */
+
+	add		r1, r0, #(4*REG_S0)		/* r1=Address of FP register storage */
+
+	/* Load all floating point registers.  Registers are loaded in numeric order,
+	 * s0, s1, ... in increasing address order.
+	 */
+
+	vldmia	r1!, {s0-s31}			/* Restore the full FP context */
+
+	/* Load the floating point control and status register.   At the end of the
+	 * vstmia, r1 will point to the FPCSR storage location.
+	 */
+
+	ldr		r2, [r1], #4			/* Fetch the floating point control and status register */
+	vmsr	fpscr, r2				/* Restore the FPCSR */
+#endif
 
 	/* Recover all registers except for r0, r1, R15, and CPSR */
 
 	add		r1, r0, #(4*REG_R2)		/* Offset to REG_R2 storage */
 	ldmia	r1, {r2-r14}			/* Recover registers */
 
-	/* Create a stack frame to hold the PC */
+	/* Create a stack frame to hold the some registers */
 
 	sub		sp, sp, #(3*4)			/* Frame for three registers */
 	ldr		r1, [r0, #(4*REG_R0)]	/* Fetch the stored r0 value */
diff --git a/nuttx/arch/arm/src/armv7-a/arm_head.S b/nuttx/arch/arm/src/armv7-a/arm_head.S
index acb87b248..6cf1a8fdf 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_head.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_head.S
@@ -395,14 +395,11 @@ __start:
 
 	ldr		lr, .LCvstart			/* Abs. virtual address */
 
-	/* Configure the domain access register (see mmu.h).
-	 *
-	 *   Domains 0: Accesses are not checked
-	 *   Domains 1: Accesses are not checked
-	 *   Domains 2: Accesses checked against permissions in the TLB
+	/* Configure the domain access register (see mmu.h).  Only domain 0 is
+	 * supported and it uses the permissions in the TLB.
 	 */
 
-	mov		r0, #(DACR_MANAGER(0) | DACR_MANAGER(1) |  DACR_CLIENT(2))
+	mov		r0, #DACR_CLIENT(0)
 	mcr		CP15_DACR(r0)			/* Set domain access register */
 
 	/* Configure the system control register (see sctrl.h) */
diff --git a/nuttx/arch/arm/src/armv7-a/arm_restorefpu.S b/nuttx/arch/arm/src/armv7-a/arm_restorefpu.S
new file mode 100644
index 000000000..0d9a64066
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-a/arm_restorefpu.S
@@ -0,0 +1,108 @@
+/************************************************************************************
+ * arch/arm/src/armv7-a/arm_restorefpu.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+#ifdef CONFIG_ARCH_FPU
+
+	.file		"arm_restorefpu.S"
+
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.globl		up_restorefpu
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+	.text
+
+/************************************************************************************
+ * Name: up_restorefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in R0), restore the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void up_restorefpu(const uint32_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area containing the floating point
+ *     registers.
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.  However, it is called from
+ *   interrupt level assembly logic that assumes that r0 is preserved.
+ * 
+ ************************************************************************************/
+
+	.globl	up_restorefpu
+	.type	up_restorefpu, function
+
+up_restorefpu:
+
+	add		r1, r0, #(4*REG_S0)		/* R1=Address of FP register storage */
+
+	/* Load all floating point registers.  Registers are loaded in numeric order,
+	 * s0, s1, ... in increasing address order.
+	 */
+
+	vldmia	r1!, {s0-s31}			/* Restore the full FP context */
+
+	/* Load the floating point control and status register.   At the end of the
+	 * vstmia, r1 will point to the FPCSR storage location.
+	 */
+
+	ldr		r2, [r1], #4			/* Fetch the floating point control and status register */
+	vmsr	fpscr, r2				/* Restore the FPCSR */
+	bx		lr
+
+	.size	up_restorefpu, .-up_restorefpu
+#endif /* CONFIG_ARCH_FPU */
+	.end
+
diff --git a/nuttx/arch/arm/src/armv7-a/arm_savefpu.S b/nuttx/arch/arm/src/armv7-a/arm_savefpu.S
new file mode 100644
index 000000000..742db7848
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-a/arm_savefpu.S
@@ -0,0 +1,106 @@
+/************************************************************************************
+ * arch/arm/src/armv7-a/arm_savefpu.S
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+#ifdef CONFIG_ARCH_FPU
+
+	.file		"arm_savefpu.S"
+
+/************************************************************************************
+ * Preprocessor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.globl		up_savefpu
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+	.text
+
+/************************************************************************************
+ * Name: up_savefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in R0), save the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void up_savefpu(uint32_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area in which to save the floating point
+ *     registers
+ *
+ * Returned Value:
+ *   None
+ * 
+ ************************************************************************************/
+
+	.globl	up_savefpu
+	.type	up_savefpu, function
+
+up_savefpu:
+
+	add		r1, r0, #(4*REG_S0)		/* R1=Address of FP register storage */
+
+	/* Store all floating point registers.  Registers are stored in numeric order,
+	 * s0, s1, ... in increasing address order.
+	 */
+
+	vstmia	r1!, {s0-s31}			/* Save the full FP context */
+
+	/* Store the floating point control and status register.  At the end of the
+	 * vstmia, r1 will point to the FPCSR storage location.
+	 */
+
+	vmrs	r2, fpscr				/* Fetch the FPCSR */
+	str		r2, [r1], #4			/* Save the floating point control and status register */
+	bx		lr
+
+	.size	up_savefpu, .-up_savefpu
+#endif /* CONFIG_ARCH_FPU */
+	.end
diff --git a/nuttx/arch/arm/src/armv7-a/arm_saveusercontext.S b/nuttx/arch/arm/src/armv7-a/arm_saveusercontext.S
index 427a08765..bdf16a7a9 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_saveusercontext.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_saveusercontext.S
@@ -68,24 +68,23 @@
  * Public Functions
  ****************************************************************************/
 
+	.text
+
 /****************************************************************************
  * Name: up_saveusercontext
  ****************************************************************************/
 
-	.text
 	.globl	up_saveusercontext
 	.type	up_saveusercontext, function
+
 up_saveusercontext:
-	/* On entry, a1 (r0) holds address of struct xcptcontext.
-	 * Offset to the user region.
-	 */
 
-	/* Make sure that the return value will be non-zero (the
-	 * value of the other volatile registers don't matter --
-	 * r1-r3, ip).  This function is called throught the
-	 * normal C calling conventions and the values of these
-	 * registers cannot be assumed at the point of setjmp
-	 * return.
+	/* On entry, a1 (r0) holds address of struct xcptcontext */
+
+	/* Make sure that the return value will be non-zero (the value of the
+	 * other volatile registers don't matter -- r1-r3, ip).  This function
+	 * is called through the normal C calling conventions and the values of
+	 * these registers cannot be assumed at the point of setjmp return.
 	 */
 
 	mov		ip, #1
@@ -104,14 +103,38 @@ up_saveusercontext:
 	add		r1, r0, #(4*REG_CPSR)
 	str		r2, [r1]
 
-	/* Finally save the return address as the PC so that we
-	 * return to the exit from this function.
+	/* Save the return address as the PC so that we return to the exit from
+	 * this function.
 	 */
 
 	add		r1, r0, #(4*REG_PC)
 	str		lr, [r1]
 
-	/* Return 0 */
+	/* Save the floating point registers.
+	 * REVISIT:  Not all of the floating point registers need to be saved.
+	 * Some are volatile and need not be preserved across functions calls.
+	 * But right now, I can't find the definitive list of the volatile
+	 * floating point registers.
+	 */
+
+#ifdef CONFIG_ARCH_FPU
+	add		r1, r0, #(4*REG_S0)		/* R1=Address of FP register storage */
+
+	/* Store all floating point registers.  Registers are stored in numeric order,
+	 * s0, s1, ... in increasing address order.
+	 */
+
+	vstmia	r1!, {s0-s31}			/* Save the full FP context */
+
+	/* Store the floating point control and status register.  At the end of the
+	 * vstmia, r1 will point to the FPCSR storage location.
+	 */
+
+	vmrs	r2, fpscr				/* Fetch the FPCSR */
+	str		r2, [r1], #4			/* Save the floating point control and status register */
+#endif
+
+	/* Return 0 now indicating that this return is not a context switch */
 
 	mov		r0, #0			/* Return value == 0 */
 	mov		pc, lr			/* Return */
diff --git a/nuttx/arch/arm/src/armv7-a/arm_sigdeliver.c b/nuttx/arch/arm/src/armv7-a/arm_sigdeliver.c
index d2ad98474..a62e3e60e 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_sigdeliver.c
+++ b/nuttx/arch/arm/src/armv7-a/arm_sigdeliver.c
@@ -100,7 +100,7 @@ void up_sigdeliver(void)
 
   /* Save the real return state on the stack. */
 
-  up_copystate(regs, rtcb->xcp.regs);
+  up_copyfullstate(regs, rtcb->xcp.regs);
   regs[REG_PC]         = rtcb->xcp.saved_pc;
   regs[REG_CPSR]       = rtcb->xcp.saved_cpsr;
 
diff --git a/nuttx/arch/arm/src/armv7-a/arm_vectors.S b/nuttx/arch/arm/src/armv7-a/arm_vectors.S
index 172067163..74bffde6e 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_vectors.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_vectors.S
@@ -90,15 +90,15 @@ g_aborttmp:
 	.type	arm_vectorirq, %function
 
 arm_vectorirq:
-	/* On entry, we are in IRQ mode.  We are free to use
-	 * the IRQ mode r13 and r14.
+	/* On entry, we are in IRQ mode.  We are free to use the IRQ mode r13
+	 * and r14.
 	 */
 
-	ldr	r13, .Lirqtmp
-	sub	lr, lr, #4
-	str	lr, [r13]				/* Save lr_IRQ */
-	mrs	lr, spsr
-	str	lr, [r13, #4]			/* Save spsr_IRQ */
+	ldr		r13, .Lirqtmp
+	sub		lr, lr, #4
+	str		lr, [r13]				/* Save lr_IRQ */
+	mrs		lr, spsr
+	str		lr, [r13, #4]			/* Save spsr_IRQ */
 
 	/* Then switch back to SVC mode */
 
diff --git a/nuttx/arch/arm/src/armv7-a/mmu.h b/nuttx/arch/arm/src/armv7-a/mmu.h
index b0135de7a..08fa9231b 100644
--- a/nuttx/arch/arm/src/armv7-a/mmu.h
+++ b/nuttx/arch/arm/src/armv7-a/mmu.h
@@ -447,73 +447,43 @@
 
 #endif /* CONFIG_PAGING */
 
-/* Page Size Selections *************************************************************/
+/* MMU flags ************************************************************************/
 
-/* Create some friendly definitions to handle some differences between
- * small and tiny pages.
- */
-
-#if CONFIG_PAGING_PAGESIZE == 1024
-
-   /* Base of the L2 page table (aligned to 4Kb byte boundaries) */
-
-#  define PGTABLE_L2_BASE_PADDR PGTABLE_L2_FINE_PBASE
-#  define PGTABLE_L2_BASE_VADDR PGTABLE_L2_FINE_VBASE
-
-   /* Number of pages in an L2 table per L1 entry */
-
-#  define PTE_NPAGES            PTE_TINY_NPAGES
-
-   /* Mask to get the page table physical address from an L1 entry */
-
-#  define PG_L1_PADDRMASK       PMD_PTE_PADDR_MASK
+/* Create some friendly definitions to handle page table entries */
 
-   /* MMU Flags for each memory region */
-
-#  define MMU_L1_TEXTFLAGS      (PMD_TYPE_PTE)
-#  define MMU_L2_TEXTFLAGS      (PTE_TYPE_SMALL | PTE_AP_R12 | PTE_CACHEABLE)
-#  define MMU_L1_DATAFLAGS      (PMD_TYPE_PTE)
-#  define MMU_L2_DATAFLAGS      (PTE_TYPE_SMALL | PTE_AP_RW12 | PTE_CACHEABLE|PTE_B)
-#  define MMU_L2_ALLOCFLAGS     (PTE_TYPE_SMALL | PTE_AP_RW12)
-#  define MMU_L1_PGTABFLAGS     (PMD_TYPE_PTE)
-#  define MMU_L2_PGTABFLAGS     (PTE_TYPE_SMALL | PTE_AP_RW12)
-
-#  define MMU_L2_VECTRWFLAGS    (PTE_TYPE_SMALL | PTE_AP_RW12)
-#  define MMU_L2_VECTROFLAGS    (PTE_TYPE_SMALL | PTE_AP_R12 | PTE_CACHEABLE)
-
-#elif CONFIG_PAGING_PAGESIZE == 4096
-
-   /* Base of the L2 page table (aligned to 1Kb byte boundaries) */
-
-#  define PGTABLE_L2_BASE_PADDR PGTABLE_L2_PBASE
-#  define PGTABLE_L2_BASE_VADDR PGTABLE_L2_VBASE
+#if CONFIG_PAGING_PAGESIZE != 4096
+#  error "Unsupported value for CONFIG_PAGING_PAGESIZE"
+#endif
 
-   /* Number of pages in an L2 table per L1 entry */
+/* Base of the L2 page table (aligned to 1Kb byte boundaries) */
 
-#  define PTE_NPAGES            PTE_SMALL_NPAGES
+#define PGTABLE_L2_BASE_PADDR PGTABLE_L2_PBASE
+#define PGTABLE_L2_BASE_VADDR PGTABLE_L2_VBASE
 
-   /* Mask to get the page table physical address from an L1 entry */
+/* Number of pages in an L2 table per L1 entry */
 
-#  define PG_L1_PADDRMASK       PMD_SECT_PADDR_MASK
+#define PTE_NPAGES            PTE_SMALL_NPAGES
+#define PT_SIZE               (4*PTE_NPAGES)
 
-   /* MMU Flags for each memory region. */
+/* Mask to get the page table physical address from an L1 entry */
 
-#  define MMU_L1_TEXTFLAGS      (PMD_TYPE_PTE)
-#  define MMU_L2_TEXTFLAGS      (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
-#  define MMU_L1_DATAFLAGS      (PMD_TYPE_PTE)
-#  define MMU_L2_DATAFLAGS      (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_B)
-#  define MMU_L2_ALLOCFLAGS     (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
-#  define MMU_L1_PGTABFLAGS     (PMD_TYPE_PTE)
-#  define MMU_L2_PGTABFLAGS     (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
+#define PG_L1_PADDRMASK       PMD_SECT_PADDR_MASK
 
-#  define MMU_L2_VECTRWFLAGS    (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
-#  define MMU_L2_VECTROFLAGS    (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
+/* MMU Flags for each type memory region. */
 
-#else
-#  error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
-#endif
+#define MMU_L1_TEXTFLAGS      (PMD_TYPE_PTE)
+#define MMU_L2_TEXTFLAGS      (PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRO | \
+                               PTE_CACHEABLE)
+#define MMU_L1_DATAFLAGS      (PMD_TYPE_PTE)
+#define MMU_L2_DATAFLAGS      (PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW | \
+                               PTE_CACHEABLE | PTE_B)
+#define MMU_L2_ALLOCFLAGS     (PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW)
+#define MMU_L1_PGTABFLAGS     (PMD_TYPE_PTE)
+#define MMU_L2_PGTABFLAGS     (PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW)
 
-#define PT_SIZE                 (4*PTE_NPAGES)
+#define MMU_L2_VECTRWFLAGS    (PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW)
+#define MMU_L2_VECTROFLAGS    (PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRO | \
+                               PTE_CACHEABLE)
 
 /* Addresses of Memory Regions ******************************************************/