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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2009-05-15 23:26:54 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2009-05-15 23:26:54 +0000
commit0368c4fac2539f3a8812f9471e9be74fb7aeb303 (patch)
tree9d9d30d5aa3c528f4ca4b098bba5e053e87e47b2 /nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
parentbead483344c325cdd7688d008023b4344af5951d (diff)
downloadnuttx-0368c4fac2539f3a8812f9471e9be74fb7aeb303.tar.gz
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Basic clocking and UART works
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1786 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm3s/lm3s_lowputc.c')
-rw-r--r--nuttx/arch/arm/src/lm3s/lm3s_lowputc.c50
1 files changed, 32 insertions, 18 deletions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
index f6d5272ef..8ab1d1a47 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
+++ b/nuttx/arch/arm/src/lm3s/lm3s_lowputc.c
@@ -220,47 +220,61 @@ void up_lowputc(char ch)
void up_lowsetup(void)
{
+ uint32 regval;
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32 ctl;
+#endif
+
+ /* Enable the selected UARTs and configure GPIO pins to need by the
+ * the selected UARTs. NOTE: The serial driver later depends on
+ * this pin configuration -- whether or not a serial console is selected.
+ */
+
+#ifndef CONFIG_UART0_DISABLE
+ regval = getreg32(LM3S_SYSCON_RCGC1);
+ regval |= SYSCON_RCGC1_UART0;
+ putreg32(regval, LM3S_SYSCON_RCGC1);
+
+ lm3s_configgpio(GPIO_UART0_RX);
+ lm3s_configgpio(GPIO_UART0_TX);
+#endif
+
+#ifndef CONFIG_UART1_DISABLE
+ regval = getreg32(LM3S_SYSCON_RCGC1);
+ regval |= SYSCON_RCGC1_UART1;
+ putreg32(regval, LM3S_SYSCON_RCGC1);
+
+ lm3s_configgpio(GPIO_UART1_RX);
+ lm3s_configgpio(GPIO_UART1_TX);
+#endif
/* Enable the selected console device */
- /* 1. Disable the UART by clearing the UARTEN bit in the UART CTL register */
+
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+ /* Disable the UART by clearing the UARTEN bit in the UART CTL register */
ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
ctl &= ~UART_CTL_UARTEN;
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
- /* 2. Write the integer portion of the BRD to the UART IBRD register */
+ /* Write the integer portion of the BRD to the UART IBRD register */
putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
- /* 3. Write the fractional portion of the BRD to the UART FBRD register */
+ /* Write the fractional portion of the BRD to the UART FBRD register */
putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
- /* 4. Write the desired serial parameters to the UART LCRH register */
+ /* Write the desired serial parameters to the UART LCRH register */
putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
- /* 5. Enable the UART by setting the UARTEN bit in the UART CTL register */
+ /* Enable the UART by setting the UARTEN bit in the UART CTL register */
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
#endif
- /* Then configure GPIO pins to enable the selected UARTs. NOTE: The
- * serial driver later depends on this pin configuration.
- */
-
-#ifndef CONFIG_UART0_DISABLE
- lm3s_configgpio(GPIO_UART0_RX);
- lm3s_configgpio(GPIO_UART0_TX);
-#endif
-
-#ifndef CONFIG_UART1_DISABLE
- lm3s_configgpio(GPIO_UART1_RX);
- lm3s_configgpio(GPIO_UART1_TX);
-#endif
}