Add LM3S6965 definition

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2654 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 55 insertions, 3 deletions

diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
index c3ffab27d..5179e3550 100644
--- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
+++ b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/lm3s/lm3s_memorymap.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,7 +48,7 @@
 
 /* Memory map ***********************************************************************/
  
-#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6965)
 #  define LM3S_FLASH_BASE     0x00000000 /* -0x0003ffff: On-chip FLASH */
                                          /* -0x1fffffff: Reserved */
 #  define LM3S_SRAM_BASE      0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
@@ -72,8 +72,13 @@
 #endif
 
 /* Peripheral base addresses ********************************************************/
+/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt
+ * peripheral modules.  They could probably be combined into one peripheral memory
+ * map.  However, keeping them separate does also provide so early, compile-time
+ * error detection that makes the duplication worthwhile.
+ */
 
-#ifdef CONFIG_ARCH_CHIP_LM3S6918
+#if defined(CONFIG_ARCH_CHIP_LM3S6918)
 /* FiRM Peripheral Base Addresses */
 
 #  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
@@ -115,6 +120,53 @@
 #  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                             /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
+/* FiRM Peripheral Base Addresses */
+
+#  define LM3S_WDOG_BASE      (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+                                                           /* -0x03fff: Reserved */
+#  define LM3S_GPIOA_BASE     (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+#  define LM3S_GPIOB_BASE     (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+#  define LM3S_GPIOC_BASE     (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+#  define LM3S_GPIOD_BASE     (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define LM3S_SSI0_BASE      (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+                                                           /* -0x0bfff: Reserved */
+#  define LM3S_UART0_BASE     (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+#  define LM3S_UART1_BASE     (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define LM3S_UART2_BASE     (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
+                                                           /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+#  define LM3S_I2CM0_BASE     (LM3S_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
+#  define LM3S_I2CS0_BASE     (LM3S_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define LM3S_I2CM1_BASE     (LM3S_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
+#  define LM3S_I2CS1_BASE     (LM3S_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+                                                            /* -0x23fff: Reserved */
+#  define LM3S_GPIOE_BASE     (LM3S_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
+#  define LM3S_GPIOF_BASE     (LM3S_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
+#  define LM3S_GPIOG_BASE     (LM3S_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
+                                                            /* -0x27fff: Reserved */
+#  define LM3S_PWM0_BASE      (LM3S_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM */
+                                                            /* -0x2bfff: Reserved */
+#  define LM3S_QEI0_BASE      (LM3S_PERIPH_BASE + 0x2c000)  /* -0x2cfff: QEI0 */
+#  define LM3S_QEI1_BASE      (LM3S_PERIPH_BASE + 0x2d000)  /* -0x2dfff: QEI1 */
+                                                            /* -0x2ffff: Reserved */
+#  define LM3S_TIMER0_BASE    (LM3S_PERIPH_BASE + 0x30000)  /* -0x30fff: Timer 0 */
+#  define LM3S_TIMER1_BASE    (LM3S_PERIPH_BASE + 0x31000)  /* -0x31fff: Timer 1 */
+#  define LM3S_TIMER2_BASE    (LM3S_PERIPH_BASE + 0x32000)  /* -0x32fff: Timer 2 */
+#  define LM3S_TIMER3_BASE    (LM3S_PERIPH_BASE + 0x33000)  /* -0x33fff: Timer 3 */
+                                                            /* -0x37fff: Reserved */
+#  define LM3S_ADC_BASE       (LM3S_PERIPH_BASE + 0x38000)  /* -0x38fff: ADC */
+                                                            /* -0x3bfff: Reserved */
+#  define LM3S_COMPARE_BASE   (LM3S_PERIPH_BASE + 0x3c000)  /* -0x3cfff: Analog Comparators */
+                                                            /* -0x47fff: Reserved */
+#  define LM3S_ETHCON_BASE    (LM3S_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
+                                                            /* -0xfcfff: Reserved */
+#  define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM3S_FLASHCON_BASE  (LM3S_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM3S_SYSCON_BASE    (LM3S_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+                                                            /* -0x1ffffff: Reserved */
+#else
 #else
 #  error "Peripheral base addresses not specified for this LM3S chip"
 #endif