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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-07-02 23:32:08 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2012-07-02 23:32:08 +0000 |
commit | cda1e504d9f8a9c9d2c730d9d3f4c96dff53eb20 (patch) | |
tree | 943f057e43903099f5b58b511e7e613dd9337f63 /nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h | |
parent | 8c15b6f4e858b9c10e4fa7c933d0a129a4f63f20 (diff) | |
download | nuttx-cda1e504d9f8a9c9d2c730d9d3f4c96dff53eb20.tar.gz nuttx-cda1e504d9f8a9c9d2c730d9d3f4c96dff53eb20.tar.bz2 nuttx-cda1e504d9f8a9c9d2c730d9d3f4c96dff53eb20.zip |
LM3S9B96 update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4899 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h')
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h index 5f4020cc1..773d3338f 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_syscontrol.h @@ -304,8 +304,8 @@ # define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ # define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ # define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ -#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 9-6: Crystal Value */ -#define SYSCON_RCC_XTAL_MASK (0x0f << SYSCON_RCC_XTAL_SHIFT) +#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ +#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) # define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ # define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ # define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ @@ -322,6 +322,15 @@ # define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ # define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ # define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ +#ifdef CONFIG_ARCH_CHIP_LM3S9B96 +# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ +# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ +# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ +# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ +# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ +#endif #define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ #define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ #define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ |