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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-08 20:56:40 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-08 20:56:40 +0000 |
| commit | ba1189436af1c941497484d199f383ffc64dc38f (patch) | |
| tree | 0ce5a8fef2db57cb94682de53ecdea6625f2b83f /nuttx/arch/arm/src/lm | |
| parent | 6e6b69155e425d81c6f92761bf80cf85ac79c808 (diff) | |
| download | nuttx-ba1189436af1c941497484d199f383ffc64dc38f.tar.gz nuttx-ba1189436af1c941497484d199f383ffc64dc38f.tar.bz2 nuttx-ba1189436af1c941497484d199f383ffc64dc38f.zip | |
Rename arch/arm/src/lm3s to arch/arm/src/lm to allow a namespace that will include the lm4f
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5495 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm')
33 files changed, 11812 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/lm/Kconfig b/nuttx/arch/arm/src/lm/Kconfig new file mode 100644 index 000000000..74d1712f3 --- /dev/null +++ b/nuttx/arch/arm/src/lm/Kconfig @@ -0,0 +1,217 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +comment "Stellaris Configuration Options" + +choice + prompt "Stellaris Chip Selection" + default ARCH_CHIP_LM3S6965 + depends on ARCH_CHIP_LM + +config ARCH_CHIP_LM3S6918 + bool "LM3S6918" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + select LM3S_HAVE_SSI1 + +config ARCH_CHIP_LM3S9B96 + bool "LM3S9B96" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +config ARCH_CHIP_LM3S6432 + bool "LM3S6432" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +config ARCH_CHIP_LM3S6965 + bool "LM3S6965" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +config ARCH_CHIP_LM3S8962 + bool "LM3S8962" + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + +endchoice + +# Chip families + +config ARCH_CHIP_LM3S + bool + +config ARCH_CHIP_LM4F + bool + +config LM3S_HAVE_SSI1 + bool + +config LM3S_REVA2 + bool "Rev A2" + default n + ---help--- + Some early silicon returned an increase LDO voltage or 2.75V to work + around a PLL bug + +config LM3S_DFU + bool "DFU" + default y + +menu "Select LM3S Peripheral Support" + +config LM3S_UART0 + bool "UART0" + select ARCH_HAVE_UART0 + default n + +config LM3S_UART1 + bool "UART1" + select ARCH_HAVE_UART1 + default n + +config SSI0_DISABLE + bool "Disable SSI0" + default y + +config SSI1_DISABLE + bool "Disable SSI1" + default y + +config LM3S_UART2 + bool "UART2" + select ARCH_HAVE_UART2 + default n + +config LM3S_ETHERNET + bool "LM3S Ethernet" + default n + ---help--- + This must be set (along with NET) to build the LM3S Ethernet driver. + +endmenu + +menu "Disable GPIO Interrupts" + +config LM3S_DISABLE_GPIOA_IRQS + bool "Disable GPIOA IRQs" + default n + +config LM3S_DISABLE_GPIOB_IRQS + bool "Disable GPIOB IRQs" + default n + +config LM3S_DISABLE_GPIOC_IRQS + bool "Disable GPIOC IRQs" + default n + +config LM3S_DISABLE_GPIOD_IRQS + bool "Disable GPIOD IRQs" + default n + +config LM3S_DISABLE_GPIOE_IRQS + bool "Disable GPIOE IRQs" + default n + +config LM3S_DISABLE_GPIOF_IRQS + bool "Disable GPIOF IRQs" + default n + +config LM3S_DISABLE_GPIOG_IRQS + bool "Disable GPIOG IRQs" + default n + +config LM3S_DISABLE_GPIOH_IRQS + bool "Disable GPIOH IRQs" + default n + +config LM3S_DISABLE_GPIOJ_IRQS + bool "Disable GPIOJ IRQs" + default n + +endmenu + +if LM3S_ETHERNET +menu "LM3S Ethernet Configuration" + +config LM3S_ETHLEDS + bool "Ethernet LEDs" + default n + ---help--- + Enable to use Ethernet LEDs on the board. + +config LM3S_BOARDMAC + bool "Board MAC" + default n + ---help--- + If the board-specific logic can provide a MAC address (via + lm3s_ethernetmac()), then this should be selected. + +config LM3S_ETHHDUPLEX + bool "Force Half Duplex" + default n + ---help--- + Set to force half duplex operation + +config LM3S_ETHNOAUTOCRC + bool "Disable auto-CRC" + default n + ---help--- + Set to suppress auto-CRC generation + +config LM3S_ETHNOPAD + bool "Disable Tx Padding" + default n + ---help--- + Set to suppress Tx padding + +config LM3S_MULTICAST + bool "Enable Multicast" + default n + ---help--- + Set to enable multicast frames + +config LM3S_PROMISCUOUS + bool "Enable Promiscuous Mode" + default n + ---help--- + Set to enable promiscuous mode + +config LM3S_TIMESTAMP + bool "Enable Timestamping" + default n + +config LM3S_BADCRC + bool "Enable Bad CRC Rejection" + default n + ---help--- + Set to enable bad CRC rejection. + +config M3S_DUMPPACKET + bool "Dump Packets" + default n + ---help--- + Dump each packet received/sent to the console. + +endmenu +endif + +if !SSI0_DISABLE || !SSI1_DISABLE +menu "LM3S SSI Configuration" + +config SSI_POLLWAIT + bool "Poll Wait (No-Interrupt) Mode" + default y + +config SSI_TXLIMIT + int "Tx Limit" + default 4 + ---help--- + Default of 4 assumes half of the 8 entry FIFO + +endmenu +endif + + diff --git a/nuttx/arch/arm/src/lm/Make.defs b/nuttx/arch/arm/src/lm/Make.defs new file mode 100644 index 000000000..aacbb1c83 --- /dev/null +++ b/nuttx/arch/arm/src/lm/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# arch/arm/src/lm/Make.defs +# +# Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <gnutt@nuttx.org> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = lm3s_vectors.S + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + vfork.S +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ + up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ + up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \ + up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ + up_releasepending.c up_releasestack.c up_reprioritizertr.c \ + up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \ + up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ + up_vfork.c + +ifeq ($(CONFIG_ARCH_MEMCPY),y) +CMN_ASRCS += up_memcpy.S +endif + +ifeq ($(CONFIG_ELF),y) +CMN_CSRCS += up_elf.c +endif + +CHIP_ASRCS = +CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c \ + lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \ + lm3s_serial.c lm3s_ssi.c lm3s_dumpgpio.c + +ifdef CONFIG_NET +CHIP_CSRCS += lm3s_ethernet.c +endif diff --git a/nuttx/arch/arm/src/lm/chip.h b/nuttx/arch/arm/src/lm/chip.h new file mode 100644 index 000000000..5857b3094 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip.h @@ -0,0 +1,83 @@ +/************************************************************************************ + * arch/arm/src/lm/chip.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_H +#define __ARCH_ARM_SRC_LM_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/lm/chip.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Then get all of the register definitions */ + +#include "chip/lm_memorymap.h" /* Memory map */ +#include "chip/lm3s_syscontrol.h" /* System control module */ +#include "chip/lm3s_gpio.h" /* GPIO modules */ +#include "chip/lm3s_uart.h" /* UART modules */ +#include "chip/lm3s_i2c.h" /* I2C modules */ +#include "chip/lm3s_ssi.h" /* SSI modules */ +#include "chip/lm3s_ethernet.h" /* Ethernet MAC and PHY */ +#include "chip/lm3s_flash.h" /* FLASH */ + +/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism + * will only look at the upper N bits of the 8-bit priority level (where N is 3 for + * the Stellaris family), so any prioritization must be performed in those bits. + * The default priority level is set to the middle value + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_epi.h b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h new file mode 100644 index 000000000..82fc94f4c --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_epi.h @@ -0,0 +1,113 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_epi.h + * + * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. + * Author: Max Neklyudov <macscomp@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* External Peripheral Interface Register Offsets ***********************************/ + +#define LM3S_EPI_CFG_OFFSET 0x000 +#define LM3S_EPI_SDRAMCFG_OFFSET 0x010 +#define LM3S_EPI_ADDRMAP_OFFSET 0x01C +#define LM3S_EPI_STAT_OFFSET 0x060 +#define LM3S_EPI_BAUD_OFFSET 0x004 + +/* External Peripheral Interface Register Addresses *********************************/ + +#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET) +#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET) +#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET) +#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET) +#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET) + +/* External Peripheral Interface Register Bit Definitions ***************************/ + +/* EPI Configuration (EPICFG), offset 0x000 */ + +#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ +#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) +# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ + +/* EPI Address Map (EPIADDRMAP), offset 0x01C */ + +#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ +#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) +# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) +#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ +#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) +# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) + +/* EPI Status (EPISTAT), offset 0x060 */ + +#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ +#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) + +/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ + +#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ +#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) +# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) +#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ +#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) +# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) +#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ +#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) +# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) + +/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ + +#define EPI_BAUD_COUNT0_SHIFT 0 +#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) +# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h new file mode 100644 index 000000000..512e96221 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_ethernet.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_ethernet.h + * + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/net/mii.h> + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Ethernet Controller Register Offsets *********************************************/ + +/* Ethernet MAC Register Offsets */ + +#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ +#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ +#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ +#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ +#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ +#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ +#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ +#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ +#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ +#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ +#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ +#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ +#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ +#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ +#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ +#endif + +/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ + +/* Ethernet Controller Register Addresses *******************************************/ + +#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET) +#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET) +#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET) +#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET) +#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET) +#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET) +#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET) +#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET) +#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET) +#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET) +#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET) +#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET) +#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) +#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) +#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) +#ifdef LM3S_ETHTS +# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) +#endif + +/* Memory Mapped MII Management Registers */ + +#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR) +#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR) +#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1) +#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2) +#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE) +#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA) +#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION) +#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC) +#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS) +#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC) +#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL) +#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG) +#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL) + +/* Ethernet Controller Register Bit Definitions *************************************/ + +/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ + +#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ +#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ +#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ +#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ +#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ +#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ +#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ + +#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ +#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ +#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ +#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ +#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ +#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ +#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ + +/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ + +#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ +#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ +#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ +#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ +#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ +#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ +#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ +#define MAC_IM_ALLINTS 0x7f + +/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ + +#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ +#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ +#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ +#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ +#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ + +/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ + +#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ +#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ +#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ +#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ + +/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ + +#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ + +/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ + +#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ +#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ +#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ +#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) + +/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ + +#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ + +/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ + +#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ + +/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ + +#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ + +/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ + +#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ + +/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ + +#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_flash.h b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h new file mode 100644 index 000000000..2f6dc78fa --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_flash.h @@ -0,0 +1,128 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_flash.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* FLASH register offsets ***********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ +#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ +#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ +#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ +#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ +#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */ + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ +#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ +#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ +#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ +#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ +#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ +#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ +#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ +#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ +#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ +#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ +#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ +#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ +#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ + +/* FLASH register addresses *********************************************************/ + +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash + * control base address of LM3S_FLASHCON_BASE. + */ + +#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET) +#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET) +#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET) +#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET) +#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET) +#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET) + +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the + * System Control base address of LM3S_SYSCON_BASE + */ + +#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET) +#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET) +#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET) +#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET) +#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET) +#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET) +#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET) +#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET) +#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET) +#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET) +#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET) +#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET) +#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET) +#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET) + +/* FLASH register bit defitiions ****************************************************/ +/* To be provided */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h new file mode 100644 index 000000000..2c199dae9 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_gpio.h @@ -0,0 +1,395 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ +#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ +#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ +#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ +#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ +#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ +#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ +#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ +#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ +#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ +#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ +#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ +#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ +#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ +#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ +#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ +#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ +#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ +#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ +#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ +#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ +#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ +#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ +#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ +#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ +#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ +#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ +#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ +#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ +#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ +#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ +#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ + +/* GPIO Register Addresses **********************************************************/ + +#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h new file mode 100644 index 000000000..e029c4f3f --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_i2c.h @@ -0,0 +1,247 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_i2c.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* I2C Register Offsets *************************************************************/ + +/* I2C Master */ + +#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ +#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ +#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ +#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ +#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ +#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ +#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ +#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ +#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ + +/* I2C Slave */ + +#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ +#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ +#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ +#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ +#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ +#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ +#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ + +/* I2C Register Addresses ***********************************************************/ + +#if LM3S_NI2C > 0 + +/* I2C Master */ + +#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000) +#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET) + +/* I2C Slave */ + +#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000) +#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET) + +/* I2C0 Master */ + +#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C0 Slave */ + +#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET) + +#if LM3S_NI2C > 1 + +/* I2C1 Master */ + +#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET) +#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET) +#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET) +#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET) +#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET) +#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET) +#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET) +#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET) +#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET) + +/* I2C1 Slave */ + +#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET) +#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET) +#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET) +#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET) +#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET) +#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET) +#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET) + +#endif +#endif + +/* I2C_Register Bit Definitions *****************************************************/ + +/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ + +#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ +#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ +#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) + +/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ + +#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ +#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ +#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ +#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ +#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ +#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ +#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ + +#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ +#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ +#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ +#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ + +/* I2C Master Data (I2CM_DR), offset 0x008 */ + +#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ + +/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ + +#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ + +/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ + +#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ + +/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ + +#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ + +#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ + +#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ + +/* I2C Master Configuration (I2CM_CR), offset 0x020 */ + +#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ +#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ +#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ + +/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ + +#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ + +/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ + +#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ +#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ +#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ + +#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ + +/* I2C Slave Data (I2CS_DR), offset 0x008 */ + +#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ + +/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ + +#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ + +/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ + +#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ + +/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ + +#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ + +/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ + +#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h new file mode 100644 index 000000000..51de04a2b --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h @@ -0,0 +1,360 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_memorymap.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory map ***********************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ + defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0xdfffffff: Reserved */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0x5fffffff: Reserved */ +# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ +#else +# error "Memory map not specified for this LM3S chip" +#endif + +/* Peripheral base addresses ********************************************************/ +/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt + * peripheral modules. They could probably be combined into one peripheral memory + * map. However, keeping them separate does also provide so early, compile-time + * error detection that makes the duplication worthwhile. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ + /* -0x27fff: Reserved */ +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ + /* -0x3fffff: Reserved */ +# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0xfcfff: Reserved */ +# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ + /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ +# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ +# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ + /* -0x3ffff: Reserved */ +# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ +# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0x49fff: Reserved */ +# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ + /* -0x53fff: Reserved */ +# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ + /* -0x57fff: Reserved */ +# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ +# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ +# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ +# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ +# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ +# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ +# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ +# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ +# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ + /* -0xcffff: Reserved */ +# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ + /* -0xfcfff: Reserved */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ +# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ + /* -0x1ffffff: Reserved */ +#else +# error "Peripheral base addresses not specified for this LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h new file mode 100644 index 000000000..85ec1369a --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h @@ -0,0 +1,281 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_pinmap.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* The following lists the input value to lm3s_configgpio to setup the alternate, + * hardware function for each pin. + */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_TMR5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_TMR4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ + +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) (differs) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ +# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ +# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: QEI module 0 index */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ +#else +# error "Unknown LM3S chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h new file mode 100644 index 000000000..be5a766e5 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_ssi.h @@ -0,0 +1,235 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_ssi.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> + +#if LM3S_NSSI > 0 + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* SSI register offsets *************************************************************/ + +#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ +#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ +#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */ +#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */ +#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ +#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ +#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ +#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ +#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ +#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ +#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ +#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ +#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ +#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ +#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ +#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ +#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ +#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ +#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ +#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ +#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ + +/* SSI register addresses ***********************************************************/ + +#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#if LM3S_NSSI > 1 +#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET) + +#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000) + +#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET) +#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET) +#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET) +#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET) +#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET) +#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET) +#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET) +#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET) +#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET) +#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET) +#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET) +#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET) +#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET) +#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET) +#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET) +#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET) +#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET) +#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET) +#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) +#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) +#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) +#endif /* LM3S_NSSI > 1 */ + +/* SSI register bit defitiions ******************************************************/ + +/* SSI Control 0 (SSICR0), offset 0x000 */ + +#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ +#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) +#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ +#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ +#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) +#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ +#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ +#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ +#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ +#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ +#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ +#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) + +/* SSI Control 1 (SSICR1), offset 0x004 */ + +#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ +#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ +#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ +#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ + +/* SSI Data (SSIDR), offset 0x008 */ + +#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ + +/* SSI Status (SSISR), offset 0x00c */ + +#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ +#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ +#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ +#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ +#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ + +/* SSI Clock Prescale (SSICPSR), offset 0x010 */ + +#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ + +/* SSI Interrupt Mask (SSIIM), offset 0x014 */ + +#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ +#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ +#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ +#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ + +/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ + +#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ +#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ +#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ +#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ + +/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ + +#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ +#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ +#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ +#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ + +/* SSI Interrupt Clear (SSIICR), offset 0x020 */ + +#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ +#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ + +/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ + +#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ + +/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ + +#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* LM3S_NSSI > 0 */ +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h new file mode 100644 index 000000000..00a222ee3 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h @@ -0,0 +1,495 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* System Control Register Offsets **************************************************/ + +#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ +#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ +#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ +#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ +#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ +#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ +#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ +#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ +#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ +#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ +#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ +#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ +#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ +#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ +#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ +#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ +#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ +#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ +#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ +#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ +#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ +#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ +#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ + +/* System Control Register Addresses ************************************************/ + +#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET) +#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET) +#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET) +#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET) +#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET) +#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET) +#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET) +#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET) +#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET) +#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET) +#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET) +#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET) +#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET) +#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET) +#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET) +#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET) +#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET) +#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET) +#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET) +#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET) +#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET) +#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET) +#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET) +#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET) +#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET) +#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET) +#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET) +#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET) +#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET) + +/* System Control Register Bit Definitions ******************************************/ + +/* Device Identification 0 (DID0), offset 0x000 */ + +#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ +#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) +#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ +#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) +#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ +#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) +#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ +#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) + +/* Device Identification 1 (DID1), offset 0x004 */ + +#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ +#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) +#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ +#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ +#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) +#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ +#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) +#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ +#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) +#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ +#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) +#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ +#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) +#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ +#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) + +/* Device Capabilities 0 (DC0), offset 0x008 */ + +#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ +#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) +#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ +#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) + +/* Device Capabilities 1 (DC1), offset 0x010 */ + +#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ +#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ +#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ +#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ +#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ +#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ +#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ +#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ +#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ +#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) +#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ +#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ +#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) + +/* Device Capabilities 2 (DC2), offset 0x014 */ + +#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ +#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ +#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ +#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ +#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ +#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ +#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ +#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ +#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ +#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ +#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ +#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ + +/* Device Capabilities 3 (DC3), offset 0x018 */ + +#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ +#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ +#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ +#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ +#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ +#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ +#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ +#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ +#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ +#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ +#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ +#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ +#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ +#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ +#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ +#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ +#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ +#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ +#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ +#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ + +/* Device Capabilities 4 (DC4), offset 0x01c */ + +#define SYSCON_DC4_GPIO(n) (1 << (n)) +#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ +#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ +#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ +#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ +#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ +#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ +#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ +#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ +#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ +#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ + +/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ + +#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ + +/* LDO Power Control (LDOPCTL), offset 0x034 */ + +#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ +#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) +# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ +# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ +# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ +# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ +# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ +# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ +# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ +# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ +# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ +# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ +# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ + +/* Software Reset Control 0 (SRCR0), offset 0x040 */ + +#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ +#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ +#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ + +/* Software Reset Control 1 (SRCR1), offset 0x044 */ + +#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ +#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ +#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ +#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ +#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ +#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ +#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ +#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ +#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ +#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ +#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ +#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ + +/* Software Reset Control 2 (SRCR2), offset 0x048 */ + +#define SYSCON_SRCR2_GPIO(n) (1 << (n)) +#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ +#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ +#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ +#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ +#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ +#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ +#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ +#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ +#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ +#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ + +/* Raw Interrupt Status (RIS), offset 0x050 */ + +#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ +#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ + +/* Interrupt Mask Control (IMC), offset 0x054 */ + +#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ +#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ + +/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ + +#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ +#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ + +/* Reset Cause (RESC), offset 0x05C */ + +#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ +#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ +#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ +#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ +#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ + +/* Run-Mode Clock Configuration (RCC), offset 0x060 */ + +#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ +#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ +#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ +#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) +# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ +# define SYSCON_RCC_OSCSRC_IOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC_OSCSRC_IOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC_OSCSRC_30KHZ (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ +#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ +#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) +# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ +# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ +# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ +# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ +# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ +# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ +# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ +# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ +# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ +# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ +# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ +# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ +# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ +# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ +#ifdef CONFIG_ARCH_CHIP_LM3S9B96 +# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ +# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ +# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ +# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ +# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ +#endif +#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ +#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ +#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ +#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ +#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) +# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) +#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ + +/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ + +#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ +#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) +#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ +#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) + +/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ + +#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ +#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) +# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ +# define SYSCON_RCC2_OSCSRC2_IOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ +# define SYSCON_RCC2_OSCSRC2_IOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ +# define SYSCON_RCC2_OSCSRC2_30KHZ (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ +# define SYSCON_RCC2_OSCSRC2_32KHZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ +#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ +#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ +#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ +#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) +# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) +#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ + +/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ + +#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) +#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ + +#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ + +#define SYSCON_RCGC2_GPIO(n) (1 << (n)) +#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ + +#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) +#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ + +#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ + +#define SYSCON_SCGC2_GPIO(n) (1 << (n)) +#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ + +#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ +#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ +#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ +#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) +#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ + +/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ + +#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ +#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ +#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ +#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ +#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ +#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ +#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ +#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ +#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ + +/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ + +#define SYSCON_DCGC2_GPIO(n) (1 << (n)) +#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ +#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ +#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ +#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ +#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ +#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ +#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ +#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ +#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ +#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ + +/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ + +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ +#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) +#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ +#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_timer.h b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h new file mode 100644 index 000000000..6be963cc3 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_timer.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_timer.h + * + * Copyright (C) 2012 Max Nekludov. All rights reserved. + * Author: Max Nekludov <macscomp@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Timer register offsets ***********************************************************/ + +#define TIMER_GPTMCFG_OFFSET 0x000 +#define TIMER_GPTMTAMR_OFFSET 0x004 +#define TIMER_GPTMCTL_OFFSET 0x00C +#define TIMER_GPTMIMR_OFFSET 0x018 +#define TIMER_GPTMRIS_OFFSET 0x01C +#define TIMER_GPTMICR_OFFSET 0x024 +#define TIMER_GPTMTAILR_OFFSET 0x028 +#define TIMER_GPTMTAR_OFFSET 0x048 + +/* SSI register addresses ***********************************************************/ + +#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000) + +#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET) +#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET) +#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET) +#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET) +#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET) +#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET) +#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET) +#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET) + +/* SSI register bit defitiions ******************************************************/ + +/* GPTM Configuration (GPTMCFG), offset 0x000 */ + +#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ +#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) +#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ +#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ +#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ + +/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ + +#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ +#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) +#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ +#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ +#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ +#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ +#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) +#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ +#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ +#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ +#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) +#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ +#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ +#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ +#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) +#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ +#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ +#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ +#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) + +/* GPTM Control (GPTMCTL), offset 0x00C */ + +#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ +#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) +#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ +#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) + +/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ + +#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ +#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) + +/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ + +#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ +#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) + +/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ + +#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ +#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_uart.h b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h new file mode 100644 index 000000000..98dcbce12 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm3s_uart.h @@ -0,0 +1,347 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm3s_uart.h + * + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H +#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* UART register offsets ************************************************************/ + +#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */ +#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */ +#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */ +#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */ +#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ +#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ +#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ +#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */ +#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */ +#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ +#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ +#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ +#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ +#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ +#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ +#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ +#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ +#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ +#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ +#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ +#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ +#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ +#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ +#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ +#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ +#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ + +/* UART register addresses **********************************************************/ + +#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000) + +#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET) +#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET) +#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET) +#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET) +#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET) +#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET) +#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET) +#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET) +#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET) +#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET) +#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET) + +#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET) +#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET) +#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET) +#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET) +#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET) +#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET) +#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET) +#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET) +#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET) +#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET) +#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET) +#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET) +#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET) +#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET) +#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET) +#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET) +#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET) +#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET) +#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET) +#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET) +#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET) +#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET) +#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET) +#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET) +#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET) +#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET) + +/* UART register bit settings *******************************************************/ + +/* UART Data (DR), offset 0x000 */ + +#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ +#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) +#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ +#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ +#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ +#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ + +/* UART Receive Status (RSR), offset 0x004 */ + +#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ +#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ +#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ +#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ + +/* UART Error Clear (ECR), offset 0x004 */ +/* Writing any value to this register clears pending error indications */ + +/* UART Flag (FR), offset 0x018 */ + +#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ +#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ +#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ +#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ +#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ + +/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ + +#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ + +/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ + +#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ + +/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ + +#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ + +/* Register 7: UART Line Control (LCRH), offset 0x02C */ + +#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ +#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ +#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ +#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ +#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ +#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ +#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) +# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ +# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ +# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ +# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ +#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ + +/* UART Control (CTL), offset 0x030 */ + +#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ +#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ +#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ +#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ +#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ +#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ + +/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ + +#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ +#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) +# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ +#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ +#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) +# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ +# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ +# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ +# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ +# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ + +/* UART Interrupt Mask (IM), offset 0x038 */ + +#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ +#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ +#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ +#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ +#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ +#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ +#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ + + +/* UART Raw Interrupt Status (RIS), offset 0x03c */ + +#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ +#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ +#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ +#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ +#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ +#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ +#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ + +/* UART Masked Interrupt Status (MIS), offset 0x040 */ + +#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ +#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ +#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ +#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ +#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ +#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ +#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ + +/* UART Interrupt Clear (ICR), offset 0x044 */ + +#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ +#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ +#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ +#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ +#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ +#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ +#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear + */ + +/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ + +#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ + +#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ + +#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ + +#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ + +#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ + +/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ + +#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ + +/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ + +#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ + +/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ + +#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ + +/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ + +#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ + +/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ + +#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ + +/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ + +#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ + +/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ + +#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h new file mode 100644 index 000000000..530ecdf64 --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h @@ -0,0 +1,69 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_memorymap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/* Include the memory map file for the specific Stellaris chip */ + +#ifdef CONFIG_ARCH_CHIP_LM3S +# include "chip/lm3s_memorymap.h" +#else +# error "Unsupported Stellaris memory map" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h new file mode 100644 index 000000000..b8154dd9f --- /dev/null +++ b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h @@ -0,0 +1,69 @@ +/************************************************************************************ + * arch/arm/src/lm/chip/lm_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H +#define __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/* Include the memory map file for the specific Stellaris chip */ + +#ifdef CONFIG_ARCH_CHIP_LM3S +# include "chip/lm3s_pinmap.h" +#else +# error "Unsupported Stellaris PIN mapping" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c new file mode 100644 index 000000000..a84dc59dd --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_dumpgpio.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_dumpgpio.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <debug.h> + +#include <nuttx/arch.h> + +#include "up_arch.h" + +#include "chip.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* NOTE: this is duplicated in lm3s_gpio.c */ + +#ifdef LM3S_GPIOH_BASE +static const uint32_t g_gpiobase[8] = +{ + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE, +}; + +static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#else +static const uint32_t g_gpiobase[8] = +{ + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0, +}; + +static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' }; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_gpiobaseaddress + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static inline uint32_t lm3s_gpiobaseaddress(int port) +{ + return g_gpiobase[port & 7]; +} + +/**************************************************************************** + * Name: lm3s_gpioport + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static inline uint8_t lm3s_gpioport(int port) +{ + return g_portchar[port & 7]; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lm3s_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t base; + uint32_t rcgc2; + bool enabled; + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + DEBUGASSERT(base != 0); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + rcgc2 = getreg32(LM3S_SYSCON_RCGC2); + enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0); + + lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", + lm3s_gpioport(port), pinset, base, msg); + lldbg(" RCGC2: %08x (%s)\n", + rcgc2, enabled ? "enabled" : "disabled" ); + + /* Don't bother with the rest unless the port is enabled */ + + if (enabled) + { + lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n", + getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET), + getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc)); + lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n", + getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET), + getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET)); + lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n", + getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET), + getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET), + getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET), + getreg32(base + LM3S_GPIO_SLR_OFFSET)); + } + irqrestore(flags); + return OK; +} diff --git a/nuttx/arch/arm/src/lm/lm3s_ethernet.c b/nuttx/arch/arm/src/lm/lm3s_ethernet.c new file mode 100644 index 000000000..f6edab5ae --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_ethernet.c @@ -0,0 +1,1472 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_ethernet.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#if defined(CONFIG_NET) && defined(CONFIG_LM3S_ETHERNET) + +#include <stdint.h> +#include <stdbool.h> +#include <time.h> +#include <string.h> +#include <debug.h> +#include <wdog.h> +#include <errno.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <arch/board/board.h> +#include <nuttx/net/uip/uip.h> +#include <nuttx/net/uip/uip-arp.h> +#include <nuttx/net/uip/uip-arch.h> + +#include "chip.h" +#include "up_arch.h" + +#include "lm_gpio.h" +#include "lm_ethernet.h" +#include "chip/lm_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Half duplex can be forced if CONFIG_LM3S_ETHHDUPLEX is defined. */ + +#ifdef CONFIG_LM3S_ETHHDUPLEX +# define LM3S_DUPLEX_SETBITS 0 +# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX +#else +# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX +# define LM3S_DUPLEX_CLRBITS 0 +#endif + +/* Auto CRC generation can be suppressed if CONFIG_LM3S_ETHNOAUTOCRC is definde */ + +#ifdef CONFIG_LM3S_ETHNOAUTOCRC +# define LM3S_CRC_SETBITS 0 +# define LM3S_CRC_CLRBITS MAC_TCTL_CRC +#else +# define LM3S_CRC_SETBITS MAC_TCTL_CRC +# define LM3S_CRC_CLRBITS 0 +#endif + +/* Tx padding can be suppressed if CONFIG_LM3S_ETHNOPAD is defined */ + +#ifdef CONFIG_LM3S_ETHNOPAD +# define LM3S_PADEN_SETBITS 0 +# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN +#else +# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN +# define LM3S_PADEN_CLRBITS 0 +#endif + +#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS) +#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS) + +/* Multicast frames can be enabled by defining CONFIG_LM3S_MULTICAST */ + +#ifdef CONFIG_LM3S_MULTICAST +# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL +# define LM3S_AMUL_CLRBITS 0 +#else +# define LM3S_AMUL_SETBITS 0 +# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL +#endif + +/* Promiscuous mode can be enabled by defining CONFIG_LM3S_PROMISCUOUS */ + +#ifdef CONFIG_LM3S_PROMISCUOUS +# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS +# define LM3S_PRMS_CLRBITS 0 +#else +# define LM3S_PRMS_SETBITS 0 +# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS +#endif + +/* Bad CRC rejection can be enabled by define CONFIG_LM3S_BADCRC */ + +#ifdef CONFIG_LM3S_BADCRC +# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC +# define LM3S_BADCRC_CLRBITS 0 +#else +# define LM3S_BADCRC_SETBITS 0 +# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC +#endif + +#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS) +#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS) + +/* CONFIG_LM3S_DUMPPACKET will dump the contents of each packet to the console. */ + +#ifdef CONFIG_LM3S_DUMPPACKET +# define lm3s_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) +#else +# define lm3s_dumppacket(m,a,n) +#endif + +/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ + +#define LM3S_WDDELAY (1*CLK_TCK) +#define LM3S_POLLHSEC (1*2) + +/* TX timeout = 1 minute */ + +#define LM3S_TXTIMEOUT (60*CLK_TCK) + +/* This is a helper pointer for accessing the contents of the Ethernet header */ + +#define ETHBUF ((struct uip_eth_hdr *)priv->ld_dev.d_buf) + +#define LM32S_MAX_MDCCLK 2500000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* EMAC statistics (debug only) */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) +struct lm3s_statistics_s +{ + uint32_t rx_int; /* Number of Rx interrupts received */ + uint32_t rx_packets; /* Number of packets received (sum of the following): */ + uint32_t rx_ip; /* Number of Rx IP packets received */ + uint32_t rx_arp; /* Number of Rx ARP packets received */ + uint32_t rx_dropped; /* Number of dropped, unsupported Rx packets */ + uint32_t rx_pktsize; /* Number of dropped, too small or too big */ + uint32_t rx_errors; /* Number of Rx errors (reception error) */ + uint32_t rx_ovrerrors; /* Number of Rx FIFO overrun errors */ + uint32_t tx_int; /* Number of Tx interrupts received */ + uint32_t tx_packets; /* Number of Tx packets queued */ + uint32_t tx_errors; /* Number of Tx errors (transmission error)*/ + uint32_t tx_timeouts; /* Number of Tx timeout errors */ +}; +# define EMAC_STAT(priv,name) priv->ld_stat.name++ +#else +# define EMAC_STAT(priv,name) +#endif + +/* The lm3s_driver_s encapsulates all state information for a single hardware + * interface + */ + +struct lm3s_driver_s +{ + /* The following fields would only be necessary on chips that support + * multiple Ethernet controllers. + */ + +#if LM3S_NETHCONTROLLERS > 1 + uint32_t ld_base; /* Ethernet controller base address */ + int ld_irq; /* Ethernet controller IRQ */ +#endif + + bool ld_bifup; /* true:ifup false:ifdown */ + WDOG_ID ld_txpoll; /* TX poll timer */ + WDOG_ID ld_txtimeout; /* TX timeout timer */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) + struct lm3s_statistics_s ld_stat; +#endif + + /* This holds the information visible to uIP/NuttX */ + + struct uip_driver_s ld_dev; /* Interface understood by uIP */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct lm3s_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS]; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Miscellaneous low level helpers */ + +#if LM3S_NETHCONTROLLERS > 1 +static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); +static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); +#else +static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset); +static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value); +#endif +static void lm3s_ethreset(struct lm3s_driver_s *priv); +#if 0 /* Not used */ +static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value); +#endif +static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr); + +/* Common TX logic */ + +static int lm3s_transmit(struct lm3s_driver_s *priv); +static int lm3s_uiptxpoll(struct uip_driver_s *dev); + +/* Interrupt handling */ + +static void lm3s_receive(struct lm3s_driver_s *priv); +static void lm3s_txdone(struct lm3s_driver_s *priv); +static int lm3s_interrupt(int irq, FAR void *context); + +/* Watchdog timer expirations */ + +static void lm3s_polltimer(int argc, uint32_t arg, ...); +static void lm3s_txtimeout(int argc, uint32_t arg, ...); + +/* NuttX callback functions */ + +static int lm3s_ifup(struct uip_driver_s *dev); +static int lm3s_ifdown(struct uip_driver_s *dev); +static int lm3s_txavail(struct uip_driver_s *dev); +#ifdef CONFIG_NET_IGMP +static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac); +static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethin + * + * Description: + * Read a register from the Ethernet module + * + * Parameters: + * priv - Reference to the driver state structure + * offset - Byte offset of the register from the ethernet base address + * + * Returned Value: + * Register value + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +static uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) +{ + return getreg32(priv->ld_base + offset); +} +#else +static inline uint32_t lm3s_ethin(struct lm3s_driver_s *priv, int offset) +{ + return getreg32(LM3S_ETHCON_BASE + offset); +} +#endif + +/**************************************************************************** + * Function: lm3s_ethout + * + * Description: + * Write a register to the Ethernet module + * + * Parameters: + * priv - Reference to the driver state structure + * offset - Byte offset of the register from the ethernet base address + * value - The value to write the Ethernet register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +static void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->ld_base + offset); +} +#else +static inline void lm3s_ethout(struct lm3s_driver_s *priv, int offset, uint32_t value) +{ + putreg32(value, LM3S_ETHCON_BASE + offset); +} +#endif + +/**************************************************************************** + * Function: lm3s_ethreset + * + * Description: + * Configure and reset the Ethernet module, leaving it in a disabled state. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_ethreset(struct lm3s_driver_s *priv) +{ + irqstate_t flags; + uint32_t regval; + +#if LM3S_NETHCONTROLLERS > 1 +# error "If multiple interfaces are supported, this function would have to be redesigned" +#endif + + /* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */ + + flags = irqsave(); + regval = getreg32(LM3S_SYSCON_RCGC2); + regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0); + putreg32(regval, LM3S_SYSCON_RCGC2); + nllvdbg("RCGC2: %08x\n", regval); + + /* Put the Ethernet controller into the reset state */ + + regval = getreg32(LM3S_SYSCON_SRCR2); + regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); + putreg32(regval, LM3S_SYSCON_SRCR2); + + /* Wait just a bit. This is a much longer delay than necessary */ + + up_mdelay(2); + + /* Then take the Ethernet controller out of the reset state */ + + regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0); + putreg32(regval, LM3S_SYSCON_SRCR2); + nllvdbg("SRCR2: %08x\n", regval); + + /* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */ + + up_mdelay(2); + + /* Enable Port F for Ethernet LEDs: LED0=Bit 3; LED1=Bit 2 */ + +#ifdef CONFIG_LM3S_ETHLEDS + /* Configure the pins for the peripheral function */ + + lm3s_configgpio(GPIO_ETHPHY_LED0 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); + lm3s_configgpio(GPIO_ETHPHY_LED1 | GPIO_STRENGTH_2MA | GPIO_PADTYPE_STD); +#endif + + /* Disable all Ethernet controller interrupts */ + + regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + regval &= ~MAC_IM_ALLINTS; + lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Clear any pending interrupts (shouldn't be any) */ + + regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); + lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + irqrestore(flags); +} + +/**************************************************************************** + * Function: lm3s_phywrite + * + * Description: + * Write a 16-bit word to a PHY register + * + * Parameters: + * priv - Reference to the driver state structure + * regaddr - Address of the PHY register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void lm3s_phywrite(struct lm3s_driver_s *priv, int regaddr, uint16_t value) +{ + /* Wait for any MII transactions in progress to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Set up the data to be written */ + + DEBUGASSERT(value < MAC_MTXD_MASK); + lm3s_ethout(priv, LM3S_MAC_MTXD_OFFSET, value); + + /* Set up the PHY register address and start the write operation */ + + regaddr <<= MAC_MCTL_REGADR_SHIFT; + DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); + lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START); + + /* Wait for the write transaction to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); +} +#endif + +/**************************************************************************** + * Function: lm3s_phyread + * + * Description: + * Write a 16-bit word to a PHY register + * + * Parameters: + * priv - Reference to the driver state structure + * regaddr - Address of the PHY register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static uint16_t lm3s_phyread(struct lm3s_driver_s *priv, int regaddr) +{ + /* Wait for any MII transactions in progress to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Set up the PHY register address and start the read operation */ + + regaddr <<= MAC_MCTL_REGADR_SHIFT; + DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr); + lm3s_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START); + + /* Wait for the write transaction to complete */ + + while ((lm3s_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0); + + /* Read and return the PHY data */ + + return (uint16_t)(lm3s_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK); +} + +/**************************************************************************** + * Function: lm3s_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +static int lm3s_transmit(struct lm3s_driver_s *priv) +{ + irqstate_t flags; + uint32_t regval; + uint8_t *dbuf; + int pktlen; + int bytesleft; + int ret = -EBUSY; + + /* Verify that the hardware is ready to send another packet */ + + flags = irqsave(); + if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* Increment statistics */ + + EMAC_STAT(priv, tx_packets); + lm3s_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); + + /* Transfer the packet into the Tx FIFO. The LS 16-bits of the first + * 32-bit word written to the Tx FIFO contains the Ethernet payload + * data length. That is the full length of the message (d_len) minus + * the size of the Ethernet header (14). + */ + + pktlen = priv->ld_dev.d_len; + nllvdbg("Sending packet, pktlen: %d\n", pktlen); + DEBUGASSERT(pktlen > UIP_LLH_LEN); + + dbuf = priv->ld_dev.d_buf; + regval = (uint32_t)(pktlen - 14); + regval |= ((uint32_t)(*dbuf++) << 16); + regval |= ((uint32_t)(*dbuf++) << 24); + lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + + /* Write all of the whole, 32-bit values in the middle of the packet */ + + for (bytesleft = pktlen - 2; bytesleft > 3; bytesleft -= 4, dbuf += 4) + { + /* Transfer a whole word from the user buffer. Note, the user + * buffer may be un-aligned. + */ + + lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf); + } + + /* Write the last, partial word in the FIFO */ + + if (bytesleft > 0) + { + /* Write the last word */ + + regval = 0; + switch (bytesleft) + { + case 0: + default: + break; + + case 3: + regval |= ((uint32_t)dbuf[2] << 16); + case 2: + regval |= ((uint32_t)dbuf[1] << 8); + case 1: + regval |= (uint32_t)dbuf[0]; + break; + } + lm3s_ethout(priv, LM3S_MAC_DATA_OFFSET, regval); + } + + /* Activate the transmitter */ + + lm3s_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + (void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm3s_txtimeout, 1, (uint32_t)priv); + ret = OK; + } + + irqrestore(flags); + return ret; +} + +/**************************************************************************** + * Function: lm3s_uiptxpoll + * + * Description: + * The transmitter is available, check if uIP has any outgoing packets ready + * to send. This is a callback from uip_poll(). uip_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_uiptxpoll(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + int ret = OK; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + nllvdbg("Poll result: d_len=%d\n", priv->ld_dev.d_len); + if (priv->ld_dev.d_len > 0) + { + /* Send the packet. lm3s_transmit() will return zero if the + * packet was successfully handled. + */ + + DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + uip_arp_out(&priv->ld_dev); + ret = lm3s_transmit(priv); + } + + /* If zero is returned, the polling will continue until all connections have + * been examined. + */ + + return ret; +} + +/**************************************************************************** + * Function: lm3s_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_receive(struct lm3s_driver_s *priv) +{ + uint32_t regval; + uint8_t *dbuf; + int pktlen; + int bytesleft; + + /* Loop while there are incoming packets to be processed */ + + while ((lm3s_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0) + { + /* Update statistics */ + + EMAC_STAT(priv, rx_packets); + + /* Copy the data data from the hardware to priv->ld_dev.d_buf. Set + * amount of data in priv->ld_dev.d_len + */ + + dbuf = priv->ld_dev.d_buf; + + /* The packet frame length begins in the LS 16-bits of the first + * word from the FIFO followed by the Ethernet header beginning + * in the MS 16-bits of the first word. + * + * Pick off the packet length from the first word. This packet length + * includes the len/type field (size 2) and the FCS (size 4). + */ + + regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + pktlen = (int)(regval & 0x0000ffff); + nllvdbg("Receiving packet, pktlen: %d\n", pktlen); + + /* Check if the pktlen is valid. It should be large enough to hold + * an Ethernet header and small enough to fit entirely in the I/O + * buffer. Six is subtracted to acount for the 2-byte length/type + * and 4 byte FCS that are not copied into the uIP packet. + */ + + if (pktlen > (CONFIG_NET_BUFSIZE + 6) || pktlen <= (UIP_LLH_LEN + 6)) + { + int wordlen; + + /* We will have to drop this packet */ + + nlldbg("Bad packet size dropped (%d)\n", pktlen); + EMAC_STAT(priv, rx_pktsize); + + /* The number of bytes and words left to read is pktlen - 4 (including, + * the final, possibly partial word) because we've already read 4 bytes. + */ + + wordlen = (pktlen - 1) >> 2; + + /* Read and discard the remaining words in the FIFO */ + + while (wordlen--) + { + (void)lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + } + + /* Check for another packet */ + + continue; + } + + /* Save the first two bytes from the first word */ + + *dbuf++ = (uint8_t)((regval >> 16) & 0xff); + *dbuf++ = (uint8_t)((regval >> 24) & 0xff); + + /* Read all of the whole, 32-bit values in the middle of the packet. + * We've already read the length (2 bytes) plus the first two bytes + * of data. + */ + + for (bytesleft = pktlen - 4; bytesleft > 7; bytesleft -= 4, dbuf += 4) + { + /* Transfer a whole word to the user buffer. Note, the user + * buffer may be un-aligned. + */ + + *(uint32_t*)dbuf = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + } + + /* Handle the last, partial word in the FIFO (0-3 bytes) and discard + * the 4-byte FCS. + */ + + for (; bytesleft > 0; bytesleft -= 4) + { + /* Read the last word. And transfer all but the last four + * bytes of the FCS into the user buffer. + */ + + regval = lm3s_ethin(priv, LM3S_MAC_DATA_OFFSET); + switch (bytesleft) + { + default: + break; + + case 7: + dbuf[2] = (regval >> 16) & 0xff; + case 6: + dbuf[1] = (regval >> 8) & 0xff; + case 5: + dbuf[0] = regval & 0xff; + break; + } + } + + /* Pass the packet length to uIP MINUS 2 bytes for the length and + * 4 bytes for the FCS. + */ + + priv->ld_dev.d_len = pktlen - 6; + lm3s_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len); + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv6 + if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP6)) +#else + if (ETHBUF->type == HTONS(UIP_ETHTYPE_IP)) +#endif + { + nllvdbg("IP packet received (%02x)\n", ETHBUF->type); + EMAC_STAT(priv, rx_ip); + + uip_arp_ipin(&priv->ld_dev); + uip_input(&priv->ld_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->ld_dev.d_len > 0) + { + uip_arp_out(&priv->ld_dev); + lm3s_transmit(priv); + } + } + else if (ETHBUF->type == htons(UIP_ETHTYPE_ARP)) + { + nllvdbg("ARP packet received (%02x)\n", ETHBUF->type); + EMAC_STAT(priv, rx_arp); + + uip_arp_arpin(&priv->ld_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->ld_dev.d_len > 0) + { + lm3s_transmit(priv); + } + } +#ifdef CONFIG_DEBUG + else + { + nlldbg("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); + EMAC_STAT(priv, rx_dropped); + } +#endif + } +} + +/**************************************************************************** + * Function: lm3s_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_txdone(struct lm3s_driver_s *priv) +{ + /* Cancel the TX timeout */ + + wd_cancel(priv->ld_txtimeout); + + /* Verify that the Tx FIFO is not in use. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. Since + * we get here because of of TXEMP which indicates that the packet was + * transmitted and that the TX FIFO is empty, NEWTX should always be zero + * at this point. + */ + + DEBUGASSERT((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + + /* Then poll uIP for new XMIT data */ + + (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); +} + +/**************************************************************************** + * Function: lm3s_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_interrupt(int irq, FAR void *context) +{ + register struct lm3s_driver_s *priv; + uint32_t ris; + +#if LM3S_NETHCONTROLLERS > 1 +# error "A mechanism to associate and interface with an IRQ is needed" +#else + priv = &g_lm3sdev[0]; +#endif + + /* Read the raw interrupt status register */ + + ris = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); + + /* Clear all pending interrupts */ + + lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, ris); + + /* Check for errors */ + +#if defined(CONFIG_DEBUG) && defined(CONFIG_DEBUG_NET) + if ((ris & MAC_RIS_TXER) != 0) + { + EMAC_STAT(priv, tx_errors); /* Number of Tx errors */ + } + + if ((ris & MAC_RIS_FOV) != 0) + { + EMAC_STAT(priv, rx_ovrerrors); /* Number of Rx FIFO overrun errors */ + } + + if ((ris & MAC_RIS_RXER) != 0) + { + EMAC_STAT(priv, rx_errors); /* Number of Rx errors */ + } +#endif + + /* Handle (unmasked) interrupts according to status bit settings */ + + ris &= lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + + /* Is this an Rx interrupt (meaning that a packet has been received)? */ + + if ((ris & MAC_RIS_RXINT) != 0) + { + /* Handle the incoming packet */ + + EMAC_STAT(priv, rx_int); + lm3s_receive(priv); + } + + /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */ + + if ((ris & MAC_RIS_TXEMP) != 0) + { + /* Handle the complete of the transmission */ + + EMAC_STAT(priv, tx_int); + lm3s_txdone(priv); + } + + /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if + * there are no pending transmissions). + */ + + return OK; +} + +/**************************************************************************** + * Function: lm3s_txtimeout + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_txtimeout(int argc, uint32_t arg, ...) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; + + /* Increment statistics */ + + nlldbg("Tx timeout\n"); + EMAC_STAT(priv, tx_timeouts); + + /* Then reset the hardware */ + + DEBUGASSERT(priv->ld_bifup); + lm3s_ifdown(&priv->ld_dev); + lm3s_ifup(&priv->ld_dev); + + /* Then poll uIP for new XMIT data */ + + (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); +} + +/**************************************************************************** + * Function: lm3s_polltimer + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void lm3s_polltimer(int argc, uint32_t arg, ...) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)arg; + + /* Check if we can send another Tx packet now. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. + * + * NOTE: This can cause missing poll cycles and, hence, some timing + * inaccuracies. + */ + + if ((lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* If so, update TCP timing states and poll uIP for new XMIT data */ + + (void)uip_timer(&priv->ld_dev, lm3s_uiptxpoll, LM3S_POLLHSEC); + + /* Setup the watchdog poll timer again */ + + (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, arg); + } +} + +/**************************************************************************** + * Function: lm3s_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_ifup(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + uint32_t div; + uint16_t phyreg; + + nlldbg("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + + /* Enable and reset the Ethernet controller */ + + flags = irqsave(); + lm3s_ethreset(priv); + + /* Set the management clock divider register for access to the PHY + * register set. The MDC clock is divided down from the system clock per: + * + * MDCCLK_FREQUENCY = SYSCLK_FREQUENCY / (2 * (div + 1)) + * div = (SYSCLK_FREQUENCY / 2 / MDCCLK_FREQUENCY) - 1 + * + * Where the maximum value for MDCCLK_FREQUENCY is 2,500,000. We will + * add 1 to assure the max LM32S_MAX_MDCCLK is not exceeded. + */ + + div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK; + lm3s_ethout(priv, LM3S_MAC_MDV_OFFSET, div); + nllvdbg("MDV: %08x\n", div); + + /* Then configure the Ethernet Controller for normal operation + * + * Setup the transmit control register (Full duplex, TX CRC Auto Generation, + * TX Padding Enabled). + */ + + regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval &= ~LM3S_TCTCL_CLRBITS; + regval |= LM3S_TCTCL_SETBITS; + lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + nllvdbg("TCTL: %08x\n", regval); + + /* Setup the receive control register (Disable multicast frames, disable + * promiscuous mode, disable bad CRC rejection). + */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~LM3S_RCTCL_CLRBITS; + regval |= LM3S_RCTCL_SETBITS; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + nllvdbg("RCTL: %08x\n", regval); + + /* Setup the time stamp configuration register */ + +#ifdef LM3S_ETHTS + regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET); +#ifdef CONFIG_LM3S_TIMESTAMP + regval |= MAC_TS_EN; +#else + regval &= ~(MAC_TS_EN); +#endif + lm3s_ethout(priv, LM3S_MAC_TS_OFFSET, regval); + nllvdbg("TS: %08x\n", regval); +#endif + + /* Wait for the link to come up. This following is not very conservative + * of system resources -- it really should wait gracefully on a semaphore + * and the interrupt handler should post the semaphore when LINKSTATUS is + * set + */ + + nlldbg("Waiting for link\n"); + do + { + phyreg = lm3s_phyread(priv, MII_MSR); + } + while ((phyreg & MII_MSR_LINKSTATUS) == 0); + nlldbg("Link established\n"); + + /* Reset the receive FIFO */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet receiver */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RXEN; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet transmitter */ + + regval = lm3s_ethin(priv, LM3S_MAC_TCTL_OFFSET); + regval |= MAC_TCTL_TXEN; + lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + + /* Reset the receive FIFO (again) */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Enable the Ethernet interrupt */ + +#if LM3S_NETHCONTROLLERS > 1 + up_enable_irq(priv->irq); +#else + up_enable_irq(LM3S_IRQ_ETHCON); +#endif + + /* Enable the Ethernet RX packet receipt interrupt */ + + regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + regval |= MAC_IM_RXINTM; + lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Program the hardware with it's MAC address (for filtering) */ + + regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0]; + lm3s_ethout(priv, LM3S_MAC_IA0_OFFSET, regval); + + regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 | + (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4]; + lm3s_ethout(priv, LM3S_MAC_IA1_OFFSET, regval); + + /* Set and activate a timer process */ + + (void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm3s_polltimer, 1, (uint32_t)priv); + + priv->ld_bifup = true; + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm3s_ifdown + * + * Description: + * NuttX Callback: Stop the interface. The only way to restore normal + * behavior is to call lm3s_ifup(). + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int lm3s_ifdown(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + + nlldbg("Taking down: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + + /* Cancel the TX poll timer and TX timeout timers */ + + flags = irqsave(); + wd_cancel(priv->ld_txpoll); + wd_cancel(priv->ld_txtimeout); + + /* Disable the Ethernet interrupt */ + +#if LM3S_NETHCONTROLLERS > 1 + up_disable_irq(priv->irq); +#else + up_disable_irq(LM3S_IRQ_ETHCON); +#endif + + /* Disable all Ethernet controller interrupt sources */ + + regval = lm3s_ethin(priv, LM3S_MAC_IM_OFFSET); + regval &= ~MAC_IM_ALLINTS; + lm3s_ethout(priv, LM3S_MAC_IM_OFFSET, regval); + + /* Reset the receive FIFO */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Disable the Ethernet receiver */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~MAC_RCTL_RXEN; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Disable the Ethernet transmitter */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval &= ~MAC_TCTL_TXEN; + lm3s_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval); + + /* Reset the receive FIFO (again) */ + + regval = lm3s_ethin(priv, LM3S_MAC_RCTL_OFFSET); + regval |= MAC_RCTL_RSTFIFO; + lm3s_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval); + + /* Clear any pending interrupts */ + + regval = lm3s_ethin(priv, LM3S_MAC_RIS_OFFSET); + lm3s_ethout(priv, LM3S_MAC_IACK_OFFSET, regval); + + /* The interface is now DOWN */ + + priv->ld_bifup = false; + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm3s_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int lm3s_txavail(struct uip_driver_s *dev) +{ + struct lm3s_driver_s *priv = (struct lm3s_driver_s *)dev->d_private; + irqstate_t flags; + + /* Ignore the notification if the interface is not yet up or if the Tx FIFO + * hardware is not available at this time. The NEWTX bit initiates an + * Ethernet transmission once the packet has been placed in the TX FIFO. + * This bit is cleared once the transmission has been completed. When the + * transmission completes, lm3s_txdone() will be called and the Tx polling + * will occur at that time. + */ + + flags = irqsave(); + if (priv->ld_bifup && (lm3s_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) + { + /* If the interface is up and we can use the Tx FIFO, then poll uIP + * for new Tx data + */ + + (void)uip_poll(&priv->ld_dev, lm3s_uiptxpoll); + } + + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Function: lm3s_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lm3s_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + +#warning "Multicast MAC support not implemented" + return OK; +} +#endif + +/**************************************************************************** + * Function: lm3s_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lm3s_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct lm3s_driver_s *priv = (FAR struct lm3s_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + +#warning "Multicast MAC support not implemented" + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface + * + * Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if LM3S_NETHCONTROLLERS > 1 +int lm3s_ethinitialize(int intf) +#else +static inline int lm3s_ethinitialize(int intf) +#endif +{ + struct lm3s_driver_s *priv = &g_lm3sdev[intf]; + int ret; + + /* Check if the Ethernet module is present */ + + ndbg("Setting up eth%d\n", intf); + +#if LM3S_NETHCONTROLLERS > 1 +# error "This debug check only works with one interface" +#else + DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)); +#endif + DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS); + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct lm3s_driver_s)); + priv->ld_dev.d_ifup = lm3s_ifup; /* I/F down callback */ + priv->ld_dev.d_ifdown = lm3s_ifdown; /* I/F up (new IP address) callback */ + priv->ld_dev.d_txavail = lm3s_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_IGMP + priv->ld_dev.d_addmac = lm3s_addmac; /* Add multicast MAC address */ + priv->ld_dev.d_rmmac = lm3s_rmmac; /* Remove multicast MAC address */ +#endif + priv->ld_dev.d_private = (void*)priv; /* Used to recover private state from dev */ + + /* Create a watchdog for timing polling for and timing of transmisstions */ + +#if LM3S_NETHCONTROLLERS > 1 +# error "A mechanism to associate base address an IRQ with an interface is needed" + priv->ld_base = ??; /* Ethernet controller base address */ + priv->ld_irq = ??; /* Ethernet controller IRQ number */ +#endif + priv->ld_txpoll = wd_create(); /* Create periodic poll timer */ + priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */ + + /* If the board can provide us with a MAC address, get the address + * from the board now. The MAC will not be applied until lm3s_ifup() + * is caleld (and the MAC can be overwritten with a netdev ioctl call). + */ + +#ifdef CONFIG_LM3S_BOARDMAC + lm3s_ethernetmac(&priv->ld_dev.d_mac); +#endif + + /* Perform minimal, one-time initialization -- just reset the controller and + * leave it disabled. The Ethernet controller will be reset and properly + * re-initialized each time lm3s_ifup() is called. + */ + + lm3s_ethreset(priv); + lm3s_ifdown(&priv->ld_dev); + + /* Attach the IRQ to the driver */ + +#if LM3S_NETHCONTROLLERS > 1 + ret = irq_attach(priv->irq, lm3s_interrupt); +#else + ret = irq_attach(LM3S_IRQ_ETHCON, lm3s_interrupt); +#endif + if (ret != 0) + { + /* We could not attach the ISR to the IRQ */ + + return -EAGAIN; + } + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + (void)netdev_register(&priv->ld_dev); + return OK; +} + + +/************************************************************************************ + * Name: up_netinitialize + * + * Description: + * Initialize the first network interface. If there are more than one interface + * in the chip, then board-specific logic will have to provide this function to + * determine which, if any, Ethernet controllers should be initialized. + * + ************************************************************************************/ + +#if LM3S_NETHCONTROLLERS == 1 +void up_netinitialize(void) +{ + (void)lm3s_ethinitialize(0); +} +#endif + +#endif /* CONFIG_NET && CONFIG_LM3S_ETHERNET */ + diff --git a/nuttx/arch/arm/src/lm/lm3s_gpio.c b/nuttx/arch/arm/src/lm/lm3s_gpio.c new file mode 100644 index 000000000..48cbefabf --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_gpio.c @@ -0,0 +1,854 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_gpio.c + * arch/arm/src/chip/lm3s_gpio.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> +#include <string.h> +#include <assert.h> +#include <debug.h> + +#include <arch/irq.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* These definitions are part of the implementation of the GPIO pad + * configuration of Table 9-1 in the LM3S6918 data sheet. + */ + +#define AFSEL_SHIFT 5 +#define AFSEL_1 (1 << AFSEL_SHIFT) /* Set/clear bit in GPIO AFSEL register */ +#define AFSEL_0 0 +#define AFSEL_X 0 + +#define DIR_SHIFT 4 +#define DIR_1 (1 << DIR_SHIFT) /* Set/clear bit in GPIO DIR register */ +#define DIR_0 0 +#define DIR_X 0 + +#define ODR_SHIFT 3 +#define ODR_1 (1 << ODR_SHIFT) /* Set/clear bit in GPIO ODR register */ +#define ODR_0 0 +#define ODR_X 0 + +#define DEN_SHIFT 2 +#define DEN_1 (1 << DEN_SHIFT) /* Set/clear bit in GPIO DEN register */ +#define DEN_0 0 +#define DEN_X 0 + +#define PUR_SHIFT 1 +#define PUR_1 (1 << PUR_SHIFT) /* Set/clear bit in GPIO PUR register */ +#define PUR_0 0 +#define PUR_X 0 + +#define PDR_SHIFT 0 +#define PDR_1 (1 << PDR_SHIFT) /* Set/clear bit in GPIO PDR register */ +#define PDR_0 0 +#define PDR_X 0 + +#define GPIO_INPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_INPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_OUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_OUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ODINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_ODINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ODOUTPUT_SETBITS (AFSEL_0 | DIR_1 | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_ODOUTPUT_CLRBITS (AFSEL_1 | DIR_0 | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_PFODIO_SETBITS (AFSEL_1 | DIR_X | ODR_1 | DEN_1 | PUR_X | PDR_X) +#define GPIO_PFODIO_CLRBITS (AFSEL_0 | DIR_X | ODR_0 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_PFIO_SETBITS (AFSEL_1 | DIR_X | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_PFIO_CLRBITS (AFSEL_0 | DIR_X | ODR_1 | DEN_0 | PUR_X | PDR_X) + +#define GPIO_ANINPUT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_0 | PUR_0 | PDR_0) +#define GPIO_ANINPUT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_1 | PUR_1 | PDR_1) + +#define GPIO_INTERRUPT_SETBITS (AFSEL_0 | DIR_0 | ODR_0 | DEN_1 | PUR_X | PDR_X) +#define GPIO_INTERRUPT_CLRBITS (AFSEL_1 | DIR_1 | ODR_1 | DEN_0 | PUR_X | PDR_X) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gpio_func_s +{ + uint8_t setbits; /* A set of GPIO register bits to set */ + uint8_t clrbits; /* A set of GPIO register bits to clear */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_func_s g_funcbits[] = +{ + {GPIO_INPUT_SETBITS, GPIO_INPUT_CLRBITS}, /* GPIO_FUNC_INPUT */ + {GPIO_OUTPUT_SETBITS, GPIO_OUTPUT_CLRBITS}, /* GPIO_FUNC_OUTPUT */ + {GPIO_ODINPUT_SETBITS, GPIO_ODINPUT_CLRBITS}, /* GPIO_FUNC_ODINPUT */ + {GPIO_ODOUTPUT_SETBITS, GPIO_ODOUTPUT_CLRBITS}, /* GPIO_FUNC_ODOUTPUT */ + {GPIO_PFODIO_SETBITS, GPIO_PFODIO_CLRBITS}, /* GPIO_FUNC_PFODIO */ + {GPIO_PFIO_SETBITS, GPIO_PFIO_CLRBITS}, /* GPIO_FUNC_PFIO */ + {GPIO_ANINPUT_SETBITS, GPIO_ANINPUT_CLRBITS}, /* GPIO_FUNC_ANINPUT */ + {GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */ +}; + +static const uint32_t g_gpiobase[LM3S_NPORTS] = +{ + /* All support LM3S parts have at least 7 ports, GPIOA-G */ + + LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE, + LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, + + /* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/ + +#if LM3S_NPORTS > 7 + LM3S_GPIOH_BASE, +#endif + + /* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/ + +#if LM3S_NPORTS > 8 + LM3S_GPIOJ_BASE, +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_gpiobaseaddress + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. + * + ****************************************************************************/ + +static uint32_t lm3s_gpiobaseaddress(unsigned int port) +{ + uint32_t gpiobase = 0; + if (port < LM3S_NPORTS) + { + gpiobase = g_gpiobase[port]; + } + return gpiobase; +} + +/**************************************************************************** + * Name: lm3s_gpiofunc + * + * Description: + * Configure GPIO registers for a specific function + * + ****************************************************************************/ + +static void lm3s_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s *func) +{ + uint32_t setbit; + uint32_t clrbit; + uint32_t regval; + + /* Set/clear/ignore the GPIO ODR bit. "The GPIO ODR register is the open drain + * control register. Setting a bit in this register enables the open drain + * configuration of the corresponding GPIO pad. When open drain mode is enabled, + * the corresponding bit should also be set in the GPIO Digital Input Enable + * (GPIO DEN) register ... Corresponding bits in the drive strength registers + * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the + * desired rise and fall times. The GPIO acts as an open drain input if the + * corresponding bit in the GPIO DIR register is set to 0; and as an open + * drain output when set to 1." + */ + + setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); + + /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control + * register. When a bit is set to 1, it enables a weak pull-up resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the + * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." + */ + + setbit = (((uint32_t)func->setbits >> PUR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> PUR_SHIFT) & 1) << pinno; + + if (setbit || clrbit) + { + regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + } + + /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control + * register. When a bit is set to 1, it enables a weak pull-down resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears + * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." + */ + + setbit = (((uint32_t)func->setbits >> PDR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> PDR_SHIFT) & 1) << pinno; + + if (setbit || clrbit) + { + regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + } + + /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable + * register. By default, with the exception of the GPIO signals used for JTAG/SWD + * function, all other GPIO signals are configured out of reset to be undriven + * (tristate). Their digital function is disabled; they do not drive a logic + * value on the pin and they do not allow the pin voltage into the GPIO receiver. + * To use the pin in a digital function (either GPIO or alternate function), the + * corresponding GPIODEN bit must be set." + */ + + setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); + + /* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data + * direction register. Bits set to 1 in the GPIODIR register configure + * the corresponding pin to be an output, while bits set to 0 configure the + * pins to be inputs. All bits are cleared by a reset, meaning all GPIO + * pins are inputs by default. + */ + + setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_DIR_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_DIR_OFFSET); + + /* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode + * control select register. Writing a 1 to any bit in this register selects + * the hardware control for the corresponding GPIO line. All bits are cleared + * by a reset, therefore no GPIO line is set to hardware control by default." + * + * NOTE: In order so set JTAG/SWD GPIOs, it is also necessary to lock, commit + * and unlock the GPIO. That is not implemented here. + */ + + setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno; + clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno; + + regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET); + regval &= ~clrbit; + regval |= setbit; + putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET); +} + +/**************************************************************************** + * Name: lm3s_gpiopadstrength + * + * Description: + * Set up pad strength and pull-ups + * + ****************************************************************************/ + +static inline void lm3s_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int strength = (cfgset & GPIO_STRENGTH_MASK) >> GPIO_STRENGTH_SHIFT; + uint32_t regoffset; + uint32_t regval; + uint32_t slrset; + uint32_t slrclr; + + /* Prepare bits to disable slew */ + + slrset = 0; + slrclr = pin; + + switch (strength) + { + case 0: /* 2mA pad drive strength */ + { + /* "The GPIODR2R register is the 2-mA drive control register. It + * allows for each GPIO signal in the port to be individually configured + * without affecting the other pads. When writing a DRV2 bit for a GPIO + * signal, the corresponding DRV4 bit in the GPIO DR4R register and the + * DRV8 bit in the GPIODR8R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR2R_OFFSET; + } + break; + + case 1: /* 4mA pad drive strength */ + { + /* "The GPIODR4R register is the 4-mA drive control register. It allows + * for each GPIO signal in the port to be individually configured without + * affecting the other pads. When writing the DRV4 bit for a GPIO signal, + * the corresponding DRV2 bit in the GPIO DR2R register and the DRV8 bit + * in the GPIO DR8R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR4R_OFFSET; + } + break; + + case 3: /* 8mA Pad drive with slew rate control */ + { + /* "The GPIOSLR register is the slew rate control register. Slew rate + * control is only available when using the 8-mA drive strength option + * via the GPIO 8-mA Drive Select (GPIODR8R) register..." + */ + + slrset = pin; + slrclr = 0; + } + /* Fall through */ + + case 2: /* 8mA pad drive strength (without slew rate control) */ + { + /* "The GPIODR8R register is the 8-mA drive control register. It + * allows for each GPIO signal in the port to be individually configured + * without affecting the other pads. When writing the DRV8 bit for a GPIO + * signal, the corresponding DRV2 bit in the GPIO DR2R register and the + * DRV4 bit in the GPIO DR4R register are automatically cleared by hardware." + */ + + regoffset = LM3S_GPIO_DR8R_OFFSET; + } + break; + } + + /* Set the selected pad strength and set/clear optional slew rate control */ + + regval = getreg32(base + regoffset); + regval |= pin; + putreg32(regval, base + regoffset); + + regval = getreg32(base + LM3S_GPIO_SLR_OFFSET); + regval &= slrclr; + regval |= slrset; + putreg32(regval, base + LM3S_GPIO_SLR_OFFSET); +} + +/**************************************************************************** + * Name: lm3s_gpiopadtype + * + * Description: + * Set up pad strength and pull-ups. Some of these values may be over- + * written by lm3s_gpiofunc, depending on the function selection. Others + * are optional for different function selections. + * + ****************************************************************************/ + +static inline void lm3s_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int padtype = (cfgset & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT; +#if 0 /* always overwritten by lm3s_gpiofunc */ + uint32_t odrset; + uint32_t odrclr; +#endif + uint32_t purset; + uint32_t purclr; + uint32_t pdrset; + uint32_t pdrclr; +#if 0 /* always overwritten by lm3s_gpiofunc */ + uint32_t denset; + uint32_t denclr; +#endif + uint32_t regval; + + /* Assume digital GPIO function, push-pull with no pull-up or pull-down */ + +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = 0; + odrclr = pin; +#endif + purset = 0; + purclr = pin; + pdrset = 0; + pdrclr = pin; +#if 0 /* always overwritten by lm3s_gpiofunc */ + denset = pin; + denclr = 0; +#endif + + switch (padtype) + { + case 0: /* Push-pull */ + default: + { + } + break; + + case 1: /* Push-pull with weak pull-up */ + { + purset = pin; + purclr = 0; + } + break; + case 2: /* Push-pull with weak pull-down */ + { + pdrset = pin; + pdrclr = 0; + } + break; + case 3: /* Open-drain */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + } + break; + case 4: /* Open-drain with weak pull-up */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + purset = pin; + purclr = 0; + } + break; + case 5: /* Open-drain with weak pull-down */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + odrset = pin; + odrclr = 0; +#endif + pdrset = pin; + pdrclr = 0; + } + break; + case 6: /* Analog comparator */ + { +#if 0 /* always overwritten by lm3s_gpiofunc */ + denset = 0; + denclr = pin; +#endif + } + break; + } + + /* Set/clear the GPIO ODR bit. "The GPIO ODR register is the open drain + * control register. Setting a bit in this register enables the open drain + * configuration of the corresponding GPIO pad. When open drain mode is enabled, + * the corresponding bit should also be set in the GPIO Digital Input Enable + * (GPIO DEN) register ... Corresponding bits in the drive strength registers + * (GPIO DR2R, GPIO DR4R, GPIO DR8R, and GPIO SLR ) can be set to achieve the + * desired rise and fall times. The GPIO acts as an open drain input if the + * corresponding bit in the GPIO DIR register is set to 0; and as an open + * drain output when set to 1." + */ + +#if 0 /* always overwritten by lm3s_gpiofunc */ + regval = getreg32(base + LM3S_GPIO_ODR_OFFSET); + regval &= ~odrclr; + regval |= odrset; + putreg32(regval, base + LM3S_GPIO_ODR_OFFSET); +#endif + + /* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control + * register. When a bit is set to 1, it enables a weak pull-up resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the + * corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..." + */ + + regval = getreg32(base + LM3S_GPIO_PUR_OFFSET); + regval &= ~purclr; + regval |= purset; + putreg32(regval, base + LM3S_GPIO_PUR_OFFSET); + + /* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control + * register. When a bit is set to 1, it enables a weak pull-down resistor on the + * corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears + * the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..." + */ + + regval = getreg32(base + LM3S_GPIO_PDR_OFFSET); + regval &= ~pdrclr; + regval |= pdrset; + putreg32(regval, base + LM3S_GPIO_PDR_OFFSET); + + /* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable + * register. By default, with the exception of the GPIO signals used for JTAG/SWD + * function, all other GPIO signals are configured out of reset to be undriven + * (tristate). Their digital function is disabled; they do not drive a logic + * value on the pin and they do not allow the pin voltage into the GPIO receiver. + * To use the pin in a digital function (either GPIO or alternate function), the + * corresponding GPIODEN bit must be set." + */ + +#if 0 /* always overwritten by lm3s_gpiofunc */ + regval = getreg32(base + LM3S_GPIO_DEN_OFFSET); + regval &= ~denclr; + regval |= denset; + putreg32(regval, base + LM3S_GPIO_DEN_OFFSET); +#endif +} + +/**************************************************************************** + * Name: lm3s_initoutput + * + * Description: + * Set the GPIO output value + * + ****************************************************************************/ + +static inline void lm3s_initoutput(uint32_t cfgset) +{ + bool value = ((cfgset & GPIO_VALUE_MASK) != GPIO_VALUE_ZERO); + lm3s_gpiowrite(cfgset, value); +} + +/**************************************************************************** + * Name: lm3s_interrupt + * + * Description: + * Configure the interrupt pin. + * + ****************************************************************************/ + +static inline void lm3s_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset) +{ + int inttype = (cfgset & GPIO_INT_MASK) >> GPIO_INT_SHIFT; + uint32_t regval; + uint32_t isset; + uint32_t isclr; + uint32_t ibeset; + uint32_t ibeclr; + uint32_t iveset; + uint32_t iveclr; + + /* Mask and clear the GPIO interrupt + * + * "The GPIOIM register is the interrupt mask register. Bits set to High in + * GPIO IM allow the corresponding pins to trigger their individual interrupts + * and the combined GPIO INTR line. Clearing a bit disables interrupt triggering + * on that pin. All bits are cleared by a reset." + */ + + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval &= ~pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + + /* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit + * in this register clears the corresponding interrupt edge detection logic + * register. Writing a 0 has no effect." + */ + + regval = getreg32(base + LM3S_GPIO_ICR_OFFSET); + regval |= pin; + putreg32(regval, base + LM3S_GPIO_ICR_OFFSET); + + /* Assume rising edge */ + + isset = 0; /* Not level sensed */ + isclr = pin; + ibeset = 0; /* Single edge */ + ibeclr = pin; + iveset = pin; /* Rising edge or high levels*/ + iveclr = 0; + + /* Then handle according to the selected interrupt type */ + + switch (inttype) + { + case 0: /* Interrupt on falling edge */ + { + iveset = 0; /* Falling edge or low levels*/ + iveclr = pin; + } + break; + + case 1: /* Interrupt on rising edge */ + default: + break; + + case 2: /* Interrupt on both edges */ + { + ibeset = pin; /* Both edges */ + ibeclr = 0; + } + break; + + case 3: /* Interrupt on low level */ + { + isset = pin; /* Level sensed */ + isclr = 0; + iveset = 0; /* Falling edge or low levels*/ + iveclr = pin; + } + break; + + case 4: /* Interrupt on high level */ + { + isset = pin; /* Level sensed */ + isclr = 0; + } + break; + } + + /* "The GPIO IS register is the interrupt sense register. Bits set to + * 1 in GPIOIS configure the corresponding pins to detect levels, while + * bits set to 0 configure the pins to detect edges. All bits are cleared + * by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IS_OFFSET); + regval &= isclr; + regval |= isset; + putreg32(regval, base + LM3S_GPIO_IS_OFFSET); + + /* "The GPIO IBE register is the interrupt both-edges register. When the + * corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is + * set to detect edges, bits set to High in GPIO IBE configure the + * corresponding pin to detect both rising and falling edges, regardless + * of the corresponding bit in the GPIO Interrupt Event (GPIO IEV) register ... + * Clearing a bit configures the pin to be controlled by GPIOIEV. All bits + * are cleared by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IBE_OFFSET); + regval &= ibeclr; + regval |= ibeset; + putreg32(regval, base + LM3S_GPIO_IBE_OFFSET); + + /* "The GPIOIEV register is the interrupt event register. Bits set to + * High in GPIO IEV configure the corresponding pin to detect rising edges + * or high levels, depending on the corresponding bit value in the GPIO + * Interrupt Sense (GPIO IS) register... Clearing a bit configures the pin to + * detect falling edges or low levels, depending on the corresponding bit + * value in GPIOIS. All bits are cleared by a reset. + */ + + regval = getreg32(base + LM3S_GPIO_IEV_OFFSET); + regval &= iveclr; + regval |= iveset; + putreg32(regval, base + LM3S_GPIO_IEV_OFFSET); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lm3s_configgpio(uint32_t cfgset) +{ + irqstate_t flags; + unsigned int func; + unsigned int port; + unsigned int pinno; + uint32_t pin; + uint32_t base; + uint32_t regval; + + /* Decode the basics */ + + func = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT; + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (cfgset & GPIO_NUMBER_MASK); + pin = (1 <<pinno); + + DEBUGASSERT(func <= GPIO_FUNC_MAX); + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + DEBUGASSERT(base != 0); + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + + /* Enable clocking for this GPIO peripheral. "To use the GPIO, the peripheral + * clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) + * in the RCGC2 register." + */ + + regval = getreg32(LM3S_SYSCON_RCGC2); + regval |= SYSCON_RCGC2_GPIO(port); + putreg32(regval, LM3S_SYSCON_RCGC2); + + /* First, set the port to digital input. This is the safest state in which + * to perform reconfiguration. + */ + + lm3s_gpiofunc(base, pinno, &g_funcbits[0]); + + /* Then set up pad strengths and pull-ups. These setups should be done before + * setting up the function because some function settings will over-ride these + * user options. + */ + + lm3s_gpiopadstrength(base, pin, cfgset); + lm3s_gpiopadtype(base, pin, cfgset); + + /* Then set up the real pin function */ + + lm3s_gpiofunc(base, pinno, &g_funcbits[func]); + + /* Special GPIO digital output pins */ + + if (func == 1 || func == 3) + { + lm3s_initoutput(cfgset); + } + + + /* Special setup for interrupt GPIO pins */ + + else if (func == 7) + { + lm3s_interrupt(base, pin, cfgset); + } + + irqrestore(flags); + return OK; +} + +/**************************************************************************** + * Name: lm3s_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lm3s_gpiowrite(uint32_t pinset, bool value) +{ + unsigned int port; + unsigned int pinno; + uint32_t base; + + /* Decode the basics */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (pinset & GPIO_NUMBER_MASK); + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + + /* "The GPIO DATA register is the data register. In software control mode, + * values written in the GPIO DATA register are transferred onto the GPIO + * port pins if the respective pins have been configured as outputs through + * the GPIO Direction (GPIO DIR) register ... + * + * "In order to write to GPIO DATA, the corresponding bits in the mask, + * resulting from the address bus bits [9:2], must be High. Otherwise, the + * bit values remain unchanged by the write. + * + * "... All bits are cleared by a reset." + */ + + putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))); +} + +/**************************************************************************** + * Name: lm3s_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lm3s_gpioread(uint32_t pinset, bool value) +{ + unsigned int port; + unsigned int pinno; + uint32_t base; + + /* Decode the basics */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pinno = (pinset & GPIO_NUMBER_MASK); + + /* Get the base address associated with the GPIO port */ + + base = lm3s_gpiobaseaddress(port); + + /* "... the values read from this register are determined for each bit + * by the mask bit derived from the address used to access the data register, + * bits [9:2]. Bits that are 1 in the address mask cause the corresponding + * bits in GPIODATA to be read, and bits that are 0 in the address mask cause + * the corresponding bits in GPIO DATA to be read as 0, regardless of their + * value. + * + * "A read from GPIO DATA returns the last bit value written if the respective + * pins are configured as outputs, or it returns the value on the + * corresponding input pin when these are configured as inputs. All bits + * are cleared by a reset." + */ + + return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0); +} + diff --git a/nuttx/arch/arm/src/lm/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c new file mode 100644 index 000000000..a54bfe335 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_gpioirq.c @@ -0,0 +1,434 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_gpioirq.c + * arch/arm/src/chip/lm3s_gpioirq.c + * + * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <debug.h> + +#include <arch/irq.h> + +#include "up_arch.h" +#include "os_internal.h" +#include "irq_internal.h" + +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A table of handlers for each GPIO interrupt */ + +static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS]; + +/* A table that maps a GPIO group to a GPIO base address. Overly complicated + * because we support disabling interrupt support for arbitrary ports. This + * must carefully match the IRQ numbers assigned in arch/arm/include/lm3s/irq.h + */ + +static const uint32_t g_gpiobase[] = +{ +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS + LM3S_GPIOA_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS + LM3S_GPIOB_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS + LM3S_GPIOC_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS + LM3S_GPIOD_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS + LM3S_GPIOE_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS + LM3S_GPIOF_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS + LM3S_GPIOG_BASE, +#endif + + /* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip + * does not support these higher ports, then they must be disabled in the + * configuration. Otherwise, the following will likely cause compilation + * errors! + */ + +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS + LM3S_GPIOH_BASE, +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS + LM3S_GPIOJ_BASE, +#endif +}; + +#define GPIO_NADDRS (sizeof(g_gpiobase)/sizeof(uint32_t)) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_gpiobaseaddress + * + * Input: + * gpioirq - A pin number in the range of 0 to NR_GPIO_IRQS. + * + * Description: + * Given a GPIO enumeration value, return the base address of the + * associated GPIO registers. NOTE that range checking was provided by + * callee + * + ****************************************************************************/ + +static uint32_t lm3s_gpiobaseaddress(unsigned int gpioirq) +{ + unsigned int ndx = gpioirq >> 3; + if (ndx < GPIO_NADDRS) + { + return g_gpiobase[ndx]; + } + return 0; +} + +/**************************************************************************** + * Name: lm3s_gpio*handler + * + * Description: + * Handle interrupts on each enabled GPIO port + * + ****************************************************************************/ + +static int lm3s_gpiohandler(uint32_t regbase, int irqbase, void *context) +{ + uint32_t mis; + int irq; + int pin; + + /* Handle each pending GPIO interrupt. "The GPIO MIS register is the masked + * interrupt status register. Bits read High in GPIO MIS reflect the status + * of input lines triggering an interrupt. Bits read as Low indicate that + * either no interrupt has been generated, or the interrupt is masked." + */ + + mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff; + + /* Clear all GPIO interrupts that we are going to process. "The GPIO ICR + * register is the interrupt clear register. Writing a 1 to a bit in this + * register clears the corresponding interrupt edge detection logic register. + * Writing a 0 has no effect." + */ + + putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET); + + /* Now process each IRQ pending in the MIS */ + + for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1) + { + if ((mis & 1) != 0) + { + irq = irqbase + pin; + g_gpioirqvector[irq - NR_IRQS](irq, context); + } + } + return OK; +} + +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS +static int lm3s_gpioahandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS +static int lm3s_gpiobhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS +static int lm3s_gpiochandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS +static int lm3s_gpiodhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS +static int lm3s_gpioehandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS +static int lm3s_gpiofhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS +static int lm3s_gpioghandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS +static int lm3s_gpiohhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context); +} +#endif + +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS +static int lm3s_gpiojhandler(int irq, FAR void *context) +{ + return lm3s_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_irqinitialize + * + * Description: + * Initialize all vectors to the unexpected interrupt handler + * + ****************************************************************************/ + +int gpio_irqinitialize(void) +{ + int i; + + /* Point all interrupt vectors to the unexpected interrupt */ + + for (i = 0; i < NR_GPIO_IRQS; i++) + { + g_gpioirqvector[i] = irq_unexpected_isr; + } + + /* Then attach each GPIO interrupt handlers and enable corresponding GPIO + * interrupts + */ + +#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS + irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler); + up_enable_irq(LM3S_IRQ_GPIOA); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS + irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler); + up_enable_irq(LM3S_IRQ_GPIOB); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS + irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler); + up_enable_irq(LM3S_IRQ_GPIOC); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS + irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler); + up_enable_irq(LM3S_IRQ_GPIOD); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS + irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler); + up_enable_irq(LM3S_IRQ_GPIOE); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS + irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler); + up_enable_irq(LM3S_IRQ_GPIOF); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS + irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler); + up_enable_irq(LM3S_IRQ_GPIOG); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS + irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler); + up_enable_irq(LM3S_IRQ_GPIOH); +#endif +#ifndef CONFIG_LM3S_DISABLE_GPIOJ_IRQS + irq_attach(LM3S_IRQ_GPIOJ, lm3s_gpiojhandler); + up_enable_irq(LM3S_IRQ_GPIOJ); +#endif + + return OK; +} + +/**************************************************************************** + * Name: gpio_irqattach + * + * Description: + * Attach in GPIO interrupt to the provide 'isr' + * + ****************************************************************************/ + +int gpio_irqattach(int irq, xcpt_t isr) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + int ret = ERROR; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + flags = irqsave(); + + /* If the new ISR is NULL, then the ISR is being detached. + * In this case, disable the ISR and direct any interrupts + * to the unexpected interrupt handler. + */ + + if (isr == NULL) + { +#ifndef CONFIG_ARCH_NOINTC + gpio_irqdisable(gpioirq); +#endif + isr = irq_unexpected_isr; + } + + /* Save the new ISR in the table. */ + + g_irqvector[gpioirq] = isr; + irqrestore(flags); + ret = OK; + } + return ret; +} + +/**************************************************************************** + * Name: gpio_irqenable + * + * Description: + * Enable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +void gpio_irqenable(int irq) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + uint32_t base; + uint32_t regval; + int pin; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + /* Get the base address of the GPIO module associated with this IRQ */ + + base = lm3s_gpiobaseaddress(gpioirq); + DEBUGASSERT(base != 0); + pin = (1 << (gpioirq & 7)); + + /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt + * mask register. Bits set to High in GPIO IM allow the corresponding + * pins to trigger their individual interrupts and the combined GPIO INTR + * line. Clearing a bit disables interrupt triggering on that pin. All + * bits are cleared by a reset. + */ + + flags = irqsave(); + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval |= pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + irqrestore(flags); + } +} + +/**************************************************************************** + * Name: gpio_irqdisable + * + * Description: + * Disable the GPIO IRQ specified by 'irq' + * + ****************************************************************************/ + +void gpio_irqdisable(int irq) +{ + irqstate_t flags; + int gpioirq = irq - NR_IRQS; + uint32_t base; + uint32_t regval; + int pin; + + if ((unsigned)gpioirq < NR_GPIO_IRQS) + { + /* Get the base address of the GPIO module associated with this IRQ */ + + base = lm3s_gpiobaseaddress(gpioirq); + DEBUGASSERT(base != 0); + pin = (1 << (gpioirq & 7)); + + /* Disable the GPIO interrupt. "The GPIO IM register is the interrupt + * mask register. Bits set to High in GPIO IM allow the corresponding + * pins to trigger their individual interrupts and the combined GPIO INTR + * line. Clearing a bit disables interrupt triggering on that pin. All + * bits are cleared by a reset. + */ + + flags = irqsave(); + regval = getreg32(base + LM3S_GPIO_IM_OFFSET); + regval &= ~pin; + putreg32(regval, base + LM3S_GPIO_IM_OFFSET); + irqrestore(flags); + } +} + diff --git a/nuttx/arch/arm/src/lm/lm3s_irq.c b/nuttx/arch/arm/src/lm/lm3s_irq.c new file mode 100644 index 000000000..2039d84a8 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_irq.c @@ -0,0 +1,458 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_irq.c + * arch/arm/src/chip/lm3s_irq.c + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <debug.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <arch/irq.h> + +#include "nvic.h" +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" + +#include "chip.h" +#include "lm_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Enable NVIC debug features that are probably only desireable during + * bringup + */ + +#undef LM3S_IRQ_DEBUG + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + NVIC_SYSH_PRIORITY_DEFAULT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +static void lm3s_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = irqsave(); + slldbg("NVIC (%s, irq=%d):\n", msg, irq); + slldbg(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + slldbg(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + slldbg(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + slldbg(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqrestore(flags); +} +#else +# define lm3s_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv, + * lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +static int lm3s_nmi(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! NMI received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_busfault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Bus fault recived\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_usagefault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Usage fault received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_pendsv(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! PendSV received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_dbgmonitor(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Debug Monitor receieved\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int lm3s_reserved(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Reserved interrupt\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} +#endif + +/**************************************************************************** + * Name: lm3s_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) +{ + DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= LM3S_IRQ_INTERRUPTS) + { + if (irq < LM3S_IRQ_INTERRUPTS + 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS); + } + else if (irq < NR_IRQS) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32); + } + else + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handler processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == LM3S_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == LM3S_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == LM3S_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == LM3S_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable all interrupts */ + + putreg32(0, NVIC_IRQ0_31_ENABLE); + putreg32(0, NVIC_IRQ32_63_ENABLE); + + /* Set all interrrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + + /* currents_regs is non-NULL only while processing an interrupt */ + + current_regs = NULL; + + /* Initialize support for GPIO interrupts if included in this build */ + +#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (gpio_irqinitialize != NULL) +#endif + { + gpio_irqinitialize(); + } +#endif + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(LM3S_IRQ_SVCALL, up_svcall); + irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO +/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARMV7M_MPU + irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); + up_enable_irq(LM3S_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG + irq_attach(LM3S_IRQ_NMI, lm3s_nmi); +#ifndef CONFIG_ARMV7M_MPU + irq_attach(LM3S_IRQ_MEMFAULT, up_memfault); +#endif + irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault); + irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault); + irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv); + irq_attach(LM3S_IRQ_DBGMONITOR, lm3s_dbgmonitor); + irq_attach(LM3S_IRQ_RESERVED, lm3s_reserved); +#endif + + lm3s_dumpnvic("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + setbasepri(NVIC_SYSH_PRIORITY_MAX); + irqrestore(0); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lm3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Clear the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + lm3s_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lm3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Set the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + lm3s_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_maskack_irq + * + * Description: + * Mask the IRQ and acknowledge it + * + ****************************************************************************/ + +void up_maskack_irq(int irq) +{ + up_disable_irq(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < LM3S_IRQ_INTERRUPTS) + { + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + } + else + { + irq -= LM3S_IRQ_INTERRUPTS; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + lm3s_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/nuttx/arch/arm/src/lm/lm3s_lowputc.c b/nuttx/arch/arm/src/lm/lm3s_lowputc.c new file mode 100644 index 000000000..7f9a826c8 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_lowputc.c @@ -0,0 +1,309 @@ +/************************************************************************** + * arch/arm/src/lm/lm3s_lowputc.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> + +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lm_gpio.h" +#include "chip/lm_pinmap.h" + +#include "lm_lowputc.h" + +/************************************************************************** + * Pre-processor Definitions + **************************************************************************/ + +/* Configuration **********************************************************/ + +#if LM3S_NUARTS < 2 +# undef CONFIG_LM3S_UART1 +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#if LM3S_NUARTS < 3 +# undef CONFIG_LM3S_UART2 +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Select UART parameters for the selected console */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART0_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART1_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define LM3S_CONSOLE_BASE LM3S_UART2_BASE +# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD +# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS +# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY +# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP +#else +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +#endif + +/* Get LCRH settings */ + +#if LM3S_CONSOLE_BITS == 5 +# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS +#elif LM3S_CONSOLE_BITS == 6 +# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS +#elif LM3S_CONSOLE_BITS == 7 +# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS +#elif LM3S_CONSOLE_BITS == 8 +# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS +#else +# error "Number of bits not supported" +#endif + +#if LM3S_CONSOLE_PARITY == 0 +# define UART_LCRH_PARITY (0) +#elif LM3S_CONSOLE_PARITY == 1 +# define UART_LCRH_PARITY UART_LCRH_PEN +#elif LM3S_CONSOLE_PARITY == 2 +# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS) +#else +# error "Invalid parity selection" +#endif + +#if LM3S_CONSOLE_2STOP != 0 +# define UART_LCRH_NSTOP UART_LCRH_STP2 +#else +# define UART_LCRH_NSTOP (0) +#endif + +#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN) + +/* Calculate BAUD rate from the SYS clock: + * + * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit + * fractional part. The number formed by these two values is used by the baud-rate generator + * to determine the bit period. Having a fractional baud-rate divider allows the UART to + * generate all the standard baud rates. + * + * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) + * register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate + * Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship + * to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional + * part, separated by a decimal place.): + * + * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) + * + * "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number + * (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated + * by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 + * to account for rounding errors: + * + * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) + * + * "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred + * to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is + * used for error detection during receive operations. + * + * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and + * UARTFBRD registers form an internal 30-bit register. This internal register is only + * updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate + * divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..." + */ + +#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD) +#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN) +#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI) +#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN) + +/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000: + * + * LM3S_BRDDEN = (16 * 115,200) = 1,843,200 + * LM3S_BRDI = 50,000,000 / 1,843,200 = 27 + * LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600 + * LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8 + * + * Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37 + */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + /* Wait until the TX FIFO is not full */ + + while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0); + + /* Then send the character */ + + putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET); +#endif +} + +/************************************************************************** + * Name: up_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + **************************************************************************/ + +void up_lowsetup(void) +{ + uint32_t regval; +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + uint32_t ctl; +#endif + + /* Enable the selected UARTs and configure GPIO pins to need by the + * the selected UARTs. NOTE: The serial driver later depends on + * this pin configuration -- whether or not a serial console is selected. + */ + +#ifdef CONFIG_LM3S_UART0 + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART0; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm3s_configgpio(GPIO_UART0_RX); + lm3s_configgpio(GPIO_UART0_TX); +#endif + +#ifdef CONFIG_LM3S_UART1 + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_UART1; + putreg32(regval, LM3S_SYSCON_RCGC1); + + lm3s_configgpio(GPIO_UART1_RX); + lm3s_configgpio(GPIO_UART1_TX); +#endif + + /* Enable the selected console device */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ + + ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + ctl &= ~UART_CTL_UARTEN; + putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); + + /* Write the integer portion of the BRD to the UART IBRD register */ + + putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET); + + /* Write the fractional portion of the BRD to the UART FBRD register */ + + putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET); + + /* Write the desired serial parameters to the UART LCRH register */ + + putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET); + + /* Enable the UART by setting the UARTEN bit in the UART CTL register */ + + ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); + putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET); +#endif + +} + + diff --git a/nuttx/arch/arm/src/lm/lm3s_serial.c b/nuttx/arch/arm/src/lm/lm3s_serial.c new file mode 100644 index 000000000..79628c765 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_serial.c @@ -0,0 +1,1064 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_serial.c + * + * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <unistd.h> +#include <semaphore.h> +#include <string.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <nuttx/serial/serial.h> + +#include <arch/serial.h> +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +#if LM3S_NUARTS < 2 +# undef CONFIG_LM3S_UART1 +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +#if LM3S_NUARTS < 3 +# undef CONFIG_LM3S_UART2 +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* Is there a UART enabled? */ + +#if !defined(CONFIG_LM3S_UART0) && !defined(CONFIG_LM3S_UART1) && !defined(CONFIG_LM3S_UART2) +# error "No UARTs enabled" +#endif + +/* Is there a serial console? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LM3S_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# warning "No valid CONFIG_UARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* If we are not using the serial driver for the console, then we + * still must provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# ifdef CONFIG_LM3S_UART1 +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# ifdef CONFIG_LM3S_UART0 +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# ifdef CONFIG_LM3S_UART0 +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elifdefined(CONFIG_LM3S_UART0) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# ifdef CONFIG_LM3S_UART1 +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# else +# undef TTYS2_DEV /* No ttyS2 */ +# endif +# else +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +# endif +#elifdefined(CONFIG_LM3S_UART1) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS2_DEV /* No ttyS2 */ +# ifdef CONFIG_LM3S_UART2 +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# else +# undef TTYS1_DEV /* No ttyS1 */ +# endif +#elifdefined(CONFIG_LM3S_UART2) +# undef CONSOLE_DEV /* No console device */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# undef TTYS2_DEV /* No ttyS2 */ +#else +# error "No valid TTY devices" +# undef CONSOLE_DEV /* No console device */ +# undef TTYS0_DEV /* No ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# undef TTYS2_DEV /* No ttyS2 */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t im; /* Saved IM value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_LM3S_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_LM3S_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_LM3S_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +/* This describes the state of the LM3S uart0 port. */ + +#ifdef CONFIG_LM3S_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = LM3S_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = LM3S_IRQ_UART0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the LM3S uart1 port. */ + +#ifdef CONFIG_LM3S_UART1 +static struct up_dev_s g_uart1priv = +{ + .uartbase = LM3S_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = LM3S_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the LM3S uart1 port. */ + +#ifdef CONFIG_LM3S_UART2 +static struct up_dev_s g_uart2priv = +{ + .uartbase = LM3S_UART2_BASE, + .baud = CONFIG_UART2_BAUD, + .irq = LM3S_IRQ_UART2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im) +{ + /* Return the current interrupt mask value */ + + if (im) + { + *im = priv->im; + } + + /* Disable all interrupts */ + + priv->im = 0; + up_serialout(priv, LM3S_UART_IM_OFFSET, 0); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im) +{ + priv->im = im; + up_serialout(priv, LM3S_UART_IM_OFFSET, im); +} + +/**************************************************************************** + * Name: up_waittxnotfull + ****************************************************************************/ + +#ifdef HAVE_CONSOLE +static inline void up_waittxnotfull(struct up_dev_s *priv) +{ + int tmp; + + /* Limit how long we will wait for the TX available condition */ + + for (tmp = 1000 ; tmp > 0 ; tmp--) + { + /* Check Tx FIFO is full */ + + if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0) + { + /* The Tx FIFO is not full... return */ + + break; + } + } + + /* If we get here, then the wait has timed out and the Tx FIFO remains + * full. + */ +} +#endif + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t lcrh; + uint32_t ctl; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t den; + uint32_t brdi; + uint32_t remainder; + uint32_t divfrac; + + /* Note: The logic here depends on the fact that that the UART module + * was enabled and the GPIOs were configured in up_lowsetup(). + */ + + /* Disable the UART by clearing the UARTEN bit in the UART CTL register */ + + ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); + ctl &= ~UART_CTL_UARTEN; + up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + + /* Calculate BAUD rate from the SYS clock: + * + * "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer + * and a 6-bit fractional part. The number formed by these two values is + * used by the baud-rate generator to determine the bit period. Having a + * fractional baud-rate divider allows the UART to generate all the standard + * baud rates. + * + * "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor + * (UARTIBRD) register ... and the 6-bit fractional part is loaded with the + * UART Fractional Baud-Rate Divisor (UARTFBRD) register... The baud-rate + * divisor (BRD) has the following relationship to the system clock (where + * BRDI is the integer part of the BRD and BRDF is the fractional part, + * separated by a decimal place.): + * + * "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) + * + * "where UARTSysClk is the system clock connected to the UART. The 6-bit + * fractional number (that is to be loaded into the DIVFRAC bit field in the + * UARTFBRD register) can be calculated by taking the fractional part of the + * baud-rate divisor, multiplying it by 64, and adding 0.5 to account for + * rounding errors: + * + * "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) + * + * "The UART generates an internal baud-rate reference clock at 16x the baud- + * rate (referred to as Baud16). This reference clock is divided by 16 to + * generate the transmit clock, and is used for error detection during receive + * operations. + * + * "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the + * UARTIBRD and UARTFBRD registers form an internal 30-bit register. This + * internal register is only updated when a write operation to UARTLCRH is + * performed, so any changes to the baud-rate divisor must be followed by a + * write to the UARTLCRH register for the changes to take effect. ..." + */ + + den = priv->baud << 4; + brdi = SYSCLK_FREQUENCY / den; + remainder = SYSCLK_FREQUENCY - den * brdi; + divfrac = ((remainder << 6) + (den >> 1)) / den; + + up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi); + up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac); + + /* Set up the LCRH register */ + + lcrh = 0; + switch (priv->bits) + { + case 5: + lcrh |= UART_LCRH_WLEN_5BITS; + break; + case 6: + lcrh |= UART_LCRH_WLEN_6BITS; + break; + case 7: + lcrh |= UART_LCRH_WLEN_7BITS; + break; + case 8: + default: + lcrh |= UART_LCRH_WLEN_8BITS; + break; + } + + switch (priv->parity) + { + case 0: + default: + break; + case 1: + lcrh |= UART_LCRH_PEN; + break; + case 2: + lcrh |= UART_LCRH_PEN|UART_LCRH_EPS; + break; + } + + if (priv->stopbits2) + { + lcrh |= UART_LCRH_STP2; + } + + up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); +#endif + + /* Set the UART to interrupt whenever the TX FIFO is almost empty or when + * any character is received. + */ + + up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th); + + /* Flush the Rx and Tx FIFOs -- How do you do that?*/ + + /* Enable Rx interrupts from the UART except for Tx interrupts. We don't want + * Tx interrupts until we have something to send. We will check for serial + * errors as part of Rx interrupt processing (no interrupts will be received + * yet because the interrupt is still disabled at the interrupt controller. + */ + + up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM); + + /* Enable the FIFOs */ + +#ifdef CONFIG_SUPPRESS_UART_CONFIG + lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET); +#endif + lcrh |= UART_LCRH_FEN; + up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh); + + /* Enable Rx, Tx, and the UART */ + +#ifdef CONFIG_SUPPRESS_UART_CONFIG + ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET); +#endif + ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE); + up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl); + + /* Set up the cache IM value */ + + priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET); + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception is + * the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked + * when an interrupt received on the 'irq' It should call + * uart_transmitchars or uart_receivechar to perform the + * appropriate data transfers. The interrupt handling logic\ + * must be able to map the 'irq' number into the approprite + * uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + uint32_t mis; + int passes; + bool handled; + +#ifdef CONFIG_LM3S_UART0 + if (g_uart0priv.irq == irq) + { + dev = &g_uart0port; + } + else +#endif +#ifdef CONFIG_LM3S_UART1 + if (g_uart1priv.irq == irq) + { + dev = &g_uart1port; + } + else +#endif + { + PANIC(OSERR_INTERNAL); + } + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the masked UART status and clear the pending interrupts. */ + + mis = up_serialin(priv, LM3S_UART_MIS_OFFSET); + up_serialout(priv, LM3S_UART_ICR_OFFSET, mis); + + /* Handle incoming, receive bytes (with or without timeout) */ + + if ((mis & (UART_MIS_RXMIS|UART_MIS_RTMIS)) != 0) + { + /* Rx buffer not empty ... process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + if ((mis & UART_MIS_TXMIS) != 0) + { + /* Tx FIFO not full ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + int ret = OK; + + switch (cmd) + { + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s*)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t rxd; + + /* Get the Rx byte + 4 bits of error information. Return those in status */ + + rxd = up_serialin(priv, LM3S_UART_DR_OFFSET); + *status = rxd; + + /* The lower 8bits of the Rx data is the actual recevied byte */ + + return rxd & 0xff; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx FIFO (or an Rx + * timeout occurs. + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= (UART_IM_RXIM|UART_IM_RTIM); +#endif + } + else + { + priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM); + } + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + irqstate_t flags; + + flags = irqsave(); + if (enable) + { + /* Set to receive an interrupt when the TX fifo is half emptied */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IM_TXIM; + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + + /* The serial driver wants an interrupt here, but will not get get + * one unless we "prime the pump." I believe that this is because + * behave like a level interrupt and the LM3S interrupts behave + * (at least by default) like edge interrupts. + * + * In any event, faking a TX interrupt here solves the problem; + * Call uart_xmitchars() just as would have been done if we recieved + * the TX interrupt. + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->im &= ~UART_IM_TXIM; + up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im); + } + irqrestore(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0); +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Performs the low level UART initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before up_serialinit. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the UARTs was performed in + * up_lowsetup + */ + + /* Disable all UARTS */ + + up_disableuartint(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + up_disableuartint(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disableuartint(TTYS2_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + uint32_t im; + + up_disableuartint(priv, &im); + up_waittxnotfull(priv); + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_waittxnotfull(priv); + up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r'); + } + + up_waittxnotfull(priv); + up_restoreuartint(priv, im); +#endif + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/nuttx/arch/arm/src/lm/lm3s_ssi.c b/nuttx/arch/arm/src/lm/lm3s_ssi.c new file mode 100644 index 000000000..8cd1cee07 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_ssi.c @@ -0,0 +1,1580 @@ +/**************************************************************************** + * arch/arm/src/lm32/lm3s_ssi.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> +#include <semaphore.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <nuttx/spi.h> + +#include <arch/irq.h> +#include <arch/board/board.h> + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "lm_gpio.h" +#include "lm_ssi.h" +#include "chip/lm_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG with + * CONFIG_DEBUG_VERBOSE too) + */ + +#undef SSI_DEBUG /* Define to enable debug */ + +#ifdef SSI_DEBUG +# define ssidbg lldbg +# define ssivdbg llvdbg +#else +# define ssidbg(x...) +# define ssivdbg(x...) +#endif + +/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI + * modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in + * such case, the following must be expanded). + */ + +#if LM3S_NSSI == 0 +# undef CONFIG_SSI0_DISABLE +# define CONFIG_SSI0_DISABLE 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#elif LM3S_NSSI == 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#endif + +/* Which SSI modules have been enabled? */ + +#ifndef CONFIG_SSI0_DISABLE +# define SSI0_NDX 0 /* Index to SSI0 in g_ssidev[] */ +# ifndef CONFIG_SSI1_DISABLE +# define SSI1_NDX 1 /* Index to SSI1 in g_ssidev[] */ +# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */ +# else +# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */ +# define SSI_BASE LM3S_SSI0_BASE +# define SSI_IRQ LM3S_IRQ_SSI0 +# endif +#else +# ifndef CONFIG_SSI1_DISABLE +# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */ +# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */ +# define SSI_BASE LM3S_SSI1_BASE +# define SSI_IRQ LM3S_IRQ_SSI1 +# else +# define NSSI_ENABLED 0 /* No SSI interfaces */ +# endif +#endif + +/* Compile the rest of the file only if at least one SSI interface has been + * enabled. + */ + +#if NSSI_ENABLED > 0 + +/* The number of (16-bit) words that will fit in the Tx FIFO */ + +#define LM3S_TXFIFO_WORDS 8 + +/* Configuration settings */ + +#ifndef CONFIG_SSI_TXLIMIT +# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2) +#endif + +#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS +# error "Invalid range for CONFIG_SSI_TXLIMIT" +#endif + +#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2) +# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size" +#endif + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + +struct lm3s_ssidev_s +{ + const struct spi_ops_s *ops; /* Common SPI operations */ +#ifndef CONFIG_SSI_POLLWAIT + sem_t xfrsem; /* Wait for transfer to complete */ +#endif + + /* These following are the source and destination buffers of the transfer. + * they are retained in this structure so that they will be accessible + * from an interrupt handler. The actual type of the buffer is uint8_t if + * nbits <=8 and uint16_t if nbits >8. + */ + + void *txbuffer; /* Source buffer */ + void *rxbuffer; /* Destination buffer */ + + /* These are functions pointers that are configured to perform the + * appropriate transfer for the particular kind of exchange that is + * occurring. Differnt functions may be selected depending on (1) + * if the tx or txbuffer is NULL and depending on the number of bits + * per word. + */ + + void (*txword)(struct lm3s_ssidev_s *priv); + void (*rxword)(struct lm3s_ssidev_s *priv); + +#if NSSI_ENABLED > 1 + uint32_t base; /* SSI register base address */ +#endif + + int ntxwords; /* Number of words left to transfer on the Tx FIFO */ + int nrxwords; /* Number of words received on the Rx FIFO */ + int nwords; /* Number of words to be exchanged */ + uint8_t nbits; /* Current number of bits per word */ + +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + uint8_t irq; /* SSI IRQ number */ +#endif + + /* If there is more than one device on the SPI bus, then we have to enforce + * mutual exclusion and remember some configuration settings to reduce the + * overhead of constant SPI re-configuration. + */ + +#ifndef CONFIG_SPI_OWNBUS + sem_t exclsem; /* For exclusive access to the SSI bus */ + uint32_t frequency; /* Current desired SCLK frequency */ + uint32_t actual; /* Current actual SCLK frequency */ + uint8_t mode; /* Current mode 0,1,2,3 */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SSI register access */ + +static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, + unsigned int offset); +static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, + uint32_t value); + +/* Misc helpers */ + +static uint32_t ssi_disable(struct lm3s_ssidev_s *priv); +static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable); + +#ifndef CONFIG_SSI_POLLWAIT +static void ssi_semtake(sem_t *sem); +#define ssi_semgive(s) sem_post(s); +#endif + +/* SSI data transfer */ + +static void ssi_txnull(struct lm3s_ssidev_s *priv); +static void ssi_txuint16(struct lm3s_ssidev_s *priv); +static void ssi_txuint8(struct lm3s_ssidev_s *priv); +static void ssi_rxnull(struct lm3s_ssidev_s *priv); +static void ssi_rxuint16(struct lm3s_ssidev_s *priv); +static void ssi_rxuint8(struct lm3s_ssidev_s *priv); +static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv); +static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv); +#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) +static inline int ssi_performtx(struct lm3s_ssidev_s *priv); +#else +static int ssi_performtx(struct lm3s_ssidev_s *priv); +#endif +static inline void ssi_performrx(struct lm3s_ssidev_s *priv); +static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords); + +/* Interrupt handling */ + +#ifndef CONFIG_SSI_POLLWAIT +static inline struct lm3s_ssidev_s *ssi_mapirq(int irq); +static int ssi_interrupt(int irq, void *context); +#endif + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int ssi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, + uint32_t frequency); +static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, + enum spi_mode_e mode); +static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits); +static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd); +#ifdef CONFIG_SPI_EXCHANGE +static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); +#else +static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords); +static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Common SSI operations */ + +static const struct spi_ops_s g_spiops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = ssi_lock, +#endif + .select = lm3s_spiselect, /* Provided externally by board logic */ + .setfrequency = ssi_setfrequency, + .setmode = ssi_setmode, + .setbits = ssi_setbits, + .status = lm3s_spistatus, /* Provided externally by board logic */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lm3s_spicmddata, +#endif + .send = ssi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = ssi_exchange, +#else + .sndblock = ssi_sndblock, + .recvblock = ssi_recvblock, +#endif +}; + +/* This supports is up to two SSI busses/ports */ + +static struct lm3s_ssidev_s g_ssidev[] = +{ +#ifndef CONFIG_SSI0_DISABLE + { + .ops = &g_spiops, +#if NSSI_ENABLED > 1 + .base = LM3S_SSI0_BASE, +#endif +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + .irq = LM3S_IRQ_SSI0, +#endif + }, +#endif +#ifndef CONFIG_SSI1_DISABLE + { + .ops = &g_spiops, +#if NSSI_ENABLED > 1 + .base = LM3S_SSI1_BASE, +#endif +#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1 + .irq = LM3S_IRQ_SSI1, +#endif + }, +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ssi_getreg + * + * Description: + * Read the SSI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SSI register from the register base address + * + * Returned Value: + * Value of the register at this offset + * + ****************************************************************************/ + +static inline uint32_t ssi_getreg(struct lm3s_ssidev_s *priv, unsigned int offset) +{ +#if NSSI_ENABLED > 1 + return getreg32(priv->base + offset); +#else + return getreg32(SSI_BASE + offset); +#endif +} + +/**************************************************************************** + * Name: ssi_putreg + * + * Description: + * Write the value to the SSI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SSI register from the register base address + * value - Value to write + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ssi_putreg(struct lm3s_ssidev_s *priv, unsigned int offset, uint32_t value) +{ +#if NSSI_ENABLED > 1 + putreg32(value, priv->base + offset); +#else + putreg32(value, SSI_BASE + offset); +#endif +} + +/**************************************************************************** + * Name: ssi_disable + * + * Description: + * Disable SSI operation. NOTE: The SSI must be disabled before any control + * registers can be re-programmed. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * State of the SSI before the SSE was disabled + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static uint32_t ssi_disable(struct lm3s_ssidev_s *priv) +{ + uint32_t retval; + uint32_t regval; + + retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + regval = (retval & ~SSI_CR1_SSE); + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssivdbg("CR1: %08x\n", regval); + return retval; +} + +/**************************************************************************** + * Name: ssi_enable + * + * Description: + * Restore the SSI operational state + * + * Input Parameters: + * priv - Device-specific state data + * enable - The previous operational state + * + * Returned Value: + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_enable(struct lm3s_ssidev_s *priv, uint32_t enable) +{ + uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET); + regval &= ~SSI_CR1_SSE; + regval |= (enable & SSI_CR1_SSE); + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval); + ssivdbg("CR1: %08x\n", regval); +} + +/**************************************************************************** + * Name: ssi_semtake + * + * Description: + * Wait for a semaphore (handling interruption by signals); + * + * Input Parameters: + * priv - Device-specific state data + * enable - The previous operational state + * + * Returned Value: + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static void ssi_semtake(sem_t *sem) +{ + int ret; + do + { + ret = sem_wait(sem); + } + while (ret < 0 && errno == EINTR); + DEBUGASSERT(ret == 0); +} +#endif + +/**************************************************************************** + * Name: ssi_txnull, ssi_txuint16, and ssi_txuint8 + * + * Description: + * Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer + * pointer appropriately. The selected function dependes on (1) if there + * is a source txbuffer provided, and (2) if the number of bits per + * word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssi_txnull(struct lm3s_ssidev_s *priv) +{ + ssivdbg("TX: ->0xffff\n"); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff); +} + +static void ssi_txuint16(struct lm3s_ssidev_s *priv) +{ + uint16_t *ptr = (uint16_t*)priv->txbuffer; + ssivdbg("TX: %p->%04x\n", ptr, *ptr); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + priv->txbuffer = (void*)ptr; +} + +static void ssi_txuint8(struct lm3s_ssidev_s *priv) +{ + uint8_t *ptr = (uint8_t*)priv->txbuffer; + ssivdbg("TX: %p->%02x\n", ptr, *ptr); + ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++)); + priv->txbuffer = (void*)ptr; +} + +/**************************************************************************** + * Name: ssi_rxnull, ssi_rxuint16, and ssi_rxuint8 + * + * Description: + * Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the + * user rxvbuffer and update the rxbuffer pointer appropriately. The + * selected function dependes on (1) if there is a desination rxbuffer + * provided, and (2) if the number of bits per word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssi_rxnull(struct lm3s_ssidev_s *priv) +{ +#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE) + uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: discard %04x\n", regval); +#else + (void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); +#endif +} + +static void ssi_rxuint16(struct lm3s_ssidev_s *priv) +{ + uint16_t *ptr = (uint16_t*)priv->rxbuffer; + *ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: %p<-%04x\n", ptr, *ptr); + priv->rxbuffer = (void*)(++ptr); +} + +static void ssi_rxuint8(struct lm3s_ssidev_s *priv) +{ + uint8_t *ptr = (uint8_t*)priv->rxbuffer; + *ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET); + ssivdbg("RX: %p<-%02x\n", ptr, *ptr); + priv->rxbuffer = (void*)(++ptr); +} + +/**************************************************************************** + * Name: ssi_txfifofull + * + * Description: + * Return true if the Tx FIFO is full + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: Not full + * + ****************************************************************************/ + +static inline bool ssi_txfifofull(struct lm3s_ssidev_s *priv) +{ + return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0; +} + +/**************************************************************************** + * Name: ssi_rxfifoempty + * + * Description: + * Return true if the Rx FIFO is empty + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: Not empty + * + ****************************************************************************/ + +static inline bool ssi_rxfifoempty(struct lm3s_ssidev_s *priv) +{ + return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0; +} + +/**************************************************************************** + * Name: ssi_performtx + * + * Description: + * If the Tx FIFO is empty, then transfer as many words as we can to + * the FIFO. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * The number of words written to the Tx FIFO (a value from 0 to 8, + * inclusive). + * + ****************************************************************************/ + +#if CONFIG_SSI_TXLIMIT == 1 && defined(CONFIG_SSI_POLLWAIT) +static inline int ssi_performtx(struct lm3s_ssidev_s *priv) +{ + /* Check if the Tx FIFO is full and more data to transfer */ + + if (!ssi_txfifofull(priv) && priv->ntxwords > 0) + { + /* Transfer one word to the Tx FIFO */ + + priv->txword(priv); + priv->ntxwords--; + return 1; + } + return 0; +} + +#else /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ + +static int ssi_performtx(struct lm3s_ssidev_s *priv) +{ +#ifndef CONFIG_SSI_POLLWAIT + uint32_t regval; +#endif + int ntxd = 0; /* Number of words written to Tx FIFO */ + + /* Check if the Tx FIFO is full */ + + if (!ssi_txfifofull(priv)) + { + /* Not full.. Check if all of the Tx words have been sent */ + + if (priv->ntxwords > 0) + { + /* No.. Transfer more words until either the Tx FIFO is full or + * until all of the user provided data has been sent. + */ +#ifdef CONFIG_SSI_TXLIMIT + /* Further limit the number of words that we put into the Tx + * FIFO to CONFIG_SSI_TXLIMIT. Otherwise, we could + * overrun the Rx FIFO on a very fast SSI bus. + */ + for (; ntxd < priv->ntxwords && ntxd < CONFIG_SSI_TXLIMIT && !ssi_txfifofull(priv); ntxd++) +#else + for (; ntxd < priv->ntxwords && !ssi_txfifofull(priv); ntxd++) +#endif + { + priv->txword(priv); + } + + /* Update the count of words to to transferred */ + + priv->ntxwords -= ntxd; + } + + /* Check again... Now have all of the Tx words been sent? */ + +#ifndef CONFIG_SSI_POLLWAIT + regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + if (priv->ntxwords > 0) + { + /* No.. Enable the Tx FIFO interrupt. This interrupt occurs + * when the Tx FIFO is 1/2 full or less. + */ + +#ifdef CONFIG_DEBUG + regval |= (SSI_IM_TX|SSI_RIS_ROR); +#else + regval |= SSI_IM_TX; +#endif + } + else + { + /* Yes.. Disable the Tx FIFO interrupt. The final stages of + * the transfer will be driven by Rx FIFO interrupts. + */ + + regval &= ~(SSI_IM_TX|SSI_RIS_ROR); + } + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); +#endif /* CONFIG_SSI_POLLWAIT */ + } + return ntxd; +} + +#endif /* CONFIG_SSI_TXLIMIT == 1 CONFIG_SSI_POLLWAIT */ + +/**************************************************************************** + * Name: ssi_performrx + * + * Description: + * Transfer as many bytes as possible from the Rx FIFO to the user Rx + * buffer (if one was provided). + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ssi_performrx(struct lm3s_ssidev_s *priv) +{ +#ifndef CONFIG_SSI_POLLWAIT + uint32_t regval; +#endif + + /* Loop while data is available in the Rx FIFO */ + + while (!ssi_rxfifoempty(priv)) + { + /* Have all of the requested words been transferred from the Rx FIFO? */ + + if (priv->nrxwords < priv->nwords) + { + /* No.. Read more data from Rx FIFO */ + + priv->rxword(priv); + priv->nrxwords++; + } + } + + /* The Rx FIFO is now empty. While there is Tx data to be sent, the + * transfer will be driven by Tx FIFO interrupts. The final part + * of the transfer is driven by Rx FIFO interrupts only. + */ + +#ifndef CONFIG_SSI_POLLWAIT + regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET); + if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords) + { + /* There are no more outgoing words to send, but there are + * additional incoming words expected (I would think that this + * a real corner case, be we will handle it with an extra + * interrupt, probably an Rx timeout). + */ + +#ifdef CONFIG_DEBUG + regval |= (SSI_IM_RX|SSI_IM_RT|SSI_IM_ROR); +#else + regval |= (SSI_IM_RX|SSI_IM_RT); +#endif + } + else + { + /* No.. there are either more Tx words to send or all Rx words + * have received. Disable Rx FIFO interrupts. + */ + + regval &= ~(SSI_IM_RX|SSI_IM_RT); + } + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval); +#endif /* CONFIG_SSI_POLLWAIT */ +} + +/**************************************************************************** + * Name: ssi_transfer + * + * Description: + * Exchange a block data with the SPI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static int ssi_transfer(struct lm3s_ssidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords) +{ +#ifndef CONFIG_SSI_POLLWAIT + irqstate_t flags; +#endif + int ntxd; + + ssidbg("txbuffer: %p rxbuffer: %p nwords: %d\n", txbuffer, rxbuffer, nwords); + + /* Set up to perform the transfer */ + + priv->txbuffer = (uint8_t*)txbuffer; /* Source buffer */ + priv->rxbuffer = (uint8_t*)rxbuffer; /* Destination buffer */ + priv->ntxwords = nwords; /* Number of words left to send */ + priv->nrxwords = 0; /* Number of words received */ + priv->nwords = nwords; /* Total number of exchanges */ + + /* Set up the low-level data transfer function pointers */ + + if (priv->nbits > 8) + { + priv->txword = ssi_txuint16; + priv->rxword = ssi_rxuint16; + } + else + { + priv->txword = ssi_txuint8; + priv->rxword = ssi_rxuint8; + } + + if (!txbuffer) + { + priv->txword = ssi_txnull; + } + + if (!rxbuffer) + { + priv->rxword = ssi_rxnull; + } + + /* Prime the Tx FIFO to start the sequence (saves one interrupt). + * At this point, all SSI interrupts should be disabled, but the + * operation of ssi_performtx() will set up the interrupts + * approapriately (if nwords > TxFIFO size). + */ + +#ifndef CONFIG_SSI_POLLWAIT + flags = irqsave(); + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + + ntxd = ssi_performtx(priv); + + /* For the case where nwords < Tx FIFO size, ssi_performrx will + * configure interrupts correctly for the final phase of the + * the transfer. + */ + + ssi_performrx(priv); + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET), + ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + + /* Wait for the transfer to complete. Since there is no handshake + * with SPI, the following should complete even if there are problems + * with the transfer, so it should be safe with no timeout. + */ + + ssivdbg("Waiting for transfer complete\n"); + irqrestore(flags); + do + { + ssi_semtake(&priv->xfrsem); + } + while (priv->nrxwords < priv->nwords); + ssidbg("Transfer complete\n"); + +#else + /* Perform the transfer using polling logic. This will totally + * dominate the CPU until the transfer is complete. Only recommended + * if (1) your SPI is very fast, and (2) if you only use very short + * transfers. + */ + + do + { + /* Handle outgoing Tx FIFO transfers */ + + ntxd = ssi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + ssi_performrx(priv); + + /* If there are other threads at this same priority level, + * the following may help: + */ + + sched_yield(); + } + while (priv->nrxwords < priv->nwords); +#endif + return OK; +} + +/**************************************************************************** + * Name: ssi_mapirq + * + * Description: + * Map an IRQ number into the appropriate SSI device + * + * Input Parameters: + * irq - The IRQ number to be mapped + * + * Returned Value: + * On success, a reference to the private data structgure for this IRQ. + * NULL on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static inline struct lm3s_ssidev_s *ssi_mapirq(int irq) +{ + switch (irq) + { +#ifndef CONFIG_SSI0_DISABLE + case LM3S_IRQ_SSI0: + return &g_ssidev[SSI0_NDX]; +#endif +#ifndef CONFIG_SSI1_DISABLE + case LM3S_IRQ_SSI1: + return &g_ssidev[SSI1_NDX]; +#endif + default: + return NULL; + } +} +#endif + +/**************************************************************************** + * Name: ssi_interrupt + * + * Description: + * Exchange a block data with the SSI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + ****************************************************************************/ + +#ifndef CONFIG_SSI_POLLWAIT +static int ssi_interrupt(int irq, void *context) +{ + struct lm3s_ssidev_s *priv = ssi_mapirq(irq); + uint32_t regval; + int ntxd; + + DEBUGASSERT(priv != NULL); + + /* Clear pending interrupts */ + + regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET); + ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval); + + /* Check for Rx FIFO overruns */ + +#ifdef CONFIG_DEBUG + if ((regval & SSI_RIS_ROR) != 0) + { + lldbg("Rx FIFO Overrun!\n"); + } +#endif + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET)); + + /* Handle outgoing Tx FIFO transfers */ + + ntxd = ssi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + ssi_performrx(priv); + + ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n", + priv->ntxwords, priv->nrxwords, priv->nwords, + ssi_getreg(priv, LM3S_SSI_SR_OFFSET), + ssi_getreg(priv, LM3S_SSI_IM_OFFSET)); + + /* Check if the transfer is complete */ + + if (priv->nrxwords >= priv->nwords) + { + /* Yes.. Disable all SSI interrupt sources */ + + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + + /* Wake up the waiting thread */ + + ssidbg("Transfer complete\n"); + ssi_semgive(&priv->xfrsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int ssi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct lm3s_ssidev_s *priv = (FAR struct lm3s_ssidev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static uint32_t ssi_setfrequencyinternal(struct lm3s_ssidev_s *priv, uint32_t frequency) +{ + uint32_t maxdvsr; + uint32_t cpsdvsr; + uint32_t regval; + uint32_t scr; + uint32_t actual; + + ssidbg("frequency: %d\n", frequency); + DEBUGASSERT(frequency); + + /* Has the frequency changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (frequency != priv->frequency) + { +#endif + /* "The serial bit rate is derived by dividing down the input clock + * (FSysClk). The clock is first divided by an even prescale value + * CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale + * (SSI_CPSR) register ... The clock is further divided by a value + * from 1 to 256, which is 1 + SCR, where SCR is the value programmed + * i n the SSI Control0 (SSICR0) register ... + * + * "The frequency of the output clock SSIClk is defined by: + * + * "SSIClk = FSysClk / (CPSDVSR * (1 + SCR)) + * + * "Note: Although the SSIClk transmit clock can theoretically be 25 MHz, + * the module may not be able to operate at that speed. For master mode, + * the system clock must be at least two times faster than the SSIClk. + * For slave mode, the system clock must be at least 12 times faster + * than the SSIClk." + */ + + if (frequency > SYSCLK_FREQUENCY/2) + { + frequency = SYSCLK_FREQUENCY/2; + } + + /* Find optimal values for CPSDVSR and SCR. This loop is inefficient, + * but should not have to execute many times. + * + * EXAMPLE 1: SYSCLK_FREQUENCY=50,000,0000 and frequency=400,000. + * + * maxcvsr = 125 + * 1. cpsdvsr = 2, scr = 61 -> DONE + * + * This would correspond to an actual frequency of: + * 50,000,000 / (2 * (62)) = 403,226 + * + * EXAMPLE 2: SYSCLK_FREQUENCY=50,000,0000 and frequency=25,000,000. + * + * maxcvsr = 2 + * 1. cpsdvsr = 2, scr = 0 -> DONE + * + * This would correspond to an actual frequency of: + * 50,000,000 / (2 * (1)) = 25,000,000 + */ + + maxdvsr = SYSCLK_FREQUENCY / frequency; + cpsdvsr = 0; + do + { + cpsdvsr += 2; + scr = (maxdvsr / cpsdvsr) - 1; + } + while (scr > 255); + + /* Set CPDVSR */ + + DEBUGASSERT(cpsdvsr < 255); + ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr); + + /* Set SCR */ + + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~SSI_CR0_SCR_MASK; + regval |= (scr << SSI_CR0_SCR_SHIFT); + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr); + + /* Calcluate the actual frequency */ + + actual = SYSCLK_FREQUENCY / (cpsdvsr * (scr + 1)); + + /* Save the frequency selection so that subsequent reconfigurations will be + * faster. + */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; + } + return priv->actual; +#else + return actual; +#endif +} + +static uint32_t ssi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + uint32_t enable; + uint32_t actual; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + actual = ssi_setfrequencyinternal(priv, frequency); + ssi_enable(priv, enable); + return actual; +} + +/**************************************************************************** + * Name: ssi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_setmodeinternal(struct lm3s_ssidev_s *priv, enum spi_mode_e mode) +{ + uint32_t modebits; + uint32_t regval; + + ssidbg("mode: %d\n", mode); + DEBUGASSERT(priv); + + /* Has the number of bits per word changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Select the CTL register bits based on the selected mode */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + modebits = 0; + break; + + case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + modebits = SSI_CR0_SPH; + break; + + case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + modebits = SSI_CR0_SPO; + break; + + case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + modebits = SSI_CR0_SPH|SSI_CR0_SPO; + break; + + default: + return; + } + + /* Then set the selected mode: Freescale SPI format, mode0-3 */ + + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO); + regval |= modebits; + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x\n", regval); + + /* Save the mode so that subsequent re-configuratins will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +static void ssi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + uint32_t enable; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + ssi_setmodeinternal(priv, mode); + ssi_enable(priv, enable); +} + +/**************************************************************************** + * Name: ssi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + * Assumption: + * Caller holds a lock on the SPI bus (if CONFIG_SPI_OWNBUS not defined) + * + ****************************************************************************/ + +static void ssi_setbitsinternal(struct lm3s_ssidev_s *priv, int nbits) +{ + uint32_t regval; + + ssidbg("nbits: %d\n", nbits); + DEBUGASSERT(priv); + if (nbits != priv->nbits && nbits >=4 && nbits <= 16) + { + regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET); + regval &= ~SSI_CR0_DSS_MASK; + regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT); + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval); + ssivdbg("CR0: %08x\n", regval); + + priv->nbits = nbits; + } +} + +static void ssi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + uint32_t enable; + + /* NOTE that the SSI must be disabled when setting any configuration registers. */ + + enable = ssi_disable(priv); + ssi_setbitsinternal(priv, nbits); + ssi_enable(priv, enable); +} + +/**************************************************************************** + * Name: ssi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t ssi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s*)dev; + uint16_t response = 0; + + (void)ssi_transfer(priv, &wd, &response, 1); + return response; +} + +/**************************************************************************** + * Name: SPI_EXCHANGE + * + * Description: + * Exahange a block of data from SPI. Required. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_EXCHANGE +static void ssi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + (void)ssi_transfer(priv, txbuffer, rxbuffer, nwords); +} +#endif + +/************************************************************************* + * Name: ssi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void ssi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + (void)ssi_transfer(priv, buffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: ssi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void ssi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +{ + struct lm3s_ssidev_s *priv = (struct lm3s_ssidev_s *)dev; + (void)ssi_transfer(priv, NULL, buffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize common parts the selected SPI port. Initialization of + * chip select GPIOs must have been performed by board specific logic + * prior to calling this function. Specifically: GPIOs should have + * been configured for output, and all chip selects disabled. + * + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, + * If multiple devices on on the bus, then multiple chip selects will be + * required. Theregore, all GPIO chip management is deferred to board- + * specific logic. + * + * Input Parameter: + * Port number (for hardware that has mutiple SSI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *up_spiinitialize(int port) +{ + struct lm3s_ssidev_s *priv; + irqstate_t flags; + uint8_t regval; + + ssidbg("port: %d\n", port); + + /* Set up for the selected port */ + + flags = irqsave(); + switch (port) + { +#ifndef CONFIG_SSI0_DISABLE + case 0: + /* Select SSI0 */ + + priv = &g_ssidev[SSI0_NDX]; + + /* Enable the SSI0 peripheral */ + + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_SSI0; + putreg32(regval, LM3S_SYSCON_RCGC1); + ssivdbg("RCGC1: %08x\n", regval); + + /* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the + * logic in this file makes no assumptions about chip select) + */ + + lm3s_configgpio(GPIO_SSI0_CLK); /* PA2: SSI0 clock (SSI0Clk) */ + /* lm3s_configgpio(GPIO_SSI0_FSS); PA3: SSI0 frame (SSI0Fss) */ + lm3s_configgpio(GPIO_SSI0_RX); /* PA4: SSI0 receive (SSI0Rx) */ + lm3s_configgpio(GPIO_SSI0_TX); /* PA5: SSI0 transmit (SSI0Tx) */ + break; +#endif /* CONFIG_SSI0_DISABLE */ + +#ifndef CONFIG_SSI1_DISABLE + case 1: + /* Select SSI0 */ + + priv = &g_ssidev[SSI1_NDX]; + + /* Enable the SSI1 peripheral */ + + regval = getreg32(LM3S_SYSCON_RCGC1); + regval |= SYSCON_RCGC1_SSI1; + putreg32(regval, LM3S_SYSCON_RCGC1); + ssivdbg("RCGC1: %08x\n", regval); + + /* Configure SSI1 GPIOs */ + + lm3s_configgpio(GPIO_SSI1_CLK); /* PE0: SSI1 clock (SSI1Clk) */ + /* lm3s_configgpio(GPIO_SSI1_FSS); PE1: SSI1 frame (SSI1Fss) */ + lm3s_configgpio(GPIO_SSI1_RX); /* PE2: SSI1 receive (SSI1Rx) */ + lm3s_configgpio(GPIO_SSI1_TX); /* PE3: SSI1 transmit (SSI1Tx) */ + break; +#endif /* CONFIG_SSI1_DISABLE */ + + default: + irqrestore(flags); + return NULL; + } + + /* Initialize the state structure */ + +#ifndef CONFIG_SSI_POLLWAIT + sem_init(&priv->xfrsem, 0, 0); +#endif +#ifndef CONFIG_SPI_OWNBUS + sem_init(&priv->exclsem, 0, 1); +#endif + + /* Set all CR1 fields to reset state. This will be master mode. */ + + ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0); + + /* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */ + + ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0); + + /* Set the initial mode to mode 0. The application may override + * this initial setting using the setmode() method. + */ + + ssi_setmodeinternal(priv, SPIDEV_MODE0); + + /* Set the initial data width to 8-bits. The application may + * override this initial setting using the setbits() method. + */ + + ssi_setbitsinternal(priv, 8); + + /* Pick some initialize clock frequency. 400,000Hz is the startup + * MMC/SD frequency used for card detection. The application may + * override this setting using the setfrequency() method. + */ + + ssi_setfrequencyinternal(priv, 400000); + + /* Disable all SSI interrupt sources. They will be enabled only + * while there is an SSI transfer in progress. + */ + + ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0); + + /* Attach the interrupt */ + +#ifndef CONFIG_SSI_POLLWAIT +#if NSSI_ENABLED > 1 + irq_attach(priv->irq, (xcpt_t)ssi_interrupt); +#else + irq_attach(SSI_IRQ, (xcpt_t)ssi_interrupt); +#endif +#endif /* CONFIG_SSI_POLLWAIT */ + + /* Enable the SSI for operation */ + + ssi_enable(priv, SSI_CR1_SSE); + + /* Enable SSI interrupts (They are still disabled at the source). */ + +#ifndef CONFIG_SSI_POLLWAIT +#if NSSI_ENABLED > 1 + up_enable_irq(priv->irq); +#else + up_enable_irq(SSI_IRQ); +#endif +#endif /* CONFIG_SSI_POLLWAIT */ + + irqrestore(flags); + return (FAR struct spi_dev_s *)priv; +} + +#endif /* NSSI_ENABLED > 0 */ diff --git a/nuttx/arch/arm/src/lm/lm3s_start.c b/nuttx/arch/arm/src/lm/lm3s_start.c new file mode 100644 index 000000000..4dfe92844 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_start.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_start.c + * arch/arm/src/chip/lm3s_start.c + * + * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <assert.h> +#include <debug.h> + +#include <nuttx/init.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "up_internal.h" + +#include "lm_lowputc.h" +#include "lm_syscontrol.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern void lm3s_vectors(void); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Configure the uart so that we can get debug output as soon as possible */ + + up_clockconfig(); + up_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + showprogress('B'); + + /* Move the intialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + showprogress('C'); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + showprogress('D'); + + /* Initialize onboard resources */ + + lm3s_boardinitialize(); + showprogress('E'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + os_start(); + + /* Shoulnd't get here */ + + for(;;); +} diff --git a/nuttx/arch/arm/src/lm/lm3s_syscontrol.c b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c new file mode 100644 index 000000000..87545bec7 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_syscontrol.c @@ -0,0 +1,315 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_syscontrol.c + * arch/arm/src/chip/lm3s_syscontrol.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <assert.h> +#include <debug.h> + +#include <nuttx/init.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "up_internal.h" +#include "chip.h" +#include "lm_syscontrol.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RCC_OSCMASK (SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) +#define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK|SYSCON_RCC_OSCSRC_MASK|SYSCON_RCC_PWRDN) +#define RCC2_XTALMASK (SYSCON_RCC2_USERCC2|SYSCON_RCC2_OSCSRC2_MASK|SYSCON_RCC2_PWRDN2) +#define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK|SYSCON_RCC_USESYSDIV|SYSCON_RCC_IOSCDIS|SYSCON_RCC_MOSCDIS) +#define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2_MASK) +#define FAST_OSCDELAY (512*1024) +#define SLOW_OSCDELAY (4*1024) +#define PLLLOCK_DELAY (32*1024) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_delay + * + * Description: + * Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + * + ****************************************************************************/ + +static inline void lm3s_delay(uint32_t delay) +{ + __asm__ __volatile__("1:\n" + "\tsubs %0, #1\n" + "\tbne 1b\n" + : "=r"(delay) : "r"(delay)); +} + +/**************************************************************************** + * Name: lm3s_oscdelay + * + * Description: + * Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + * + ****************************************************************************/ + +static inline void lm3s_oscdelay(uint32_t rcc, uint32_t rcc2) +{ + /* Wait for the oscillator to stabilize. A smaller delay is used if the + * current clock rate is very slow. + */ + + uint32_t delay = FAST_OSCDELAY; + + /* Are we currently using RCC2? */ + + if ((rcc2 & SYSCON_RCC2_USERCC2) != 0) + { + uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK; + if ((rcc2src == SYSCON_RCC2_OSCSRC2_30KHZ) || + (rcc2src == SYSCON_RCC2_OSCSRC2_32KHZ)) + { + delay = SLOW_OSCDELAY; + } + } + + /* No.. using srce in RCC */ + + else + { + uint32_t rccsrc = rcc & SYSCON_RCC_OSCSRC_MASK; + if (rccsrc == SYSCON_RCC_OSCSRC_30KHZ) + { + delay = SLOW_OSCDELAY; + } + } + + /* Then delay that number of loops */ + + lm3s_delay(delay); +} + +/**************************************************************************** + * Name: lm3s_plllock + * + * Description: + * The new RCC values have been selected... wait for the PLL to lock on + * + ****************************************************************************/ + +static inline void lm3s_plllock(void) +{ + volatile uint32_t delay; + + /* Loop until the lock is achieved or until a timeout occurs */ + + for (delay = PLLLOCK_DELAY; delay > 0; delay--) + { + /* Check if the PLL is locked on */ + + if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0) + { + /* Yes.. return now */ + + return; + } + } + + /* If we get here, then PLL lock was not achieved */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_clockconfig + * + * Description: + * Called to change to new clock based on desired rcc and rcc2 settings. + * This is use to set up the initial clocking but can be used later to + * support slow clocked, low power consumption modes. + * + ****************************************************************************/ + +void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2) +{ + uint32_t rcc; + uint32_t rcc2; + + /* Get the current values of the RCC and RCC2 registers */ + + rcc = getreg32(LM3S_SYSCON_RCC); + rcc2 = getreg32(LM3S_SYSCON_RCC2); + + /* Temporarily bypass the PLL and system clock dividers */ + + rcc |= SYSCON_RCC_BYPASS; + rcc &= ~(SYSCON_RCC_USESYSDIV); + putreg32(rcc, LM3S_SYSCON_RCC); + + rcc2 |= SYSCON_RCC2_BYPASS2; + putreg32(rcc2, LM3S_SYSCON_RCC2); + + /* We are probably using the main oscillator. The main oscillator is disabled on + * reset and so probably must be enabled here. The internal oscillator is enabled + * on rest and if that is selected, most likely nothing needs to be done. + */ + + if (((rcc & SYSCON_RCC_MOSCDIS) && !(newrcc & SYSCON_RCC_MOSCDIS)) || + ((rcc & SYSCON_RCC_IOSCDIS) && !(newrcc & SYSCON_RCC_IOSCDIS))) + { + /* Enable any selected osciallators (but don't disable any yet) */ + + rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK)); + putreg32(rcc, LM3S_SYSCON_RCC); + + /* Wait for the newly selected oscillator(s) to settle. This is tricky because + * the time that we wait can be significant and is determined by the previous + * clock setting, not the one that we are configuring. + */ + + lm3s_oscdelay(rcc, rcc2); + } + + /* Set the new crystal value, oscillator source and PLL configuration */ + + rcc &= ~RCC_XTALMASK; + rcc |= newrcc & RCC_XTALMASK; + + rcc2 &= ~RCC2_XTALMASK; + rcc2 |= newrcc2 & RCC2_XTALMASK; + + /* Clear the PLL lock interrupt */ + + putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC); + + /* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC + * is currently enabled. + */ + + if (rcc2 & SYSCON_RCC2_USERCC2) + { + putreg32(rcc2, LM3S_SYSCON_RCC2); + putreg32(rcc, LM3S_SYSCON_RCC); + } + else + { + putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM3S_SYSCON_RCC2); + } + + /* Wait for the new crystal value and oscillator source to take effect */ + + lm3s_delay(16); + + /* Set the requested system divider and disable the non-selected osciallators */ + + rcc &= ~RCC_DIVMASK; + rcc |= newrcc & RCC_DIVMASK; + + rcc2 &= ~RCC2_DIVMASK; + rcc2 |= newrcc2 & RCC2_DIVMASK; + + /* Will the PLL output be used to clock the system? */ + + if ((newrcc & SYSCON_RCC_BYPASS) == 0) + { + /* Yes, wail untill the PLL is locked */ + + lm3s_plllock(); + + /* Then enable the PLL */ + + rcc &= ~SYSCON_RCC_BYPASS; + rcc2 &= ~SYSCON_RCC2_BYPASS2; + } + + /* Now we can set the final RCC/RCC2 values */ + + putreg32(rcc, LM3S_SYSCON_RCC); + putreg32(rcc2, LM3S_SYSCON_RCC2); + + /* Wait for the system divider to be effective */ + + lm3s_delay(6); +} + +/**************************************************************************** + * Name: up_clockconfig + * + * Description: + * Called early in the bootsequence (before .data and .bss are available) + * in order to configure initial clocking. + * + ****************************************************************************/ + +void up_clockconfig(void) +{ +#ifdef CONFIG_LM3S_REVA2 + /* Some early silicon returned an increase LDO voltage or 2.75V to work + * around a PLL bug + */ + + putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL); +#endif + + /* Set the clocking to run with the default settings provided in the board.h + * header file + */ + + lm3s_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE); +} + diff --git a/nuttx/arch/arm/src/lm/lm3s_timerisr.c b/nuttx/arch/arm/src/lm/lm3s_timerisr.c new file mode 100644 index 000000000..823d810da --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_timerisr.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/arm/src/lm/lm3s_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <time.h> +#include <debug.h> +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "nvic.h" +#include "clock_internal.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h + * header file. + */ + +#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify taht the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(LM3S_IRQ_SYSTICK); +} diff --git a/nuttx/arch/arm/src/lm/lm3s_vectors.S b/nuttx/arch/arm/src/lm/lm3s_vectors.S new file mode 100644 index 000000000..fe92fc954 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm3s_vectors.S @@ -0,0 +1,805 @@ +/************************************************************************************ + * arch/arm/src/lm/lm3s_vectors.S + * arch/arm/src/chip/lm3s_vectors.S + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <arch/irq.h> + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +/* Memory Map: + * + * 0x0000:0000 - Beginning of FLASH. Address of vectors (if not using bootloader) + * 0x0002:0000 - Address of vectors if using bootloader + * 0x0003:ffff - End of flash + * 0x2000:0000 - Start of SRAM and start of .data (_sdata) + * - End of .data (_edata) abd start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap + * 0x2000:ffff - End of SRAM and end of heap + */ + +#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) + +/* The Cortex-M3 return from interrupt is unusual. We provide the following special + * address to the BX instruction. The particular value also forces a return to + * thread mode and covers state from the main stack point, the MSP (vs. the MSP). + */ + +#define EXC_RETURN 0xfffffff9 + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .globl __start + + .syntax unified + .thumb + .file "lm3s_vectors.S" + +/************************************************************************************ + * Macros + ************************************************************************************/ + +/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3 + * registers on the stack, then branches to an instantantiation of the following + * macro. This macro simply loads the IRQ number into R0, then jumps to the common + * IRQ handling logic. + */ + + .macro HANDLER, label, irqno + .thumb_func +\label: + mov r0, #\irqno + b lm3s_irqcommon + .endm + +/************************************************************************************ + * Vectors + ************************************************************************************/ + + .section .vectors, "ax" + .code 16 + .align 2 + .globl lm3s_vectors + .type lm3s_vectors, function + +lm3s_vectors: + +/* Processor Exceptions */ + + .word IDLE_STACK /* Vector 0: Reset stack pointer */ + .word __start /* Vector 1: Reset vector */ + .word lm3s_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */ + .word lm3s_hardfault /* Vector 3: Hard fault */ + .word lm3s_mpu /* Vector 4: Memory management (MPU) */ + .word lm3s_busfault /* Vector 5: Bus fault */ + .word lm3s_usagefault /* Vector 6: Usage fault */ + .word lm3s_reserved /* Vector 7: Reserved */ + .word lm3s_reserved /* Vector 8: Reserved */ + .word lm3s_reserved /* Vector 9: Reserved */ + .word lm3s_reserved /* Vector 10: Reserved */ + .word lm3s_svcall /* Vector 11: SVC call */ + .word lm3s_dbgmonitor /* Vector 12: Debug monitor */ + .word lm3s_reserved /* Vector 13: Reserved */ + .word lm3s_pendsv /* Vector 14: Pendable system service request */ + .word lm3s_systick /* Vector 15: System tick */ + +/* External Interrupts */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_reserved /* Vector 25: Reserved */ + .word lm3s_reserved /* Vector 26: Reserved */ + .word lm3s_reserved /* Vector 27: Reserved */ + .word lm3s_reserved /* Vector 28: Reserved */ + .word lm3s_reserved /* Vector 29: Reserved */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_gpioh /* Vector 48: GPIO Port H */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_ssi1 /* Vector 50: SSI 1 */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_i2c1 /* Vector 53: I2C 1 */ + .word lm3s_reserved /* Vector 54: Reserved */ + .word lm3s_reserved /* Vector 55: Reserved */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_reserved /* Vector 25: Reserved */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_reserved /* Vector 27: Reserved */ + .word lm3s_reserved /* Vector 28: Reserved */ + .word lm3s_reserved /* Vector 29: Reserved */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_reserved /* Vector 51: Reserved */ + .word lm3s_reserved /* Vector 52: Reserved */ + .word lm3s_reserved /* Vector 53: Reserved */ + .word lm3s_reserved /* Vector 54: Reserved */ + .word lm3s_reserved /* Vector 55: Reserved */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_reserved /* Vector 59: Reserved */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_uart2 /* Vector 49: UART 2 */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_i2c1 /* Vector 53: I2C 1 */ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_reserved /* Vector 55: Reserved */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */ + .word lm3s_cmp2 /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_gpioh /* Vector 48: GPIO Port H */ + .word lm3s_uart2 /* Vector 49: UART 2 */ + .word lm3s_ssi1 /* Vector 50: SSI 1 */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_i2c1 /* Vector 53: I2C 1 */ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_can0 /* Vector 55: CAN 0 */ + .word lm3s_can1 /* Vector 56: CAN 1 */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_reserved /* Vector 59: Reserved */ + .word lm3s_usb /* Vector 60: USB */ + .word lm3s_pwm3 /* Vector 61: PWM 3 */ + .word lm3s_udmasoft /* Vector 62: uDMA Software */ + .word lm3s_udmaerror /* Vector 63: uDMA Error */ + .word lm3s_adc1_0 /* Vector 64: ADC1 Sequence 0 */ + .word lm3s_adc1_1 /* Vector 65: ADC1 Sequence 1 */ + .word lm3s_adc1_2 /* Vector 66: ADC1 Sequence 2 */ + .word lm3s_adc1_3 /* Vector 67: ADC1 Sequence 3 */ + .word lm3s_i2s0 /* Vector 68: I2S 0 */ + .word lm3s_epi /* Vector 69: Reserved */ + .word lm3s_gpioj /* Vector 70: GPIO J */ + .word lm3s_reserved /* Vector 71: Reserved */ + #elif defined(CONFIG_ARCH_CHIP_LM3S8962) + .word lm3s_gpioa /* Vector 16: GPIO Port A */ + .word lm3s_gpiob /* Vector 17: GPIO Port B */ + .word lm3s_gpioc /* Vector 18: GPIO Port C */ + .word lm3s_gpiod /* Vector 19: GPIO Port D */ + .word lm3s_gpioe /* Vector 20: GPIO Port E */ + .word lm3s_uart0 /* Vector 21: UART 0 */ + .word lm3s_uart1 /* Vector 22: UART 1 */ + .word lm3s_ssi0 /* Vector 23: SSI 0 */ + .word lm3s_i2c0 /* Vector 24: I2C 0 */ + .word lm3s_pwmfault /* Vector 25: PWM Fault */ + .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */ + .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */ + .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */ + .word lm3s_qei0 /* Vector 29: QEI0 */ + .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */ + .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */ + .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */ + .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */ + .word lm3s_wdog /* Vector 34: Watchdog Timer */ + .word lm3s_tmr0a /* Vector 35: Timer 0 A */ + .word lm3s_tmr0b /* Vector 36: Timer 0 B */ + .word lm3s_tmr1a /* Vector 37: Timer 1 A */ + .word lm3s_tmr1b /* Vector 38: Timer 1 B */ + .word lm3s_tmr2a /* Vector 39: Timer 2 A */ + .word lm3s_tmr2b /* Vector 40: Timer 3 B */ + .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */ + .word lm3s_reserved /* Vector 42: Reserved */ + .word lm3s_reserved /* Vector 43: Reserved */ + .word lm3s_syscon /* Vector 44: System Control */ + .word lm3s_flashcon /* Vector 45: FLASH Control */ + .word lm3s_gpiof /* Vector 46: GPIO Port F */ + .word lm3s_gpiog /* Vector 47: GPIO Port G */ + .word lm3s_reserved /* Vector 48: Reserved */ + .word lm3s_reserved /* Vector 49: Reserved */ + .word lm3s_reserved /* Vector 50: Reserved */ + .word lm3s_tmr3a /* Vector 51: Timer 3 A */ + .word lm3s_tmr3b /* Vector 52: Timer 3 B */ + .word lm3s_reserved /* Vector 53: Reserved*/ + .word lm3s_qei1 /* Vector 54: QEI1 */ + .word lm3s_can0 /* Vector 55: Can Controller */ + .word lm3s_reserved /* Vector 56: Reserved */ + .word lm3s_reserved /* Vector 57: Reserved */ + .word lm3s_eth /* Vector 58: Ethernet Controller */ + .word lm3s_hib /* Vector 59: Hibernation Module */ + .word lm3s_reserved /* Vector 60: Reserved */ + .word lm3s_reserved /* Vector 61: Reserved */ + .word lm3s_reserved /* Vector 62: Reserved */ + .word lm3s_reserved /* Vector 63: Reserved */ + .word lm3s_reserved /* Vector 64: Reserved */ + .word lm3s_reserved /* Vector 65: Reserved */ + .word lm3s_reserved /* Vector 66: Reserved */ + .word lm3s_reserved /* Vector 67: Reserved */ + .word lm3s_reserved /* Vector 68: Reserved */ + .word lm3s_reserved /* Vector 69: Reserved */ + .word lm3s_reserved /* Vector 70: Reserved */ +#else +# error "Vectors not specified for this LM3S chip" +#endif + .size lm3s_vectors, .-lm3s_vectors + +/************************************************************************************ + * .text + ************************************************************************************/ + + .text + .type handlers, function + .thumb_func +handlers: + HANDLER lm3s_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */ + HANDLER lm3s_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ + HANDLER lm3s_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */ + HANDLER lm3s_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */ + HANDLER lm3s_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */ + HANDLER lm3s_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */ + HANDLER lm3s_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */ + HANDLER lm3s_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */ + HANDLER lm3s_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */ + HANDLER lm3s_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */ + +#if defined(CONFIG_ARCH_CHIP_LM3S6918) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6432) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ +#elif defined(CONFIG_ARCH_CHIP_LM3S6965) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S8962) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) + HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */ + HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */ + HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */ + HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */ + HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */ + HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */ + HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */ + HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */ + HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */ + HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */ + HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */ + HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */ + HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */ + HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */ + HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */ + HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */ + HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */ + HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */ + HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */ + HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */ + HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */ + HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */ + HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */ + HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */ + HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */ + HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */ + HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */ + HANDLER lm3s_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */ + HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */ + HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */ + HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */ + HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */ + HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */ + HANDLER lm3s_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */ + HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */ + HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */ + HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */ + HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */ + HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */ + HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */ + HANDLER lm3s_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */ + HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */ + HANDLER lm3s_usb, LM3S_IRQ_USB /* Vector 60: USB */ + HANDLER lm3s_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */ + HANDLER lm3s_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */ + HANDLER lm3s_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */ + HANDLER lm3s_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */ + HANDLER lm3s_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */ + HANDLER lm3s_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */ + HANDLER lm3s_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */ + HANDLER lm3s_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */ + HANDLER lm3s_epi, LM3S_IRQ_EPI /* Vector 69: EPI */ + HANDLER lm3s_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */ +#else +# error "Vectors not specified for this LM3S chip" +#endif + +/* Common IRQ handling logic. On entry here, the return stack is on either + * the PSP or the MSP and looks like the following: + * + * REG_XPSR + * REG_R15 + * REG_R14 + * REG_R12 + * REG_R3 + * REG_R2 + * REG_R1 + * MSP->REG_R0 + * + * And + * R0 contains the IRQ number + * R14 Contains the EXC_RETURN value + * We are in handler mode and the current SP is the MSP + */ + +lm3s_irqcommon: + + /* Complete the context save */ + +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r2, r14, #3 /* If R14=0xfffffffd, then r2 == 0 */ + ite ne /* Next two instructions are condition */ + mrsne r1, msp /* R1=The main stack pointer */ + mrseq r1, psp /* R1=The process stack pointer */ +#else + mrs r1, msp /* R1=The main stack pointer */ +#endif + + mov r2, r1 /* R2=Copy of the main/process stack pointer */ + add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ + mrs r3, primask /* R3=Current PRIMASK setting */ +#ifdef CONFIG_NUTTX_KERNEL + stmdb r1!, {r2-r11,r14} /* Save the remaining registers plus the SP value */ +#else + stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */ +#endif + + /* Disable interrupts, select the stack to use for interrupt handling + * and call up_doirq to handle the interrupt + */ + + cpsid i /* Disable further interrupts */ + + /* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt + * stack pointer. The way that this is done here prohibits nested interrupts! + * Otherwise, we will re-use the main stack for interrupt level processing. + */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + ldr sp, =g_intstackbase + str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */ +#else + mov sp, r1 /* We are using the main stack pointer */ + bl up_doirq /* R0=IRQ, R1=register save (msp) */ + mov r1, sp /* Recover R1=main stack pointer */ +#endif + + /* On return from up_doirq, R0 will hold a pointer to register context + * array to use for the interrupt return. If that return value is the same + * as current stack pointer, then things are relatively easy. + */ + + cmp r0, r1 /* Context switch? */ + beq 1f /* Branch if no context switch */ + + /* We are returning with a pending context switch. This case is different + * because in this case, the register save structure does not lie on the + * stack but, rather, are within a TCB structure. We'll have to copy some + * values to the stack. + */ + + add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */ + ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */ + ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */ + stmdb r1!, {r4-r11} /* Store eight registers in HW save area */ +#ifdef CONFIG_NUTTX_KERNEL + ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif + b 2f /* Re-join common logic */ + + /* We are returning with no context switch. We simply need to "unwind" + * the same stack frame that we created + */ +1: +#ifdef CONFIG_NUTTX_KERNEL + ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */ +#else + ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */ +#endif +2: +#ifdef CONFIG_NUTTX_KERNEL + /* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1 + * (handler mode) if the state is on the MSP. It can only be on the PSP if + * EXC_RETURN is 0xfffffffd (unprivileged thread) + */ + + adds r0, r14, #3 /* If R14=0xfffffffd, then r0 == 0 */ + ite ne /* Next two instructions are condition */ + msrne msp, r1 /* R1=The main stack pointer */ + msreq psp, r1 /* R1=The process stack pointer */ +#else + msr msp, r1 /* Recover the return MSP value */ + + /* Preload r14 with the special return value first (so that the return + * actually occurs with interrupts still disabled). + */ + + ldr r14, =EXC_RETURN /* Load the special value */ +#endif + + /* Restore the interrupt state */ + + msr primask, r3 /* Restore interrupts */ + + /* Always return with R14 containing the special value that will: (1) + * return to thread mode, and (2) continue to use the MSP + */ + + bx r14 /* And return */ + .size handlers, .-handlers + +/************************************************************************************ + * Name: up_interruptstack/g_intstackbase + * + * Description: + * Shouldn't happen + * + ************************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + .bss + .global g_intstackbase + .align 4 +up_interruptstack: + .skip (CONFIG_ARCH_INTERRUPTSTACK & ~3) +g_intstackbase: + .size up_interruptstack, .-up_interruptstack +#endif + +/************************************************************************************ + * .rodata + ************************************************************************************/ + + .section .rodata, "a" + +/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end + * of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS + * and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that + * the system boots on and, eventually, becomes the idle, do nothing task that runs + * only when there is nothing else to run. The heap continues from there until the + * end of memory. See g_heapbase below. + */ + + .globl g_heapbase + .type g_heapbase, object +g_heapbase: + .long _ebss+CONFIG_IDLETHREAD_STACKSIZE + .size g_heapbase, .-g_heapbase + + .end diff --git a/nuttx/arch/arm/src/lm/lm_ethernet.h b/nuttx/arch/arm/src/lm/lm_ethernet.h new file mode 100644 index 000000000..29fe4fd17 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_ethernet.h @@ -0,0 +1,103 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_ethernet.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_ETHERNET_H +#define __ARCH_ARM_SRC_LM_LM_ETHERNET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +#if LM3S_NETHCONTROLLERS > 1 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Function: lm3s_ethinitialize + * + * Description: + * Initialize the Ethernet driver for one interface. If the LM3S chip + * supports multiple Ethernet controllers, then bould specific logic + * must implement up_netinitialize() and call this function to initialize + * the desiresed interfaces. + * + * Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int lm3s_ethinitialize(int intf); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* LM3S_NETHCONTROLLERS > 1 */ +#endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/lm_gpio.h b/nuttx/arch/arm/src/lm/lm_gpio.h new file mode 100644 index 000000000..9577fd926 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_gpio.h @@ -0,0 +1,223 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_gpio.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_GPIO_H +#define __ARCH_ARM_SRC_LM_LM_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/compiler.h> + +#include <stdint.h> +#include <stdbool.h> + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Bit-encoded input to lm3s_configgpio() *******************************************/ + +/* Encoding: + * FFFS SPPP IIIn nnnn nnnn nnnn VPPP PBBB + * + * These bits set the primary function of the pin: + * FFFn nnnn nnnn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */ +#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */ +#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */ +#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */ +#define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */ +#define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */ +#define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */ +#define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */ +#define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */ +#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */ +#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */ +#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */ +#define GPIO_FUNC_MAX GPIO_FUNC_INTERRUPT + +/* That primary may be modified by the following options + * nnnS SPPP nnnn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_STRENGTH_SHIFT 27 /* Bits 28-27: Pad drive strength */ +#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT) +#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */ +#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */ +#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */ +#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */ +#define GPIO_STRENGTH_MAX GPIO_STRENGTH_8MASC + +#define GPIO_PADTYPE_SHIFT 24 /* Bits 26-24: Pad type */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) +#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */ +#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */ +#define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */ +#define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */ +#define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */ +#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */ +#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */ + +/* If the pin is an interrupt, then the following options apply + * nnnn nnnn IIIn nnnn nnnn nnnn nnnn nnnn + */ + +#define GPIO_INT_SHIFT 21 /* Bits 23-21: Interrupt type */ +#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT) +#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */ +#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */ +#define GPIO_INT_BOTHEDGES (2 << GPIO_INT_SHIFT) /* Interrupt on both edges */ +#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */ +#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */ + +/* If the pin is an GPIO digital output, then this identifies the initial output value: + * nnnn nnnn nnnn nnnn nnnn nnnn Vnnn nnnn + */ + +#define GPIO_VALUE_SHIFT 7 /* Bit 7: If output, inital value of output */ +#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT) +#define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */ +#define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */ + +/* This identifies the GPIO port + * nnnn nnnn nnnn nnnn nnnn nnnn nPPP Pnnn + */ + +#define GPIO_PORT_SHIFT 3 /* Bit 3-6: Port number */ +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ +#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ +#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ +#define GPIO_PORTJ (8 << GPIO_PORT_SHIFT) /* GPIOJ */ + +/* This identifies the bit in the port: + * nnnn nnnn nnnn nnnn nnnn nnnn nnnn nBBB + */ + +#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */ +#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lm3s_configgpio(uint32_t cfgset); + +/**************************************************************************** + * Name: lm3s_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lm3s_gpiowrite(uint32_t pinset, bool value); + +/**************************************************************************** + * Name: lm3s_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lm3s_gpioread(uint32_t pinset, bool value); + +/**************************************************************************** + * Function: lm3s_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lm3s_dumpgpio(uint32_t pinset, const char *msg); + +/**************************************************************************** + * Name: gpio_irqinitialize + * + * Description: + * Initialize all vectors to the unexpected interrupt handler + * + ****************************************************************************/ + +int weak_function gpio_irqinitialize(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/lm_lowputc.h b/nuttx/arch/arm/src/lm/lm_lowputc.h new file mode 100644 index 000000000..b384bbd80 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_lowputc.h @@ -0,0 +1,87 @@ +/************************************************************************************ + * arch/arm/src/lm/lm3s_lowputc.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_LOWPUTC_H +#define __ARCH_ARM_SRC_LM_LM_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization. + * + ****************************************************************************/ + +void up_lowsetup(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_LOWPUTC_H */ diff --git a/nuttx/arch/arm/src/lm/lm_ssi.h b/nuttx/arch/arm/src/lm/lm_ssi.h new file mode 100644 index 000000000..4e7119898 --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_ssi.h @@ -0,0 +1,114 @@ +/************************************************************************************ + * arch/arm/src/lm/lm_ssi.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_SSI_H +#define __ARCH_ARM_SRC_LM_LM_SSI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdbool.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * The external functions, lm3s_spiselect, lm3s_spistatus, and + * lm3s_spicmddata must be provided by board-specific logic. These are + * implementations of the select, status, and cmddata methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * All other methods (including up_spiinitialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in lm3s_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * board-specific logic. These functions will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration, provide + * the lm3s_spicmddata() function in your board-specific logic. This + * functions will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 4. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 5. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; +void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lm3s_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/lm_syscontrol.h b/nuttx/arch/arm/src/lm/lm_syscontrol.h new file mode 100644 index 000000000..79cc2349d --- /dev/null +++ b/nuttx/arch/arm/src/lm/lm_syscontrol.h @@ -0,0 +1,100 @@ +/************************************************************************************ + * arch/arm/src/lm/lm3s_syscontrol.h + * + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H +#define __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lm3s_clockconfig + * + * Description: + * Called to change to new clock based on desired rcc and rcc2 settings. + * This is use to set up the initial clocking but can be used later to + * support slow clocked, low power consumption modes. + * + ****************************************************************************/ + +void lm3s_clockconfig(uint32_t newrcc, uint32_t newrcc2); + +/**************************************************************************** + * Name: up_clockconfig + * + * Description: + * Called early in the bootsequence (before .data and .bss are available) + * in order to configure initial clocking. + * + ****************************************************************************/ + +void up_clockconfig(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LM_LM_SYSCONTROL_H */ |