LPC31: Configuration and build support for a forthcoming USB host driver; configs/ea3131/nsh converted to use kconfig-frontend tools

4 files changed, 91 insertions, 56 deletions

diff --git a/nuttx/arch/arm/src/lpc31xx/Kconfig b/nuttx/arch/arm/src/lpc31xx/Kconfig
index a832c6bfe..831aca7f2 100644
--- a/nuttx/arch/arm/src/lpc31xx/Kconfig
+++ b/nuttx/arch/arm/src/lpc31xx/Kconfig
@@ -40,30 +40,6 @@ config ARCH_CHIP_LPC3154
 
 endchoice # LPC31xx Configuration Options
 
-choice
-	prompt "Toolchain Selection"
-	default LPC31_BUILDROOT if !HOST_WINDOWS
-	default LPC31_CODESOURCERYW if HOST_WINDOWS
-	depends on ARCH_CHIP_LPC31XX
-
-config LPC31_CODESOURCERYW
-	bool "CodeSourcery GNU toolchain under Windows"
-	depends on HOST_WINDOWS
-
-config LPC31_CODESOURCERYL
-	bool "CodeSourcery GNU toolchain under Linux"
-	depends on HOST_LINUX
-
-config LPC31_DEVKITARM
-	bool "devkitARM GNU toolchain"
-	depends on HOST_WINDOWS
-
-config LPC31_BUILDROOT
-	bool "Buildroot"
-	depends on !WINDOWS_NATIVE
-
-endchoice # Toolchain Selection
-
 config LPC31_SDRAMHCLK
 	int "External SDRAM HCLK"
 	depends on LPC31_EXTSDRAM
@@ -81,8 +57,8 @@ config LPC31_SPI
 	bool "SPI"
 	default n
 
-config LPC31_USB
-	bool "USB"
+config LPC31_USBOTG
+	bool "USB OTG"
 	default n
 
 config LPC31_MCI
@@ -215,6 +191,12 @@ endmenu # External Memory Configuration
 menu "LPC31xx UART Configuration"
 	depends on LPC31_UART
 
+config LPC31_UART_PRECALCULATED
+	bool "Use pre-calculated BAD configuration"
+	default n
+
+if LPC31_UART_PRECALCULATED
+
 config LPC31_UART_DIVADDVAL
 	int "BAUD pre-scaler divisor"
 	---help---
@@ -230,20 +212,21 @@ config LPC31_UART_MULVAL
 	---help---
 		BAUD multiplier
 
+endif # LPC31_UART_PRECALCULATED
 endmenu # LPC31xx UART Configuration
 
-menu "USB device driver options"
+if LPC31_USBOTG && USBDEV
+
+menu "USB device controller driver (DCD) options"
 
 config LPC31_USBDEV_EP0_MAXSIZE
 	int "EP0 Max packet size"
-	depends on USBDEV
 	default 64
 	---help---
 		Endpoint 0 maximum packet size.  Default: 64
 
 config LPC31_USBDEV_FRAME_INTERRUPT
 	bool "USB frame interrupt"
-	depends on USBDEV
 	default n
 	---help---
 		Handle USB Start-Of-Frame events.  Enable reading SOF from interrupt
@@ -252,19 +235,61 @@ config LPC31_USBDEV_FRAME_INTERRUPT
 
 config LPC31_USBDEV_DMA
 	bool "Enable USB device DMA"
-	depends on USBDEV
 	default n
 	---help---
 		Enable lpc31xx-specific DMA support
 
 config LPC31_USBDEV_REGDEBUG
 	bool "Register level debug"
-	depends on USBDEV && DEBUG
+	depends on DEBUG
 	default n
 	---help---
 		Output detailed register-level USB device debug information.  Requires also DEBUG.
 
-endmenu # USB device driver options
+endmenu # USB device driver controller (DCD) options
+endif # LPC31_USBOTG && USBDEV
+
+if LPC31_USBOTG && USBHOST
+
+menu "USB host controller driver (HCD) options"
+
+config LPC31_EHCI_NQHS
+	int "Number of Queue Head (QH) structures"
+	default 4
+	---help---
+		Configurable number of Queue Head (QH) structures.  The default is
+		one per Root hub port plus one for EP0 (4).
+
+config LPC31_EHCI_NQTDS
+	int "Number of Queue Element Transfer Descriptor (qTDs)"
+	default 6
+	---help---
+		Configurable number of Queue Element Transfer Descriptor (qTDs).
+		The default is one per root hub plus three from EP0 (6).
+
+config LPC31_EHCI_BUFSIZE
+	int "Size of one request/descriptor buffer"
+	default 128
+	---help---
+		The size of one request/descriptor buffer in bytes.  The TD buffe
+		size must be an even number of 32-bit words and must be large enough
+		to hangle the largest transfer via a SETUP request.
+
+config LPC31_EHCI_PREALLOCATE
+	bool "Preallocate descriptor pool"
+	default y
+	---help---
+		Select this option to pre-allocate EHCI queue and descriptor
+		structure pools in .bss.  Otherwise, these pools will be
+		dynamically allocated using kmemalign().
+
+config LPC31_EHCI_REGDEBUG
+	bool "Enable low-level EHCI register debug"
+	default n
+	depends on DEBUG
+
+endmenu # USB host controller driver (HCD) options
+endif # LPC31_USBOTG && USBHOST
 
 menu "SPI device driver options"
 
diff --git a/nuttx/arch/arm/src/lpc31xx/Make.defs b/nuttx/arch/arm/src/lpc31xx/Make.defs
index f5bdf7a94..005bb784d 100644
--- a/nuttx/arch/arm/src/lpc31xx/Make.defs
+++ b/nuttx/arch/arm/src/lpc31xx/Make.defs
@@ -33,39 +33,47 @@
 #
 ############################################################################
 
-HEAD_ASRC	= up_head.S
+HEAD_ASRC = up_head.S
 
-CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
-		  up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S
-CMN_CSRCS	= up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c \
-		  up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
-		  up_initialize.c up_initialstate.c up_interruptcontext.c \
-		  up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
-		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
-		  up_reprioritizertr.c up_schedulesigaction.c \
-		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
-		  up_undefinedinsn.c up_usestack.c up_vfork.c
+CMN_ASRCS  = up_cache.S up_fullcontextrestore.S up_saveusercontext.S
+CMN_ASRCS += up_vectors.S up_vectoraddrexcptn.S up_vectortab.S vfork.S
+
+CMN_CSRCS  = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
+CMN_CSRCS += up_dataabort.c up_mdelay.c up_udelay.c up_exit.c up_idle.c
+CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
+CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
+CMN_CSRCS += up_prefetchabort.c up_releasepending.c up_releasestack.c
+CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c
+CMN_CSRCS += up_sigdeliver.c up_syscall.c up_unblocktask.c
+CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c
 
 ifeq ($(CONFIG_PAGING),y)
-CMN_CSRCS	+= up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c
+CMN_CSRCS += up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c
 endif
 
 ifeq ($(CONFIG_ELF),y)
 CMN_CSRCS += up_elf.c
 endif
 
-CGU_ASRCS	= 
-CGU_CSRCS	= lpc31_bcrndx.c lpc31_clkdomain.c lpc31_clkexten.c \
-		  lpc31_clkfreq.c lpc31_clkinit.c lpc31_defclk.c \
-		  lpc31_esrndx.c lpc31_fdcndx.c lpc31_fdivinit.c \
-		  lpc31_freqin.c lpc31_pllconfig.c lpc31_resetclks.c \
-		  lpc31_setfreqin.c lpc31_setfdiv.c lpc31_softreset.c
+CGU_ASRCS  =
+
+CGU_CSRCS  = lpc31_bcrndx.c lpc31_clkdomain.c lpc31_clkexten.c
+CGU_CSRCS += lpc31_clkfreq.c lpc31_clkinit.c lpc31_defclk.c
+CGU_CSRCS += lpc31_esrndx.c lpc31_fdcndx.c lpc31_fdivinit.c
+CGU_CSRCS += lpc31_freqin.c lpc31_pllconfig.c lpc31_resetclks.c
+CGU_CSRCS += lpc31_setfreqin.c lpc31_setfdiv.c lpc31_softreset.c
+
+CHIP_ASRCS  = $(CGU_ASRCS)
 
-CHIP_ASRCS	= $(CGU_ASRCS)
-CHIP_CSRCS	= lpc31_allocateheap.c lpc31_boot.c lpc31_decodeirq.c \
-		  lpc31_irq.c lpc31_lowputc.c lpc31_serial.c lpc31_i2c.c \
-		  lpc31_spi.c lpc31_timerisr.c $(CGU_CSRCS)
+CHIP_CSRCS  = lpc31_allocateheap.c lpc31_boot.c lpc31_decodeirq.c
+CHIP_CSRCS += lpc31_irq.c lpc31_lowputc.c lpc31_serial.c lpc31_i2c.c
+CHIP_CSRCS += lpc31_spi.c lpc31_timerisr.c $(CGU_CSRCS)
 
+ifeq ($(CONFIG_LPC31_USBOTG),y)
+ifeq ($(CONFIG_USBHOST),y)
+CHIP_CSRCS += lpc31_ehci.c
+endif
 ifeq ($(CONFIG_USBDEV),y)
-CHIP_CSRCS	+= lpc31_usbdev.c
+CHIP_CSRCS += lpc31_usbdev.c
+endif
 endif
diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c b/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c
index 03f869562..5728570eb 100644
--- a/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c
+++ b/nuttx/arch/arm/src/lpc31xx/lpc31_usbdev.c
@@ -2604,7 +2604,6 @@ void up_usbuninitialize(void)
   lpc31_disableclock (CLKID_USBOTGAHBCLK);
   lpc31_disableclock (CLKID_EVENTROUTERPCLK);
 
-
   irqrestore(flags);
 }
 
@@ -2666,6 +2665,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
 
       lpc31_pullup(&g_usbdev.usbdev, true);
     }
+
   return ret;
 }
 
diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h b/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h
index b98706dfb..cc4e55ec2 100644
--- a/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h
+++ b/nuttx/arch/arm/src/lpc31xx/lpc31_usbotg.h
@@ -47,6 +47,8 @@
  * Pre-processor Definitions
  ************************************************************************************************/
 
+#define LPC31_EHCI_NRHPORT                1      /* There is only a single root hub port */
+
 /* USBOTG register base address offset into the USBOTG domain ***********************************/
 
 #define LPC31_USBOTG_VBASE                (LPC31_USBOTG_VSECTION)