diff options
author | Gregory Nutt <gnutt@nuttx.org> | 2014-10-21 06:36:27 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2014-10-21 06:36:27 -0600 |
commit | 335c898292e5cc3473e713cddd2d39b04dac7849 (patch) | |
tree | 483ab31d2385a17e53cba7de970500d2bd6dc563 /nuttx/arch/arm/src/lpc43xx | |
parent | 2e3978913678eb0bbf7e5156794d779904c240d6 (diff) | |
download | nuttx-335c898292e5cc3473e713cddd2d39b04dac7849.tar.gz nuttx-335c898292e5cc3473e713cddd2d39b04dac7849.tar.bz2 nuttx-335c898292e5cc3473e713cddd2d39b04dac7849.zip |
Fixe to allow compile of lpc43_gpioint.c. It likely doesn't work. From Brandon warhurst_002
Diffstat (limited to 'nuttx/arch/arm/src/lpc43xx')
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c | 41 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 20 |
5 files changed, 31 insertions, 42 deletions
diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h index 6d3bb5d80..a4d0ad7ad 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpio.h @@ -42,6 +42,8 @@ #include <nuttx/config.h> +#include "chip.h" + /**************************************************************************************************** * Pre-processor Definitions ****************************************************************************************************/ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h index d9dfe1ce9..a63fc35bd 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_scu.h @@ -371,7 +371,7 @@ #define SCU_GPIO_PIN31 31 #define SCU_PINTSEL0_SHIFT(n) ((n) << 3) -#define SCU_PINTSEL0_MASK(n) (0xff << SCU_PINTSEL0_SHIFT(n))) +#define SCU_PINTSEL0_MASK(n) (0xff << SCU_PINTSEL0_SHIFT(n)) #define SCU_PINTSEL0_INTPIN_SHIFT(n) ((n) << 3) #define SCU_PINTSEL0_INTPIN_MASK(n) (31 << SCU_PINTSEL0_INTPIN_SHIFT(n)) #define SCU_PINTSEL0_PORTSEL_SHIFT(n) (((n) << 3) + 5) diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c index d33d2dfa9..6de112b2f 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43/lpc43_gpioint.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -34,19 +34,21 @@ ****************************************************************************/ /* GPIO pin interrupts * - * From all available GPIO pins, up to eight pins can be selected in the system - * control block to serve as external interrupt pins. The external interrupt pins - * are connected to eight individual interrupts in the NVIC and are created based - * on rising or falling edges or on the input level on the pin. + * From all available GPIO pins, up to eight pins can be selected in the + * system control block to serve as external interrupt pins. The external + * interrupt pins are connected to eight individual interrupts in the NVIC + * and are created based on rising or falling edges or on the input level + * on the pin. * * GPIO group interrupt * - * For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks - * (GROUP0 and GROUP1), the GPIO grouped interrupt registers determine which pins are - * enabled to generate interrupts and what the active polarities of each of those - * inputs are. The GPIO grouped interrupt registers also select whether the interrupt - * output will be level or edge triggered and whether it will be based on the OR or - * the AND of all of the enabled inputs. + * For each port/pin connected to one of the two the GPIO Grouped Interrupt + * blocks (GROUP0 and GROUP1), the GPIO grouped interrupt registers + * determine which pins are enabled to generate interrupts and what the + * active polarities of each of those inputs are. The GPIO grouped + * interrupt registers also select whether the interrupt output will be + * level or edge triggered and whether it will be based on the OR or the + * AND of all of the enabled inputs. */ /**************************************************************************** @@ -59,8 +61,11 @@ #include <nuttx/arch.h> #include <errno.h> +#include "up_arch.h" #include "chip.h" #include "chip/lpc43_scu.h" +#include "chip/lpc43_gpio.h" +#include "lpc43_gpio.h" #include "lpc43_gpioint.h" #ifdef CONFIG_GPIO_IRQ @@ -144,7 +149,8 @@ int lpc43_gpioint_grpinitialize(int group, bool anded, bool level) { regval |= GRPINT_CTRL_TRIG; } - putreg32(regbal, grpbase + LPC43_GRP1INT_CTRL_OFFSET); + + putreg32(regval, grpbase + LPC43_GRPINT_CTRL_OFFSET); irqrestore(flags); return OK; @@ -172,7 +178,6 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg) unsigned int pinint = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT); uint32_t bitmask = (1 << pinint); uint32_t regval; - int ret = OK; DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS && GPIO_IS_PININT(gpiocfg)); @@ -215,6 +220,7 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg) { regval &= ~bitmask; } + putreg32(regval, LPC43_GPIOINT_ISEL); /* Configure the active high level or rising edge */ @@ -228,6 +234,7 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg) { regval &= ~bitmask; } + putreg32(regval, LPC43_GPIOINT_IENR); /* Configure the active high low or falling edge */ @@ -241,8 +248,8 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg) { regval &= ~bitmask; } - putreg32(regval, LPC43_GPIOINT_IENF); + putreg32(regval, LPC43_GPIOINT_IENF); return OK; } @@ -250,8 +257,8 @@ int lpc43_gpioint_pinconfig(uint16_t gpiocfg) * Name: lpc43_gpioint_grpconfig * * Description: - * Configure a GPIO pin as an GPIO group interrupt member (after it has been - * configured as an input). + * Configure a GPIO pin as an GPIO group interrupt member (after it has + * been configured as an input). * * Returned Value: * Zero on success; a negated errno value on failure. @@ -270,7 +277,6 @@ int lpc43_gpioint_grpconfig(uint16_t gpiocfg) uintptr_t regaddr; uint32_t regval; uint32_t bitmask = (1 << pin); - int ret = OK; /* Select the group register base address */ @@ -314,4 +320,3 @@ int lpc43_gpioint_grpconfig(uint16_t gpiocfg) } #endif /* CONFIG_GPIO_IRQ */ - diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h index ef83d147f..35b22f7c7 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_gpioint.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lpc43xx/lpc43_gpioint.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -96,7 +96,7 @@ * ****************************************************************************/ -EXTERN int lpc43_gpioint_grpinitialize(int group, bool anded, bool level); +int lpc43_gpioint_grpinitialize(int group, bool anded, bool level); /**************************************************************************** * Name: lpc43_gpioint_pinconfig @@ -115,7 +115,7 @@ EXTERN int lpc43_gpioint_grpinitialize(int group, bool anded, bool level); * ****************************************************************************/ -EXTERN int lpc43_gpioint_pinconfig(uint16_t gpiocfg); +int lpc43_gpioint_pinconfig(uint16_t gpiocfg); /**************************************************************************** * Name: lpc43_gpioint_grpconfig @@ -134,7 +134,7 @@ EXTERN int lpc43_gpioint_pinconfig(uint16_t gpiocfg); * ****************************************************************************/ -EXTERN int lpc43_gpioint_grpconfig(uint16_t gpiocfg); +int lpc43_gpioint_grpconfig(uint16_t gpiocfg); #endif /* CONFIG_GPIO_IRQ */ #endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index e5a7937a7..36dbe1a35 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -141,7 +141,7 @@ static void lpc43_dumpnvic(const char *msg, int irq) * lpc43_dbgmonitor, lpc43_pendsv, lpc43_reserved * * Description: - * Handlers for various execptions. None are handled and all are fatal + * Handlers for various exceptions. None are handled and all are fatal * error conditions. The only advantage these provided over the default * unexpected interrupt handler is that they provide a diagnostic output. * @@ -451,14 +451,6 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_GPIO_IRQ - else if (irq >= LPC43_VALID_FIRST0L) - { - /* Maybe it is a (derived) GPIO IRQ */ - - lpc43_gpioint_disable(irq); - } -#endif lpc43_dumpnvic("disable", irq); } @@ -496,14 +488,6 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_GPIO_IRQ - else if (irq >= LPC43_VALID_FIRST0L) - { - /* Maybe it is a (derived) GPIO IRQ */ - - lpc43_gpioint_enable(irq); - } -#endif lpc43_dumpnvic("enable", irq); } @@ -518,9 +502,7 @@ void up_enable_irq(int irq) void up_ack_irq(int irq) { -#if 0 /* Does not appear to be necessary in most cases */ lpc43_clrpend(irq); -#endif } /**************************************************************************** |