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authorGregory Nutt <gnutt@nuttx.org>2013-07-23 13:54:49 -0600
committerGregory Nutt <gnutt@nuttx.org>2013-07-23 13:54:49 -0600
commit35f43c8a49525e0a61140a291fb171fc0f0d39d9 (patch)
tree2b3d34e0ec1928b270ff032a9d3265d964c70c60 /nuttx/arch/arm/src/lpc43xx
parent540dd6e555a5221612a41ff2ed38e610319178e5 (diff)
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SAMA5: Adapt clocking for different boot modes. New header files for AXI matrix, BSC, and SFR
Diffstat (limited to 'nuttx/arch/arm/src/lpc43xx')
-rw-r--r--nuttx/arch/arm/src/lpc43xx/Kconfig20
-rw-r--r--nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c2
-rw-r--r--nuttx/arch/arm/src/lpc43xx/lpc43_start.c12
3 files changed, 17 insertions, 17 deletions
diff --git a/nuttx/arch/arm/src/lpc43xx/Kconfig b/nuttx/arch/arm/src/lpc43xx/Kconfig
index 6902935ca..87c3cd920 100644
--- a/nuttx/arch/arm/src/lpc43xx/Kconfig
+++ b/nuttx/arch/arm/src/lpc43xx/Kconfig
@@ -89,36 +89,36 @@ config ARCH_FAMILY_LPC4357
choice
prompt "LPC43XX Boot Configuration"
- default BOOT_SRAM
+ default LPC43_BOOT_SRAM
depends on ARCH_CHIP_LPC43XX
---help---
The startup code needs to know if the code is running from internal FLASH,
external FLASH, SPIFI, or SRAM in order to initialize properly. Note that
a boot device is not specified for cases where the code is copied into SRAM;
- those cases are all covered by BOOT_SRAM.
+ those cases are all covered by LPC43_BOOT_SRAM.
-config BOOT_SRAM
+config LPC43_BOOT_SRAM
bool "Running from SRAM"
-config BOOT_SPIFI
+config LPC43_BOOT_SPIFI
bool "Running from QuadFLASH"
-config BOOT_FLASHA
+config LPC43_BOOT_FLASHA
bool "Running in internal FLASHA"
-config BOOT_FLASHB
+config LPC43_BOOT_FLASHB
bool "Running in internal FLASHA"
-config BOOT_CS0FLASH
+config LPC43_BOOT_CS0FLASH
bool "Running in external FLASH CS0"
-config BOOT_CS1FLASH
+config LPC43_BOOT_CS1FLASH
bool "Running in external FLASH CS1"
-config BOOT_CS2FLASH
+config LPC43_BOOT_CS2FLASH
bool "Running in external FLASH CS2"
-config BOOT_CS3FLASH
+config LPC43_BOOT_CS3FLASH
bool "Running in external FLASH CS3"
endchoice
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
index 7304bc04c..aef54d95f 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_allocateheap.c
@@ -141,7 +141,7 @@
/* Check for Configuration A. */
-#ifndef CONFIG_BOOT_SRAM
+#ifndef CONFIG_LPC43_BOOT_SRAM
/* Configuration A */
/* CONFIG_DRAM_START should be set to the base of AHB SRAM, local 0. */
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
index abb1a6fa3..bb9d8c6ab 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
@@ -129,31 +129,31 @@ static inline void lpc43_setbootrom(void)
*
****************************************************************************/
-#if defined(CONFIG_BOOT_CS0FLASH) || defined(CONFIG_BOOT_CS1FLASH) || \
- defined(CONFIG_BOOT_CS2FLASH) || defined(CONFIG_BOOT_CS3FLASH)
+#if defined(CONFIG_LPC43_BOOT_CS0FLASH) || defined(CONFIG_LPC43_BOOT_CS1FLASH) || \
+ defined(CONFIG_LPC43_BOOT_CS2FLASH) || defined(CONFIG_LPC43_BOOT_CS3FLASH)
static inline void lpc43_enabuffering(void)
{
uint32_t regval;
-#ifdef CONFIG_BOOT_CS0FLASH
+#ifdef CONFIG_LPC43_BOOT_CS0FLASH
regval = getreg32(LPC43_EMC_STATCONFIG0);
regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG0);
#endif
-#ifdef CONFIG_BOOT_CS1FLASH
+#ifdef CONFIG_LPC43_BOOT_CS1FLASH
regval = getreg32(LPC43_EMC_STATCONFIG1);
regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG1);
#endif
-#ifdef CONFIG_BOOT_CS2FLASH
+#ifdef CONFIG_LPC43_BOOT_CS2FLASH
regval = getreg32(LPC43_EMC_STATCONFIG2);
regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG2);
#endif
-#ifdef CONFIG_BOOT_CS3FLASH
+#ifdef CONFIG_LPC43_BOOT_CS3FLASH
regval = getreg32(LPC43_EMC_STATCONFIG3);
regval |= EMC_STATCONFIG_BENA
putreg32(regval, LPC43_EMC_STATCONFIG3);