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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-03-08 15:50:26 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-03-08 15:50:26 -0600 |
| commit | fc300bda7bf9d68ac5d75fa7b732692eeeae5221 (patch) | |
| tree | 295b1a1ffbbfea2990cdee1d05a05ca2577c42c0 /nuttx/arch/arm/src/tiva/chip/tiva_timer.h | |
| parent | 3100722cdd78ff94412a760138e2fd4fdc319548 (diff) | |
| download | nuttx-fc300bda7bf9d68ac5d75fa7b732692eeeae5221.tar.gz nuttx-fc300bda7bf9d68ac5d75fa7b732692eeeae5221.tar.bz2 nuttx-fc300bda7bf9d68ac5d75fa7b732692eeeae5221.zip | |
functions and definitions renamed from lm_ to tiva_
Diffstat (limited to 'nuttx/arch/arm/src/tiva/chip/tiva_timer.h')
| -rw-r--r-- | nuttx/arch/arm/src/tiva/chip/tiva_timer.h | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/nuttx/arch/arm/src/tiva/chip/tiva_timer.h b/nuttx/arch/arm/src/tiva/chip/tiva_timer.h index 023d6403c..3ce93a6c1 100644 --- a/nuttx/arch/arm/src/tiva/chip/tiva_timer.h +++ b/nuttx/arch/arm/src/tiva/chip/tiva_timer.h @@ -46,29 +46,29 @@ /* Timer register offsets ***********************************************************/ -#define LM_TIMER_GPTMCFG_OFFSET 0x000 -#define LM_TIMER_GPTMTAMR_OFFSET 0x004 -#define LM_TIMER_GPTMCTL_OFFSET 0x00c -#define LM_TIMER_GPTMIMR_OFFSET 0x018 -#define LM_TIMER_GPTMRIS_OFFSET 0x01c -#define LM_TIMER_GPTMICR_OFFSET 0x024 -#define LM_TIMER_GPTMTAILR_OFFSET 0x028 -#define LM_TIMER_GPTMTAR_OFFSET 0x048 +#define TIVA_TIMER_GPTMCFG_OFFSET 0x000 +#define TIVA_TIMER_GPTMTAMR_OFFSET 0x004 +#define TIVA_TIMER_GPTMCTL_OFFSET 0x00c +#define TIVA_TIMER_GPTMIMR_OFFSET 0x018 +#define TIVA_TIMER_GPTMRIS_OFFSET 0x01c +#define TIVA_TIMER_GPTMICR_OFFSET 0x024 +#define TIVA_TIMER_GPTMTAILR_OFFSET 0x028 +#define TIVA_TIMER_GPTMTAR_OFFSET 0x048 /* SSI register addresses ***********************************************************/ -#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000) +#define TIVA_TIMER_BASE(n) (TIVA_TIMER0_BASE + (n)*0x01000) -#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET) -#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET) -#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET) -#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET) -#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET) -#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET) -#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET) -#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET) +#define TIVA_TIMER_GPTMCFG(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMCFG_OFFSET) +#define TIVA_TIMER_GPTMTAMR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAMR_OFFSET) +#define TIVA_TIMER_GPTMCTL(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMCTL_OFFSET) +#define TIVA_TIMER_GPTMIMR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMIMR_OFFSET) +#define TIVA_TIMER_GPTMRIS(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMRIS_OFFSET) +#define TIVA_TIMER_GPTMICR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMICR_OFFSET) +#define TIVA_TIMER_GPTMTAILR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAILR_OFFSET) +#define TIVA_TIMER_GPTMTAR(n) (TIVA_TIMER_BASE(n) + TIVA_TIMER_GPTMTAR_OFFSET) -/* SSI register bit defitiions ******************************************************/ +/* SSI register bit definitions *****************************************************/ /* GPTM Configuration (GPTMCFG), offset 0x000 */ |