functions and definitions renamed from lm_ to tiva_

1 files changed, 108 insertions, 108 deletions

diff --git a/nuttx/arch/arm/src/tiva/chip/tiva_uart.h b/nuttx/arch/arm/src/tiva/chip/tiva_uart.h
index 26a54061c..0f2ea2c47 100644
--- a/nuttx/arch/arm/src/tiva/chip/tiva_uart.h
+++ b/nuttx/arch/arm/src/tiva/chip/tiva_uart.h
@@ -48,117 +48,117 @@
 
 /* UART register offsets ************************************************************/
 
-#define LM_UART_DR_OFFSET          0x000 /* UART Data */
-#define LM_UART_RSR_OFFSET         0x004 /* UART Receive Status */
-#define LM_UART_ECR_OFFSET         0x004 /* UART Error Clear */
-#define LM_UART_FR_OFFSET          0x018 /* UART Flag */
-#define LM_UART_ILPR_OFFSET        0x020 /* UART IrDA Low-Power Register */
-#define LM_UART_IBRD_OFFSET        0x024 /* UART Integer Baud-Rate Divisor*/
-#define LM_UART_FBRD_OFFSET        0x028 /* UART Fractional Baud-Rate Divisor */
-#define LM_UART_LCRH_OFFSET        0x02c /* UART Line Control */
-#define LM_UART_CTL_OFFSET         0x030 /* UART Control */
-#define LM_UART_IFLS_OFFSET        0x034 /* UART Interrupt FIFO Level Select */
-#define LM_UART_IM_OFFSET          0x038 /* UART Interrupt Mask */
-#define LM_UART_RIS_OFFSET         0x03c /* UART Raw Interrupt Status */
-#define LM_UART_MIS_OFFSET         0x040 /* UART Masked Interrupt Status */
-#define LM_UART_ICR_OFFSET         0x044 /* UART Interrupt Clear */
-#define LM_UART_PERIPHID4_OFFSET   0xfd0 /* UART Peripheral Identification 4 */
-#define LM_UART_PERIPHID5_OFFSET   0xfd4 /* UART Peripheral Identification 5 */
-#define LM_UART_PERIPHID6_OFFSET   0xfd8 /* UART Peripheral Identification 6 */
-#define LM_UART_PERIPHID7_OFFSET   0xfdc /* UART Peripheral Identification 7 */
-#define LM_UART_PERIPHID0_OFFSET   0xfe0 /* UART Peripheral Identification 0 */
-#define LM_UART_PERIPHID1_OFFSET   0xfe4 /* UART Peripheral Identification 1 */
-#define LM_UART_PERIPHID2_OFFSET   0xfe8 /* UART Peripheral Identification 2 */
-#define LM_UART_PERIPHID3_OFFSET   0xfec /* UART Peripheral Identification 3 */
-#define LM_UART_PCELLID0_OFFSET    0xff0 /* UART PrimeCell Identification 0 */
-#define LM_UART_PCELLID1_OFFSET    0xff4 /* UART PrimeCell Identification 1 */
-#define LM_UART_PCELLID2_OFFSET    0xff8 /* UART PrimeCell Identification 2 */
-#define LM_UART_PCELLID3_OFFSET    0xffc /* UART PrimeCell Identification 3 */
+#define TIVA_UART_DR_OFFSET        0x000 /* UART Data */
+#define TIVA_UART_RSR_OFFSET       0x004 /* UART Receive Status */
+#define TIVA_UART_ECR_OFFSET       0x004 /* UART Error Clear */
+#define TIVA_UART_FR_OFFSET        0x018 /* UART Flag */
+#define TIVA_UART_ILPR_OFFSET      0x020 /* UART IrDA Low-Power Register */
+#define TIVA_UART_IBRD_OFFSET      0x024 /* UART Integer Baud-Rate Divisor*/
+#define TIVA_UART_FBRD_OFFSET      0x028 /* UART Fractional Baud-Rate Divisor */
+#define TIVA_UART_LCRH_OFFSET      0x02c /* UART Line Control */
+#define TIVA_UART_CTL_OFFSET       0x030 /* UART Control */
+#define TIVA_UART_IFLS_OFFSET      0x034 /* UART Interrupt FIFO Level Select */
+#define TIVA_UART_IM_OFFSET        0x038 /* UART Interrupt Mask */
+#define TIVA_UART_RIS_OFFSET       0x03c /* UART Raw Interrupt Status */
+#define TIVA_UART_MIS_OFFSET       0x040 /* UART Masked Interrupt Status */
+#define TIVA_UART_ICR_OFFSET       0x044 /* UART Interrupt Clear */
+#define TIVA_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
+#define TIVA_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
+#define TIVA_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
+#define TIVA_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
+#define TIVA_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
+#define TIVA_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
+#define TIVA_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
+#define TIVA_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
+#define TIVA_UART_PCELLID0_OFFSET  0xff0 /* UART PrimeCell Identification 0 */
+#define TIVA_UART_PCELLID1_OFFSET  0xff4 /* UART PrimeCell Identification 1 */
+#define TIVA_UART_PCELLID2_OFFSET  0xff8 /* UART PrimeCell Identification 2 */
+#define TIVA_UART_PCELLID3_OFFSET  0xffc /* UART PrimeCell Identification 3 */
 
 /* UART register addresses **********************************************************/
 
-#define LM_UART_BASE(n)            (LM_UART0_BASE + (n)*0x01000)
-
-#define LM_UART_DR(n)              (LM_UART_BASE(n) + LM_UART_DR_OFFSET)
-#define LM_UART_RSR(n)             (LM_UART_BASE(n) + LM_UART_RSR_OFFSET)
-#define LM_UART_ECR(n)             (LM_UART_BASE(n) + LM_UART_ECR_OFFSET)
-#define LM_UART_FR(n)              (LM_UART_BASE(n) + LM_UART_FR_OFFSET)
-#define LM_UART_ILPR(n)            (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET)
-#define LM_UART_IBRD(n)            (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET)
-#define LM_UART_FBRD(n)            (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET)
-#define LM_UART_LCRH(n)            (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET)
-#define LM_UART_CTL(n)             (LM_UART_BASE(n) + LM_UART_CTL_OFFSET)
-#define LM_UART_IFLS(n)            (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET)
-#define LM_UART_IM(n)              (LM_UART_BASE(n) + LM_UART_IM_OFFSET)
-#define LM_UART_RIS(n)             (LM_UART_BASE(n) + LM_UART_RIS_OFFSET)
-#define LM_UART_MIS(n)             (LM_UART_BASE(n) + LM_UART_MIS_OFFSET)
-#define LM_UART_ICR(n)             (LM_UART_BASE(n) + LM_UART_ICR_OFFSET)
-#define LM_UART_PERIPHID4(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET)
-#define LM_UART_PERIPHID5(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET)
-#define LM_UART_PERIPHID6(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET)
-#define LM_UART_PERIPHID7(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET)
-#define LM_UART_PERIPHID0(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET)
-#define LM_UART_PERIPHID1(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET)
-#define LM_UART_PERIPHID2(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET)
-#define LM_UART_PERIPHID3(n)       (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET)
-#define LM_UART_PCELLID0(n)        (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET)
-#define LM_UART_PCELLID1(n)        (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET)
-#define LM_UART_PCELLID2(n)        (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET)
-#define LM_UART_PCELLID3(n)        (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET)
-
-#define LM_UART0_DR                (LM_UART0_BASE + LM_UART_TDR_OFFSET)
-#define LM_UART0_RSR               (LM_UART0_BASE + LM_UART_RSR_OFFSET)
-#define LM_UART0_ECR               (LM_UART0_BASE + LM_UART_ECR_OFFSET)
-#define LM_UART0_FR                (LM_UART0_BASE + LM_UART_FR_OFFSET)
-#define LM_UART0_ILPR              (LM_UART0_BASE + LM_UART_ILPR_OFFSET)
-#define LM_UART0_IBRD              (LM_UART0_BASE + LM_UART_IBRD_OFFSET)
-#define LM_UART0_FBRD              (LM_UART0_BASE + LM_UART_FBRD_OFFSET)
-#define LM_UART0_LCRH              (LM_UART0_BASE + LM_UART_LCRH_OFFSET)
-#define LM_UART0_CTL               (LM_UART0_BASE + LM_UART_CTL_OFFSET)
-#define LM_UART0_IFLS              (LM_UART0_BASE + LM_UART_IFLS_OFFSET)
-#define LM_UART0_IM                (LM_UART0_BASE + LM_UART_IM_OFFSET)
-#define LM_UART0_RIS               (LM_UART0_BASE + LM_UART_RIS_OFFSET)
-#define LM_UART0_MIS               (LM_UART0_BASE + LM_UART_MIS_OFFSET)
-#define LM_UART0_ICR               (LM_UART0_BASE + LM_UART_ICR_OFFSET)
-#define LM_UART0_PERIPHID4         (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET)
-#define LM_UART0_PERIPHID5         (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET)
-#define LM_UART0_PERIPHID6         (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET)
-#define LM_UART0_PERIPHID7         (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET)
-#define LM_UART0_PERIPHID0         (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET)
-#define LM_UART0_PERIPHID1         (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET)
-#define LM_UART0_PERIPHID2         (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET)
-#define LM_UART0_PERIPHID3         (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET)
-#define LM_UART0_PCELLID0          (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET)
-#define LM_UART0_PCELLID1          (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET)
-#define LM_UART0_PCELLID2          (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET)
-#define LM_UART0_PCELLID3          (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET)
-
-#define LM_UART1_DR                (LM_UART1_BASE + LM_UART_DR_OFFSET)
-#define LM_UART1_RSR               (LM_UART1_BASE + LM_UART_RSR_OFFSET)
-#define LM_UART1_ECR               (LM_UART1_BASE + LM_UART_ECR_OFFSET)
-#define LM_UART1_FR                (LM_UART1_BASE + LM_UART_FR_OFFSET)
-#define LM_UART1_ILPR              (LM_UART1_BASE + LM_UART_ILPR_OFFSET)
-#define LM_UART1_IBRD              (LM_UART1_BASE + LM_UART_IBRD_OFFSET)
-#define LM_UART1_FBRD              (LM_UART1_BASE + LM_UART_FBRD_OFFSET)
-#define LM_UART1_LCRH              (LM_UART1_BASE + LM_UART_LCRH_OFFSET)
-#define LM_UART1_CTL               (LM_UART1_BASE + LM_UART_CTL_OFFSET)
-#define LM_UART1_IFLS              (LM_UART1_BASE + LM_UART_IFLS_OFFSET)
-#define LM_UART1_IM                (LM_UART1_BASE + LM_UART_IM_OFFSET)
-#define LM_UART1_RIS               (LM_UART1_BASE + LM_UART_RIS_OFFSET)
-#define LM_UART1_MIS               (LM_UART1_BASE + LM_UART_MIS_OFFSET)
-#define LM_UART1_ICR               (LM_UART1_BASE + LM_UART_ICR_OFFSET)
-#define LM_UART1_PERIPHID4         (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET)
-#define LM_UART1_PERIPHID5         (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET)
-#define LM_UART1_PERIPHID6         (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET)
-#define LM_UART1_PERIPHID7         (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET)
-#define LM_UART1_PERIPHID0         (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET)
-#define LM_UART1_PERIPHID1         (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET)
-#define LM_UART1_PERIPHID2         (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET)
-#define LM_UART1_PERIPHID3         (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET)
-#define LM_UART1_PCELLID0          (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET)
-#define LM_UART1_PCELLID1          (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET)
-#define LM_UART1_PCELLID2          (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET)
-#define LM_UART1_PCELLID3          (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET)
+#define TIVA_UART_BASE(n)          (TIVA_UART0_BASE + (n)*0x01000)
+
+#define TIVA_UART_DR(n)            (TIVA_UART_BASE(n) + TIVA_UART_DR_OFFSET)
+#define TIVA_UART_RSR(n)           (TIVA_UART_BASE(n) + TIVA_UART_RSR_OFFSET)
+#define TIVA_UART_ECR(n)           (TIVA_UART_BASE(n) + TIVA_UART_ECR_OFFSET)
+#define TIVA_UART_FR(n)            (TIVA_UART_BASE(n) + TIVA_UART_FR_OFFSET)
+#define TIVA_UART_ILPR(n)          (TIVA_UART_BASE(n) + TIVA_UART_ILPR_OFFSET)
+#define TIVA_UART_IBRD(n)          (TIVA_UART_BASE(n) + TIVA_UART_IBRD_OFFSET)
+#define TIVA_UART_FBRD(n)          (TIVA_UART_BASE(n) + TIVA_UART_FBRD_OFFSET)
+#define TIVA_UART_LCRH(n)          (TIVA_UART_BASE(n) + TIVA_UART_LCRH_OFFSET)
+#define TIVA_UART_CTL(n)           (TIVA_UART_BASE(n) + TIVA_UART_CTL_OFFSET)
+#define TIVA_UART_IFLS(n)          (TIVA_UART_BASE(n) + TIVA_UART_IFLS_OFFSET)
+#define TIVA_UART_IM(n)            (TIVA_UART_BASE(n) + TIVA_UART_IM_OFFSET)
+#define TIVA_UART_RIS(n)           (TIVA_UART_BASE(n) + TIVA_UART_RIS_OFFSET)
+#define TIVA_UART_MIS(n)           (TIVA_UART_BASE(n) + TIVA_UART_MIS_OFFSET)
+#define TIVA_UART_ICR(n)           (TIVA_UART_BASE(n) + TIVA_UART_ICR_OFFSET)
+#define TIVA_UART_PERIPHID4(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID4_OFFSET)
+#define TIVA_UART_PERIPHID5(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID5_OFFSET)
+#define TIVA_UART_PERIPHID6(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID6_OFFSET)
+#define TIVA_UART_PERIPHID7(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID7_OFFSET)
+#define TIVA_UART_PERIPHID0(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID0_OFFSET)
+#define TIVA_UART_PERIPHID1(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID1_OFFSET)
+#define TIVA_UART_PERIPHID2(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID2_OFFSET)
+#define TIVA_UART_PERIPHID3(n)     (TIVA_UART_BASE(n) + TIVA_UART_PERIPHID3_OFFSET)
+#define TIVA_UART_PCELLID0(n)      (TIVA_UART_BASE(n) + TIVA_UART_PCELLID0_OFFSET)
+#define TIVA_UART_PCELLID1(n)      (TIVA_UART_BASE(n) + TIVA_UART_PCELLID1_OFFSET)
+#define TIVA_UART_PCELLID2(n)      (TIVA_UART_BASE(n) + TIVA_UART_PCELLID2_OFFSET)
+#define TIVA_UART_PCELLID3(n)      (TIVA_UART_BASE(n) + TIVA_UART_PCELLID3_OFFSET)
+
+#define TIVA_UART0_DR              (TIVA_UART0_BASE + TIVA_UART_TDR_OFFSET)
+#define TIVA_UART0_RSR             (TIVA_UART0_BASE + TIVA_UART_RSR_OFFSET)
+#define TIVA_UART0_ECR             (TIVA_UART0_BASE + TIVA_UART_ECR_OFFSET)
+#define TIVA_UART0_FR              (TIVA_UART0_BASE + TIVA_UART_FR_OFFSET)
+#define TIVA_UART0_ILPR            (TIVA_UART0_BASE + TIVA_UART_ILPR_OFFSET)
+#define TIVA_UART0_IBRD            (TIVA_UART0_BASE + TIVA_UART_IBRD_OFFSET)
+#define TIVA_UART0_FBRD            (TIVA_UART0_BASE + TIVA_UART_FBRD_OFFSET)
+#define TIVA_UART0_LCRH            (TIVA_UART0_BASE + TIVA_UART_LCRH_OFFSET)
+#define TIVA_UART0_CTL             (TIVA_UART0_BASE + TIVA_UART_CTL_OFFSET)
+#define TIVA_UART0_IFLS            (TIVA_UART0_BASE + TIVA_UART_IFLS_OFFSET)
+#define TIVA_UART0_IM              (TIVA_UART0_BASE + TIVA_UART_IM_OFFSET)
+#define TIVA_UART0_RIS             (TIVA_UART0_BASE + TIVA_UART_RIS_OFFSET)
+#define TIVA_UART0_MIS             (TIVA_UART0_BASE + TIVA_UART_MIS_OFFSET)
+#define TIVA_UART0_ICR             (TIVA_UART0_BASE + TIVA_UART_ICR_OFFSET)
+#define TIVA_UART0_PERIPHID4       (TIVA_UART0_BASE + TIVA_UART_PERIPHID4_OFFSET)
+#define TIVA_UART0_PERIPHID5       (TIVA_UART0_BASE + TIVA_UART_PERIPHID5_OFFSET)
+#define TIVA_UART0_PERIPHID6       (TIVA_UART0_BASE + TIVA_UART_PERIPHID6_OFFSET)
+#define TIVA_UART0_PERIPHID7       (TIVA_UART0_BASE + TIVA_UART_PERIPHID7_OFFSET)
+#define TIVA_UART0_PERIPHID0       (TIVA_UART0_BASE + TIVA_UART_PERIPHID0_OFFSET)
+#define TIVA_UART0_PERIPHID1       (TIVA_UART0_BASE + TIVA_UART_PERIPHID1_OFFSET)
+#define TIVA_UART0_PERIPHID2       (TIVA_UART0_BASE + TIVA_UART_PERIPHID2_OFFSET)
+#define TIVA_UART0_PERIPHID3       (TIVA_UART0_BASE + TIVA_UART_PERIPHID3_OFFSET)
+#define TIVA_UART0_PCELLID0        (TIVA_UART0_BASE + TIVA_UART_PCELLID0_OFFSET)
+#define TIVA_UART0_PCELLID1        (TIVA_UART0_BASE + TIVA_UART_PCELLID1_OFFSET)
+#define TIVA_UART0_PCELLID2        (TIVA_UART0_BASE + TIVA_UART_PCELLID2_OFFSET)
+#define TIVA_UART0_PCELLID3        (TIVA_UART0_BASE + TIVA_UART_PCELLID3_OFFSET)
+
+#define TIVA_UART1_DR              (TIVA_UART1_BASE + TIVA_UART_DR_OFFSET)
+#define TIVA_UART1_RSR             (TIVA_UART1_BASE + TIVA_UART_RSR_OFFSET)
+#define TIVA_UART1_ECR             (TIVA_UART1_BASE + TIVA_UART_ECR_OFFSET)
+#define TIVA_UART1_FR              (TIVA_UART1_BASE + TIVA_UART_FR_OFFSET)
+#define TIVA_UART1_ILPR            (TIVA_UART1_BASE + TIVA_UART_ILPR_OFFSET)
+#define TIVA_UART1_IBRD            (TIVA_UART1_BASE + TIVA_UART_IBRD_OFFSET)
+#define TIVA_UART1_FBRD            (TIVA_UART1_BASE + TIVA_UART_FBRD_OFFSET)
+#define TIVA_UART1_LCRH            (TIVA_UART1_BASE + TIVA_UART_LCRH_OFFSET)
+#define TIVA_UART1_CTL             (TIVA_UART1_BASE + TIVA_UART_CTL_OFFSET)
+#define TIVA_UART1_IFLS            (TIVA_UART1_BASE + TIVA_UART_IFLS_OFFSET)
+#define TIVA_UART1_IM              (TIVA_UART1_BASE + TIVA_UART_IM_OFFSET)
+#define TIVA_UART1_RIS             (TIVA_UART1_BASE + TIVA_UART_RIS_OFFSET)
+#define TIVA_UART1_MIS             (TIVA_UART1_BASE + TIVA_UART_MIS_OFFSET)
+#define TIVA_UART1_ICR             (TIVA_UART1_BASE + TIVA_UART_ICR_OFFSET)
+#define TIVA_UART1_PERIPHID4       (TIVA_UART1_BASE + TIVA_UART_PERIPHID4_OFFSET)
+#define TIVA_UART1_PERIPHID5       (TIVA_UART1_BASE + TIVA_UART_PERIPHID5_OFFSET)
+#define TIVA_UART1_PERIPHID6       (TIVA_UART1_BASE + TIVA_UART_PERIPHID6_OFFSET)
+#define TIVA_UART1_PERIPHID7       (TIVA_UART1_BASE + TIVA_UART_PERIPHID7_OFFSET)
+#define TIVA_UART1_PERIPHID0       (TIVA_UART1_BASE + TIVA_UART_PERIPHID0_OFFSET)
+#define TIVA_UART1_PERIPHID1       (TIVA_UART1_BASE + TIVA_UART_PERIPHID1_OFFSET)
+#define TIVA_UART1_PERIPHID2       (TIVA_UART1_BASE + TIVA_UART_PERIPHID2_OFFSET)
+#define TIVA_UART1_PERIPHID3       (TIVA_UART1_BASE + TIVA_UART_PERIPHID3_OFFSET)
+#define TIVA_UART1_PCELLID0        (TIVA_UART1_BASE + TIVA_UART_PCELLID0_OFFSET)
+#define TIVA_UART1_PCELLID1        (TIVA_UART1_BASE + TIVA_UART_PCELLID1_OFFSET)
+#define TIVA_UART1_PCELLID2        (TIVA_UART1_BASE + TIVA_UART_PCELLID2_OFFSET)
+#define TIVA_UART1_PCELLID3        (TIVA_UART1_BASE + TIVA_UART_PCELLID3_OFFSET)
 
 /* UART register bit settings *******************************************************/