TM4C129X: Framework for new Tiva clocking logic (details not yet implemented)

6 files changed, 311 insertions, 42 deletions

diff --git a/nuttx/arch/arm/src/tiva/Make.defs b/nuttx/arch/arm/src/tiva/Make.defs
index 6ce1e3111..8cd2d78dc 100644
--- a/nuttx/arch/arm/src/tiva/Make.defs
+++ b/nuttx/arch/arm/src/tiva/Make.defs
@@ -74,9 +74,15 @@ CMN_CSRCS += up_elf.c
 endif
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = tiva_allocateheap.c tiva_start.c tiva_syscontrol.c tiva_irq.c
-CHIP_CSRCS += tiva_gpio.c tiva_gpioirq.c tiva_lowputc.c tiva_serial.c
-CHIP_CSRCS += tiva_ssi.c tiva_dumpgpio.c
+CHIP_CSRCS  = tiva_allocateheap.c tiva_start.c tiva_irq.c tiva_gpio.c
+CHIP_CSRCS += tiva_gpioirq.c tiva_lowputc.c tiva_serial.c tiva_ssi.c
+CHIP_CSRCS += tiva_dumpgpio.c
+
+ifeq ($(CONFIG_ARCH_CHIP_TM4C129),y)
+CHIP_CSRCS += tm4c129_syscontrol.c
+else
+CHIP_CSRCS += tiva_syscontrol.c
+endif
 
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += tiva_timerisr.c
diff --git a/nuttx/arch/arm/src/tiva/chip/tm4c129_syscontrol.h b/nuttx/arch/arm/src/tiva/chip/tm4c129_syscontrol.h
index 95dfc7c63..d33bc262d 100644
--- a/nuttx/arch/arm/src/tiva/chip/tm4c129_syscontrol.h
+++ b/nuttx/arch/arm/src/tiva/chip/tm4c129_syscontrol.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/tiva/chip/tm4c129x_syscontrol.h
+ * arch/arm/src/tiva/chip/tm4c129_syscontrol.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TIVA_CHIP_TM4C129X_SYSCONTROL_H
-#define __ARCH_ARM_SRC_TIVA_CHIP_TM4C129X_SYSCONTROL_H
+#ifndef __ARCH_ARM_SRC_TIVA_CHIP_TM4C129_SYSCONTROL_H
+#define __ARCH_ARM_SRC_TIVA_CHIP_TM4C129_SYSCONTROL_H
 
 /********************************************************************************************
  * Included Files
@@ -1190,8 +1190,8 @@
 #  define SYSCON_SRTIMER_R3            (1 << 3)   /* Bit 3:  16/32-Bit Timer 3 Software Reset */
 #  define SYSCON_SRTIMER_R4            (1 << 4)   /* Bit 4:  16/32-Bit Timer 4 Software Reset */
 #  define SYSCON_SRTIMER_R5            (1 << 5)   /* Bit 5:  16/32-Bit Timer 5 Software Reset */
-#  define SYSCON_SRTIMER_R5            (1 << 6)   /* Bit 6:  16/32-Bit Timer 6 Software Reset */
-#  define SYSCON_SRTIMER_R5            (1 << 7)   /* Bit 7:  16/32-Bit Timer 7 Software Reset */
+#  define SYSCON_SRTIMER_R6            (1 << 6)   /* Bit 6:  16/32-Bit Timer 6 Software Reset */
+#  define SYSCON_SRTIMER_R7            (1 << 7)   /* Bit 7:  16/32-Bit Timer 7 Software Reset */
 
 /* GPIO Software Reset */
 
@@ -1646,8 +1646,8 @@
 #  define SYSCON_DCGCTIMER_D3          (1 << 3)   /* Bit 3:  16/32-Bit Timer 3 Deep-Sleep Mode Clock Gating Control */
 #  define SYSCON_DCGCTIMER_D4          (1 << 4)   /* Bit 4:  16/32-Bit Timer 4 Deep-Sleep Mode Clock Gating Control */
 #  define SYSCON_DCGCTIMER_D5          (1 << 5)   /* Bit 5:  16/32-Bit Timer 5 Deep-Sleep Mode Clock Gating Control */
-#  define SYSCON_DCGCTIMER_D5          (1 << 6)   /* Bit 6:  16/32-Bit Timer 6 Deep-Sleep Mode Clock Gating Control */
-#  define SYSCON_DCGCTIMER_D5          (1 << 7)   /* Bit 7:  16/32-Bit Timer 7 Deep-Sleep Mode Clock Gating Control */
+#  define SYSCON_DCGCTIMER_D6          (1 << 6)   /* Bit 6:  16/32-Bit Timer 6 Deep-Sleep Mode Clock Gating Control */
+#  define SYSCON_DCGCTIMER_D7          (1 << 7)   /* Bit 7:  16/32-Bit Timer 7 Deep-Sleep Mode Clock Gating Control */
 
 /* GPIO Deep-Sleep Mode Clock */
 
@@ -1803,7 +1803,7 @@
 
 /* GPIO Power Control */
 
-#define SYSCON_PCGPIO(n)               (1 << (n)) /* Bit n:  GPIO Port N Power Control */
+#define SYSCON_PCGPIO(n)               (1 << (n)) /* Bit n:  GPIO Port n Power Control */
 #  define SYSCON_PCGPIO_P0             (1 << 0)   /* Bit 0:  GPIO Port A Power Control */
 #  define SYSCON_PCGPIO_P1             (1 << 1)   /* Bit 1:  GPIO Port B Power Control */
 #  define SYSCON_PCGPIO_P2             (1 << 2)   /* Bit 2:  GPIO Port C Power Control */
@@ -1941,7 +1941,7 @@
 
 /* GPIO Peripheral Ready */
 
-#define SYSCON_PRGPIO(n)               (1 << (n)) /* Bit n:  GPIO Port F Peripheral Ready */
+#define SYSCON_PRGPIO(n)               (1 << (n)) /* Bit n:  GPIO Port n Peripheral Ready */
 #  define SYSCON_PRGPIO_R0             (1 << 0)   /* Bit 0:  GPIO Port A Peripheral Ready */
 #  define SYSCON_PRGPIO_R1             (1 << 1)   /* Bit 1:  GPIO Port B Peripheral Ready */
 #  define SYSCON_PRGPIO_R2             (1 << 2)   /* Bit 2:  GPIO Port C Peripheral Ready */
@@ -2095,4 +2095,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TM4C129X_SYSCONTROL_H */
+#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TM4C129_SYSCONTROL_H */
diff --git a/nuttx/arch/arm/src/tiva/tiva_enableclks.h b/nuttx/arch/arm/src/tiva/tiva_enableclks.h
new file mode 100644
index 000000000..ddcf9db10
--- /dev/null
+++ b/nuttx/arch/arm/src/tiva/tiva_enableclks.h
@@ -0,0 +1,102 @@
+/************************************************************************************
+ * arch/arm/src/tiva/tiva_enableclks.h
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TIVA_TIVA_ENABLECLKS_H
+#define __ARCH_ARM_SRC_TIVA_TIVA_ENABLECLKS_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "chip/tiva_syscontrol.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Clocks are enabled or disabled by setting or clearing a bit (b) in a system
+ * control register (a))
+ */
+
+#define tiva_enableclk(a,b)       modifyreg32((a),0,(b))
+#define tiva_disableclk(a,b)      modifyreg32((a),(b),0)
+
+/* GPIO clocking */
+
+#ifdef TIVA_SYSCON_RCGCGPIO
+#  define tiva_gpio_enableclk(p)  tiva_enableclk(TIVA_SYSCON_RCGCGPIO,SYSCON_RCGCGPIO(p))
+#  define tiva_gpio_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCGPIO,SYSCON_RCGCGPIO(p))
+#else
+#  define tiva_gpio_enableclk(p)  tiva_enableclk(TIVA_SYSCON_RCGC2,SYSCON_RCGC2_GPIO(p))
+#  define tiva_gpio_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGC2,SYSCON_RCGC2_GPIO(p))
+#endif
+
+/* UART clocking */
+
+#ifdef TIVA_SYSCON_RCGCUART
+#  define tiva_uart_enableclk(p)  tiva_enableclk(TIVA_SYSCON_RCGCUART,SYSCON_RCGCUART(p))
+#  define tiva_uart_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGCUART,SYSCON_RCGCUART(p))
+
+#  define tiva_uart0_enableclk()  tiva_uart_enableclk(0)
+#  define tiva_uart1_enableclk()  tiva_uart_enableclk(1)
+#  define tiva_uart2_enableclk()  tiva_uart_enableclk(2)
+#  define tiva_uart3_enableclk()  tiva_uart_enableclk(3)
+#  define tiva_uart4_enableclk()  tiva_uart_enableclk(4)
+#  define tiva_uart5_enableclk()  tiva_uart_enableclk(5)
+#  define tiva_uart6_enableclk()  tiva_uart_enableclk(6)
+#  define tiva_uart7_enableclk()  tiva_uart_enableclk(7)
+
+#  define tiva_uart0_disableclk() tiva_uart_disableclk(0)
+#  define tiva_uart1_disableclk() tiva_uart_disableclk(1)
+#  define tiva_uart2_disableclk() tiva_uart_disableclk(2)
+#  define tiva_uart3_disableclk() tiva_uart_disableclk(3)
+#  define tiva_uart4_disableclk() tiva_uart_disableclk(4)
+#  define tiva_uart5_disableclk() tiva_uart_disableclk(5)
+#  define tiva_uart6_disableclk() tiva_uart_disableclk(6)
+#  define tiva_uart7_disableclk() tiva_uart_disableclk(7)
+#else
+#  define tiva_uart0_enableclk()  tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0)
+#  define tiva_uart1_enableclk()  tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1)
+#  define tiva_uart2_enableclk()  tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2)
+
+#  define tiva_uart0_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0)
+#  define tiva_uart1_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1)
+#  define tiva_uart2_disableclk() tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2)
+#endif
+
+#endif /* __ARCH_ARM_SRC_TIVA_TIVA_ENABLECLKS_H */
diff --git a/nuttx/arch/arm/src/tiva/tiva_gpio.c b/nuttx/arch/arm/src/tiva/tiva_gpio.c
index faf141905..5405bda49 100644
--- a/nuttx/arch/arm/src/tiva/tiva_gpio.c
+++ b/nuttx/arch/arm/src/tiva/tiva_gpio.c
@@ -48,6 +48,7 @@
 #include <arch/irq.h>
 
 #include "up_arch.h"
+#include "tiva_enableclks.h"
 #include "tiva_gpio.h"
 
 /****************************************************************************
@@ -814,7 +815,6 @@ int tiva_configgpio(uint32_t cfgset)
   unsigned int pinno;
   uintptr_t    base;
   uint32_t     pin;
-  uint32_t     regval;
 
   /* Decode the basics */
 
@@ -839,9 +839,7 @@ int tiva_configgpio(uint32_t cfgset)
    * in the RCGC2 register."
    */
 
-  regval = getreg32(TIVA_SYSCON_RCGC2);
-  regval |= SYSCON_RCGC2_GPIO(port);
-  putreg32(regval, TIVA_SYSCON_RCGC2);
+  tiva_gpio_enableclk(port);
 
   /* First, set the port to digital input.  This is the safest state in which
    * to perform reconfiguration.
diff --git a/nuttx/arch/arm/src/tiva/tiva_lowputc.c b/nuttx/arch/arm/src/tiva/tiva_lowputc.c
index b0860a8e5..b943cd4de 100644
--- a/nuttx/arch/arm/src/tiva/tiva_lowputc.c
+++ b/nuttx/arch/arm/src/tiva/tiva_lowputc.c
@@ -46,6 +46,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
+#include "tiva_enableclks.h"
 #include "tiva_gpio.h"
 #include "chip/tiva_pinmap.h"
 
@@ -246,7 +247,6 @@ void up_lowputc(char ch)
 
 void up_lowsetup(void)
 {
-  uint32_t regval;
 #if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
   uint32_t ctl;
 #endif
@@ -257,72 +257,56 @@ void up_lowsetup(void)
    */
 
 #ifdef CONFIG_TIVA_UART0
-  regval  = getreg32(TIVA_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART0;
-  putreg32(regval, TIVA_SYSCON_RCGC1);
+  tiva_uart0_enableclk();
 
   tiva_configgpio(GPIO_UART0_RX);
   tiva_configgpio(GPIO_UART0_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART1
-  regval  = getreg32(TIVA_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART1;
-  putreg32(regval, TIVA_SYSCON_RCGC1);
+  tiva_uart1_enableclk();
 
   tiva_configgpio(GPIO_UART1_RX);
   tiva_configgpio(GPIO_UART1_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART2
-  regval  = getreg32(TIVA_SYSCON_RCGC1);
-  regval |= SYSCON_RCGC1_UART2;
-  putreg32(regval, TIVA_SYSCON_RCGC1);
+  tiva_uart2_enableclk();
 
   tiva_configgpio(GPIO_UART2_RX);
   tiva_configgpio(GPIO_UART2_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART3
-  regval  = getreg32(TIVA_SYSCON_RCGCUART);
-  regval |= SYSCON_RCGCUART_R3;
-  putreg32(regval, TIVA_SYSCON_RCGCUART);
+  tiva_uart3_enableclk();
 
   tiva_configgpio(GPIO_UART3_RX);
   tiva_configgpio(GPIO_UART3_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART4
-  regval  = getreg32(TIVA_SYSCON_RCGCUART);
-  regval |= SYSCON_RCGCUART_R4;
-  putreg32(regval, TIVA_SYSCON_RCGCUART);
+  tiva_uart4_enableclk();
 
   tiva_configgpio(GPIO_UART4_RX);
   tiva_configgpio(GPIO_UART4_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART5
-  regval  = getreg32(TIVA_SYSCON_RCGCUART);
-  regval |= SYSCON_RCGCUART_R5;
-  putreg32(regval, TIVA_SYSCON_RCGCUART);
+  tiva_uart5_enableclk();
 
   tiva_configgpio(GPIO_UART5_RX);
   tiva_configgpio(GPIO_UART5_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART6
-  regval  = getreg32(TIVA_SYSCON_RCGCUART);
-  regval |= SYSCON_RCGCUART_R6;
-  putreg32(regval, TIVA_SYSCON_RCGCUART);
+  tiva_uart6_enableclk();
 
   tiva_configgpio(GPIO_UART6_RX);
   tiva_configgpio(GPIO_UART6_TX);
 #endif
 
 #ifdef CONFIG_TIVA_UART7
-  regval  = getreg32(TIVA_SYSCON_RCGCUART);
-  regval |= SYSCON_RCGCUART_R7;
-  putreg32(regval, TIVA_SYSCON_RCGCUART);
+  tiva_uart7_enableclk();
 
   tiva_configgpio(GPIO_UART7_RX);
   tiva_configgpio(GPIO_UART7_TX);
diff --git a/nuttx/arch/arm/src/tiva/tm4c129_syscontrol.c b/nuttx/arch/arm/src/tiva/tm4c129_syscontrol.c
new file mode 100644
index 000000000..f7436ca98
--- /dev/null
+++ b/nuttx/arch/arm/src/tiva/tm4c129_syscontrol.c
@@ -0,0 +1,179 @@
+/****************************************************************************
+ * arch/arm/src/tiva/tm4c129_syscontrol.c
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/init.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "chip.h"
+#include "tiva_syscontrol.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define FAST_OSCDELAY   (512*1024)
+#define SLOW_OSCDELAY   (4*1024)
+#define PLLLOCK_DELAY   (32*1024)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: tiva_delay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky
+ *   because the time that we wait can be significant and is determined by
+ *   the previous clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void tiva_delay(uint32_t delay)
+{
+  __asm__ __volatile__("1:\n"
+                       "\tsubs  %0, #1\n"
+                       "\tbne   1b\n"
+                       : "=r"(delay) : "r"(delay));
+}
+
+/****************************************************************************
+ * Name: tiva_oscdelay
+ *
+ * Description:
+ *   Wait for the newly selected oscillator(s) to settle.  This is tricky because
+ *   the time that we wait can be significant and is determined by the previous
+ *   clock setting, not the one that we are configuring.
+ *
+ ****************************************************************************/
+
+static inline void tiva_oscdelay(uint32_t rcc, uint32_t rcc2)
+{
+  /* Wait for the oscillator  to stabilize.  A smaller delay is used if the
+   * current clock rate is very slow.
+   */
+
+  uint32_t delay = FAST_OSCDELAY;
+#warning Missing logic
+
+  /* Then delay that number of loops */
+
+  tiva_delay(delay);
+}
+
+/****************************************************************************
+ * Name: tiva_pll_lock
+ *
+ * Description:
+ *   The new RCC values have been selected... wait for the PLL to lock on
+ *
+ ****************************************************************************/
+
+static inline void tiva_pll_lock(void)
+{
+  volatile uint32_t delay;
+
+  /* Loop until the lock is achieved or until a timeout occurs */
+
+  for (delay = PLLLOCK_DELAY; delay > 0; delay--)
+    {
+      /* Check if the PLL is locked on */
+
+      if ((getreg32(TIVA_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
+        {
+          /* Yes.. return now */
+
+          return;
+        }
+    }
+
+  /* If we get here, then PLL lock was not achieved */
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: tiva_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on desired rcc and rcc2 settings.
+ *   This is use to set up the initial clocking but can be used later to
+ *   support slow clocked, low power consumption modes.
+ *
+ ****************************************************************************/
+
+void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
+{
+#warning Missing logic
+}
+
+/****************************************************************************
+ * Name: up_clockconfig
+ *
+ * Description:
+ *   Called early in the boot sequence (before .data and .bss are available)
+ *   in order to configure initial clocking.
+ *
+ ****************************************************************************/
+
+void up_clockconfig(void)
+{
+  /* Set the clocking to run with the default settings provided in the board.h
+   * header file
+   */
+#warning Missing logic
+}