A10 serial driver (still needs some work). From Alan Carvalho de Assis

9 files changed, 2021 insertions, 20 deletions

diff --git a/nuttx/arch/arm/src/a1x/Make.defs b/nuttx/arch/arm/src/a1x/Make.defs
index 5e05df102..9acf9ab60 100644
--- a/nuttx/arch/arm/src/a1x/Make.defs
+++ b/nuttx/arch/arm/src/a1x/Make.defs
@@ -97,4 +97,4 @@ CHIP_ASRCS  =
 
 # A1x-specific C source files
 
-CHIP_CSRCS  = a1x_boot.c a1x_irq.c a1x_pio.c a1x_timerisr.c
+CHIP_CSRCS  = a1x_boot.c a1x_irq.c a1x_pio.c a1x_timerisr.c a1x_lowputc.c a1x_serial.c
diff --git a/nuttx/arch/arm/src/a1x/a1x_lowputc.c b/nuttx/arch/arm/src/a1x/a1x_lowputc.c
new file mode 100644
index 000000000..1c10464ba
--- /dev/null
+++ b/nuttx/arch/arm/src/a1x/a1x_lowputc.c
@@ -0,0 +1,289 @@
+/**************************************************************************
+ * arch/arm/src/a1x/a1x_lowputc.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "a1x_config.h"
+#include "chip/a1x_uart.h"
+#include "a1x_pio.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/* Select UART parameters for the selected console */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART0_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define CONSOLE_BITS     CONFIG_UART0_BITS
+#  define CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART1_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define CONSOLE_BITS     CONFIG_UART1_BITS
+#  define CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART2_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART2_BAUD
+#  define CONSOLE_BITS     CONFIG_UART2_BITS
+#  define CONSOLE_PARITY   CONFIG_UART2_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART2_2STOP
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART3_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART3_BAUD
+#  define CONSOLE_BITS     CONFIG_UART3_BITS
+#  define CONSOLE_PARITY   CONFIG_UART3_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART3_2STOP
+#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART4_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART4_BAUD
+#  define CONSOLE_BITS     CONFIG_UART4_BITS
+#  define CONSOLE_PARITY   CONFIG_UART4_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART4_2STOP
+#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART5_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART5_BAUD
+#  define CONSOLE_BITS     CONFIG_UART5_BITS
+#  define CONSOLE_PARITY   CONFIG_UART5_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART5_2STOP
+#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART6_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART6_BAUD
+#  define CONSOLE_BITS     CONFIG_UART6_BITS
+#  define CONSOLE_PARITY   CONFIG_UART6_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART6_2STOP
+#elif defined(CONFIG_UART7_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     A1X_UART7_VADDR
+#  define CONSOLE_BAUD     CONFIG_UART7_BAUD
+#  define CONSOLE_BITS     CONFIG_UART7_BITS
+#  define CONSOLE_PARITY   CONFIG_UART7_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART7_2STOP
+#elif defined(HAVE_SERIAL_CONSOLE)
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get word length setting for the console */
+
+#if CONSOLE_BITS == 5
+#  define CONSOLE_LCR_DLS UART_LCR_DLS_5BITS
+#elif CONSOLE_BITS == 6
+#  define CONSOLE_LCR_DLS UART_LCR_DLS_6BITS
+#elif CONSOLE_BITS == 7
+#  define CONSOLE_LCR_DLS UART_LCR_DLS_7BITS
+#elif CONSOLE_BITS == 8
+#  define CONSOLE_LCR_DLS UART_LCR_DLS_8BITS
+#elif defined(HAVE_SERIAL_CONSOLE)
+#  error "Invalid CONFIG_UARTn_BITS setting for console "
+#endif
+
+/* Get parity setting for the console */
+
+#if CONSOLE_PARITY == 0
+#  define CONSOLE_LCR_PAR 0
+#elif CONSOLE_PARITY == 1
+#  define CONSOLE_LCR_PAR UART_LCR_PEN
+#elif CONSOLE_PARITY == 2
+#  define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_EPS)
+#elif CONSOLE_PARITY == 3
+#elif defined(HAVE_SERIAL_CONSOLE)
+#    error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
+#endif
+
+/* Get stop-bit setting for the console and UART0-3 */
+
+#if CONSOLE_2STOP != 0
+#  define CONSOLE_LCR_STOP UART_LCR_STOP
+#else
+#  define CONSOLE_LCR_STOP 0
+#endif
+
+/* LCR and FCR values for the console */
+
+#define CONSOLE_LCR_VALUE (CONSOLE_LCR_DLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
+#define CONSOLE_FCR_VALUE (UART_FCR_RT_HALF | UART_FCR_XFIFOR |\
+                           UART_FCR_RFIFOR | UART_FCR_FIFOE)
+
+/* SCLK is the UART input clock */
+
+#define A1X_SCLK 0
+#warning What is the correct value of SCLK
+
+/* The output baud rate is equal to the serial clock (SCLK) frequency divided
+ * by sixteen times the value of the baud rate divisor, as follows:
+ *
+ * baud rate = Fsclk / (16 * divisor).
+ */
+
+#define CONSOLE_DL (A1X_SCLK / (CONSOLE_BAUD << 4))
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE
+  /* Wait for the transmitter to be available */
+
+  while ((getreg32(CONSOLE_BASE+A1X_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
+
+  /* Send the character */
+
+  putreg32((uint32_t)ch, CONSOLE_BASE+A1X_UART_THR_OFFSET);
+#endif
+}
+
+/**************************************************************************
+ * Name: a1x_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output available as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void a1x_lowsetup(void)
+{
+#ifdef HAVE_UART_DEVICE
+  /* Enable power and clocking to the UART peripheral */
+#warning Missing logic
+
+  /* Configure UART pins for the selected CONSOLE.  If there are multiple
+   * pin options for a given UART, the the applicable option must be
+   * disambiguated in the board.h header file.
+   */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART0_TX);
+  a1x_pio_config(PIO_UART0_RX);
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART1_TX);
+  a1x_pio_config(PIO_UART1_RX);
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART2_TX);
+  a1x_pio_config(PIO_UART2_RX);
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART3_TX);
+  a1x_pio_config(PIO_UART3_RX);
+#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART4_TX);
+  a1x_pio_config(PIO_UART4_RX);
+#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART5_TX);
+  a1x_pio_config(PIO_UART5_RX);
+#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART6_TX);
+  a1x_pio_config(PIO_UART6_RX);
+#elif defined(CONFIG_UART7_SERIAL_CONSOLE)
+  a1x_pio_config(PIO_UART7_TX);
+  a1x_pio_config(PIO_UART7_RX);
+#endif
+
+  /* Configure the console (only) */
+
+#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+
+  /* Clear fifos */
+
+  putreg32(UART_FCR_RFIFOR|UART_FCR_XFIFOR, CONSOLE_BASE+A1X_UART_FCR_OFFSET);
+
+  /* Set trigger */
+
+  putreg32(UART_FCR_FIFOE|UART_FCR_RT_HALF, CONSOLE_BASE+A1X_UART_FCR_OFFSET);
+
+  /* Set up the LCR and set DLAB=1 */
+
+  putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+A1X_UART_LCR_OFFSET);
+
+  /* Set the BAUD divisor */
+
+  putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+A1X_UART_DLH_OFFSET);
+  putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+A1X_UART_DLL_OFFSET);
+
+  /* Clear DLAB */
+
+  putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+A1X_UART_LCR_OFFSET);
+
+  /* Configure the FIFOs */
+
+  putreg32(UART_FCR_RT_HALF|UART_FCR_XFIFOR|UART_FCR_RFIFOR|UART_FCR_FIFOE,
+           CONSOLE_BASE+A1X_UART_FCR_OFFSET);
+#endif
+#endif /* HAVE_UART_DEVICE */
+}
diff --git a/nuttx/arch/arm/src/a1x/a1x_lowputc.h b/nuttx/arch/arm/src/a1x/a1x_lowputc.h
index 7c04a4468..720785d58 100644
--- a/nuttx/arch/arm/src/a1x/a1x_lowputc.h
+++ b/nuttx/arch/arm/src/a1x/a1x_lowputc.h
@@ -41,14 +41,6 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "up_internal.h"
-#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -59,16 +51,11 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Inline Functions
+ * Public Data
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
 extern "C"
diff --git a/nuttx/arch/arm/src/a1x/a1x_pio.c b/nuttx/arch/arm/src/a1x/a1x_pio.c
index 8ec035095..cd1167b34 100644
--- a/nuttx/arch/arm/src/a1x/a1x_pio.c
+++ b/nuttx/arch/arm/src/a1x/a1x_pio.c
@@ -209,14 +209,14 @@ void a1x_pio_irqinitialize(void)
 #endif
 
 /****************************************************************************
- * Name: a1x_configpio
+ * Name: a1x_pio_config
  *
  * Description:
  *   Configure a PIO pin based on bit-encoded description of the pin.
  *
  ****************************************************************************/
 
-int a1x_configpio(pio_pinset_t cfgset)
+int a1x_pio_config(pio_pinset_t cfgset)
 {
   unsigned int port = a1x_pio_port(cfgset);
   unsigned int pin  = a1x_pio_pin(cfgset);
diff --git a/nuttx/arch/arm/src/a1x/a1x_pio.h b/nuttx/arch/arm/src/a1x/a1x_pio.h
index be6636d3b..6a1c2fdcc 100644
--- a/nuttx/arch/arm/src/a1x/a1x_pio.h
+++ b/nuttx/arch/arm/src/a1x/a1x_pio.h
@@ -50,7 +50,7 @@
 /************************************************************************************
  * Definitions
  ************************************************************************************/
-/* Bit-encoded input to a1x_configpio() ********************************************/
+/* Bit-encoded input to a1x_pio_config() ********************************************/
 
 /* 32-bit Encoding:
  *
@@ -258,14 +258,14 @@ void a1x_pio_irqinitialize(void);
 #endif
 
 /************************************************************************************
- * Name: a1x_configpio
+ * Name: a1x_pio_config
  *
  * Description:
  *   Configure a PIO pin based on bit-encoded description of the pin.
  *
  ************************************************************************************/
 
-int a1x_configpio(pio_pinset_t cfgset);
+int a1x_pio_config(pio_pinset_t cfgset);
 
 /************************************************************************************
  * Name: a1x_pio_write
diff --git a/nuttx/arch/arm/src/a1x/a1x_serial.c b/nuttx/arch/arm/src/a1x/a1x_serial.c
new file mode 100644
index 000000000..4432cca78
--- /dev/null
+++ b/nuttx/arch/arm/src/a1x/a1x_serial.c
@@ -0,0 +1,1644 @@
+/****************************************************************************
+ * arch/arm/src/a1x/a1x_serial.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#ifdef CONFIG_SERIAL_TERMIOS
+#  include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/serial.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+#include "chip.h"
+#include "chip/a1x_uart.h"
+#include "a1x_pio.h"
+#include "a1x_serial.h"
+
+/****************************************************************************
+ * Pre-processor definitions
+ ****************************************************************************/
+
+/* If we are not using the serial driver for the console, then we still must
+ * provide some minimal implementation of up_putc.
+ */
+
+#if defined(USE_SERIALDRIVER) && defined(HAVE_UART_DEVICE)
+
+/* SCLK is the UART input clock */
+
+#define A1X_SCLK 0
+#warning What is the correct value of SCLK
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint32_t uartbase;  /* Base address of UART registers */
+  uint32_t baud;      /* Configured baud */
+  uint32_t ier;       /* Saved IER value */
+  uint8_t  irq;       /* IRQ associated with this UART */
+  uint8_t  parity;    /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;      /* Number of bits (7 or 8) */
+  bool     stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context);
+static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+static const struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_A1X_UART0
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART2
+static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART3
+static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
+static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART4
+static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
+static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART5
+static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
+static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART6
+static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE];
+static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_A1X_UART7
+static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE];
+static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE];
+#endif
+
+/* This describes the state of the A1X UART0 port. */
+
+#ifdef CONFIG_A1X_UART0
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = A1X_UART0_VADDR,
+  .baud           = CONFIG_UART0_BAUD,
+  .irq            = A1X_IRQ_UART0,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+#endif
+
+/* This describes the state of the A1X UART1 port. */
+
+#ifdef CONFIG_A1X_UART1
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = A1X_UART1_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .irq            = A1X_IRQ_UART1,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+#endif
+
+/* This describes the state of the A1X UART2 port. */
+
+#ifdef CONFIG_A1X_UART2
+static struct up_dev_s g_uart2priv =
+{
+  .uartbase       = A1X_UART2_BASE,
+  .baud           = CONFIG_UART2_BAUD,
+  .irq            = A1X_IRQ_UART2,
+  .parity         = CONFIG_UART2_PARITY,
+  .bits           = CONFIG_UART2_BITS,
+  .stopbits2      = CONFIG_UART2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART2_RXBUFSIZE,
+    .buffer = g_uart2rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART2_TXBUFSIZE,
+    .buffer = g_uart2txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart2priv,
+};
+#endif
+
+/* This describes the state of the A1X UART3 port. */
+
+#ifdef CONFIG_A1X_UART3
+static struct up_dev_s g_uart3priv =
+{
+  .uartbase       = A1X_UART3_BASE,
+  .baud           = CONFIG_UART3_BAUD,
+  .irq            = A1X_IRQ_UART3,
+  .parity         = CONFIG_UART3_PARITY,
+  .bits           = CONFIG_UART3_BITS,
+  .stopbits2      = CONFIG_UART3_2STOP,
+};
+
+static uart_dev_t g_uart3port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART3_RXBUFSIZE,
+    .buffer = g_uart3rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART3_TXBUFSIZE,
+    .buffer = g_uart3txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart3priv,
+};
+#endif
+
+/* This describes the state of the A1X UART4 port. */
+
+#ifdef CONFIG_A1X_UART4
+static struct up_dev_s g_uart4priv =
+{
+  .uartbase       = A1X_UART4_BASE,
+  .baud           = CONFIG_UART4_BAUD,
+  .irq            = A1X_IRQ_UART4,
+  .parity         = CONFIG_UART4_PARITY,
+  .bits           = CONFIG_UART4_BITS,
+  .stopbits2      = CONFIG_UART4_2STOP,
+};
+
+static uart_dev_t g_uart4port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART4_RXBUFSIZE,
+    .buffer = g_uart4rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART4_TXBUFSIZE,
+    .buffer = g_uart4txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart4priv,
+};
+#endif
+
+/* This describes the state of the A1X UART5 port. */
+
+#ifdef CONFIG_A1X_UART5
+static struct up_dev_s g_uart5priv =
+{
+  .uartbase       = A1X_UART5_BASE,
+  .baud           = CONFIG_UART5_BAUD,
+  .irq            = A1X_IRQ_UART5,
+  .parity         = CONFIG_UART5_PARITY,
+  .bits           = CONFIG_UART5_BITS,
+  .stopbits2      = CONFIG_UART5_2STOP,
+};
+
+static uart_dev_t g_uart5port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART5_RXBUFSIZE,
+    .buffer = g_uart5rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART5_TXBUFSIZE,
+    .buffer = g_uart5txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart5priv,
+};
+#endif
+
+/* This describes the state of the A1X UART6 port. */
+
+#ifdef CONFIG_A1X_UART6
+static struct up_dev_s g_uart6priv =
+{
+  .uartbase       = A1X_UART6_BASE,
+  .baud           = CONFIG_UART6_BAUD,
+  .irq            = A1X_IRQ_UART6,
+  .parity         = CONFIG_UART6_PARITY,
+  .bits           = CONFIG_UART6_BITS,
+  .stopbits2      = CONFIG_UART6_2STOP,
+};
+
+static uart_dev_t g_uart6port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART6_RXBUFSIZE,
+    .buffer = g_uart6rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART6_TXBUFSIZE,
+    .buffer = g_uart6txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart6priv,
+};
+#endif
+
+/* This describes the state of the A1X UART7 port. */
+
+#ifdef CONFIG_A1X_UART7
+static struct up_dev_s g_uart7priv =
+{
+  .uartbase       = A1X_UART7_BASE,
+  .baud           = CONFIG_UART7_BAUD,
+  .irq            = A1X_IRQ_UART7,
+  .parity         = CONFIG_UART7_PARITY,
+  .bits           = CONFIG_UART7_BITS,
+  .stopbits2      = CONFIG_UART7_2STOP,
+};
+
+static uart_dev_t g_uart7port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_UART7_RXBUFSIZE,
+    .buffer = g_uart7rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART7_TXBUFSIZE,
+    .buffer = g_uart7txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart7priv,
+};
+#endif
+
+/* Which UART with be tty0/console and which tty1-7?  The console will always
+ * be ttyS0.  If there is no console then will use the lowest numbered UART.
+ */
+
+/* First pick the console and ttys0.  This could be any of UART0-7 */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart0port /* UART0 is console */
+#    define TTYS0_DEV           g_uart0port /* UART0 is ttyS0 */
+#    define UART0_ASSIGNED      1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart1port /* UART1 is console */
+#    define TTYS0_DEV           g_uart1port /* UART1 is ttyS0 */
+#    define UART1_ASSIGNED      1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart2port /* UART2 is console */
+#    define TTYS0_DEV           g_uart2port /* UART2 is ttyS0 */
+#    define UART2_ASSIGNED      1
+#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart3port /* UART3 is console */
+#    define TTYS0_DEV           g_uart3port /* UART3 is ttyS0 */
+#    define UART3_ASSIGNED      1
+#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart4port /* UART4 is console */
+#    define TTYS0_DEV           g_uart4port /* UART4 is ttyS0 */
+#    define UART4_ASSIGNED      1
+#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart5port /* UART5 is console */
+#    define TTYS5_DEV           g_uart5port /* UART5 is ttyS0 */
+#    define UART5_ASSIGNED      1
+#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart6port /* UART6 is console */
+#    define TTYS5_DEV           g_uart6port /* UART6 is ttyS0 */
+#    define UART6_ASSIGNED      1
+#elif defined(CONFIG_UART7_SERIAL_CONSOLE)
+#    define CONSOLE_DEV         g_uart7port /* UART7 is console */
+#    define TTYS5_DEV           g_uart7port /* UART7 is ttyS0 */
+#    define UART7_ASSIGNED      1
+#else
+#  undef CONSOLE_DEV                        /* No console */
+#  if defined(CONFIG_KINETIS_UART0)
+#    define TTYS0_DEV           g_uart0port /* UART0 is ttyS0 */
+#    define UART0_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART1)
+#    define TTYS0_DEV           g_uart1port /* UART1 is ttyS0 */
+#    define UART1_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART2)
+#    define TTYS0_DEV           g_uart2port /* UART2 is ttyS0 */
+#    define UART2_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART3)
+#    define TTYS0_DEV           g_uart3port /* UART3 is ttyS0 */
+#    define UART3_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART4)
+#    define TTYS0_DEV           g_uart4port /* UART4 is ttyS0 */
+#    define UART4_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART5)
+#    define TTYS0_DEV           g_uart5port /* UART5 is ttyS0 */
+#    define UART5_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART6)
+#    define TTYS0_DEV           g_uart6port /* UART6 is ttyS0 */
+#    define UART6_ASSIGNED      1
+#  elif defined(CONFIG_KINETIS_UART7)
+#    define TTYS0_DEV           g_uart7port /* UART7 is ttyS0 */
+#    define UART7_ASSIGNED      1
+#  endif
+#endif
+
+/* Pick ttys1.  This could be any of UART0-7 excluding the console UART. */
+
+#if defined(CONFIG_KINETIS_UART0) && !defined(UART0_ASSIGNED)
+#  define TTYS1_DEV           g_uart0port /* UART0 is ttyS1 */
+#  define UART0_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART1) && !defined(UART1_ASSIGNED)
+#  define TTYS1_DEV           g_uart1port /* UART1 is ttyS1 */
+#  define UART1_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART2) && !defined(UART2_ASSIGNED)
+#  define TTYS1_DEV           g_uart2port /* UART2 is ttyS1 */
+#  define UART2_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART3) && !defined(UART3_ASSIGNED)
+#  define TTYS1_DEV           g_uart3port /* UART3 is ttyS1 */
+#  define UART3_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART4) && !defined(UART4_ASSIGNED)
+#  define TTYS1_DEV           g_uart4port /* UART4 is ttyS1 */
+#  define UART4_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART5) && !defined(UART5_ASSIGNED)
+#  define TTYS1_DEV           g_uart5port /* UART5 is ttyS1 */
+#  define UART5_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS1_DEV           g_uart6port /* UART6 is ttyS1 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS1_DEV           g_uart7port /* UART7 is ttyS1 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/* Pick ttys2.  This could be one of UART1-7. It can't be UART0 because that
+ * was either assigned as ttyS0 or ttys1.  One of UART 1-7 could also be the
+ * console.
+ */
+
+#if defined(CONFIG_KINETIS_UART1) && !defined(UART1_ASSIGNED)
+#  define TTYS2_DEV           g_uart1port /* UART1 is ttyS2 */
+#  define UART1_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART2) && !defined(UART2_ASSIGNED)
+#  define TTYS2_DEV           g_uart2port /* UART2 is ttyS2 */
+#  define UART2_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART3) && !defined(UART3_ASSIGNED)
+#  define TTYS2_DEV           g_uart3port /* UART3 is ttyS2 */
+#  define UART3_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART4) && !defined(UART4_ASSIGNED)
+#  define TTYS2_DEV           g_uart4port /* UART4 is ttyS2 */
+#  define UART4_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART5) && !defined(UART5_ASSIGNED)
+#  define TTYS2_DEV           g_uart5port /* UART5 is ttyS2 */
+#  define UART5_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS2_DEV           g_uart6port /* UART6 is ttyS2 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS2_DEV           g_uart7port /* UART7 is ttyS2 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/* Pick ttys3. This could be one of UART2-7. It can't be UART0-1 because
+ * those have already been assigned to ttsyS0, 1, or 2.  One of
+ * UART 2-7 could also be the console.
+ */
+
+#if defined(CONFIG_KINETIS_UART2) && !defined(UART2_ASSIGNED)
+#  define TTYS3_DEV           g_uart2port /* UART2 is ttyS3 */
+#  define UART2_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART3) && !defined(UART3_ASSIGNED)
+#  define TTYS3_DEV           g_uart3port /* UART3 is ttyS3 */
+#  define UART3_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART4) && !defined(UART4_ASSIGNED)
+#  define TTYS3_DEV           g_uart4port /* UART4 is ttyS3 */
+#  define UART4_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART5) && !defined(UART5_ASSIGNED)
+#  define TTYS3_DEV           g_uart5port /* UART5 is ttyS3 */
+#  define UART5_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS3_DEV           g_uart6port /* UART6 is ttyS3 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS3_DEV           g_uart7port /* UART7 is ttyS3 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/* Pick ttys4. This could be one of UART3-7. It can't be UART0-2 because
+ * those have already been assigned to ttsyS0, 1, 2 or 3.  One of
+ * UART 3-7 could also be the console.
+ */
+
+#if defined(CONFIG_KINETIS_UART3) && !defined(UART3_ASSIGNED)
+#  define TTYS4_DEV           g_uart3port /* UART3 is ttyS4 */
+#  define UART3_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART4) && !defined(UART4_ASSIGNED)
+#  define TTYS4_DEV           g_uart4port /* UART4 is ttyS4 */
+#  define UART4_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART5) && !defined(UART5_ASSIGNED)
+#  define TTYS4_DEV           g_uart5port /* UART5 is ttyS4 */
+#  define UART5_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS4_DEV           g_uart6port /* UART6 is ttyS4 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS4_DEV           g_uart7port /* UART7 is ttyS4 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/* Pick ttys5. This could be one of UART4-7. It can't be UART0-3 because
+ * those have already been assigned to ttsyS0, 1, 2, 3 or 4.  One of
+ * UART 4-7 could also be the console.
+ */
+
+#if defined(CONFIG_KINETIS_UART4) && !defined(UART4_ASSIGNED)
+#  define TTYS5_DEV           g_uart4port /* UART4 is ttyS5 */
+#  define UART4_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART5) && !defined(UART5_ASSIGNED)
+#  define TTYS5_DEV           g_uart5port /* UART5 is ttyS5 */
+#  define UART5_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS5_DEV           g_uart6port /* UART6 is ttyS5 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS5_DEV           g_uart7port /* UART7 is ttyS5 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/* Pick ttys6. This could be one of UART5-7. It can't be UART0-4 because
+ * those have already been assigned to ttsyS0, 1, 2, 3, 4, or 5.  One of
+ * UART 5-7 could also be the console.
+ */
+
+#if defined(CONFIG_KINETIS_UART5) && !defined(UART5_ASSIGNED)
+#  define TTYS6_DEV           g_uart5port /* UART5 is ttyS6 */
+#  define UART5_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS6_DEV           g_uart6port /* UART6 is ttyS6 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS6_DEV           g_uart7port /* UART7 is ttyS6 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/* Pick ttys7. This could be one of UART6-7. It can't be UART0-5 because
+ * those have already been assigned to ttsyS0, 1, 2, 3, 4, 5, or 6.  One of
+ * UART 6-7 could also be the console.
+ */
+
+#if defined(CONFIG_KINETIS_UART6) && !defined(UART6_ASSIGNED)
+#  define TTYS7_DEV           g_uart6port /* UART6 is ttyS7 */
+#  define UART6_ASSIGNED      1
+#elif defined(CONFIG_KINETIS_UART7) && !defined(UART7_ASSIGNED)
+#  define TTYS7_DEV           g_uart7port /* UART7 is ttyS7 */
+#  define UART7_ASSIGNED      1
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier)
+{
+  if (ier)
+    {
+      *ier = priv->ier & UART_IER_ALLIE;
+    }
+
+  priv->ier &= ~UART_IER_ALLIE;
+  up_serialout(priv, A1X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier)
+{
+  priv->ier |= ier & UART_IER_ALLIE;
+  up_serialout(priv, A1X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_enablebreaks
+ ****************************************************************************/
+
+static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
+{
+  uint32_t lcr = up_serialin(priv, A1X_UART_LCR_OFFSET);
+
+  if (enable)
+    {
+      lcr |= UART_LCR_BC;
+    }
+  else
+    {
+      lcr &= ~UART_LCR_BC;
+    }
+
+  up_serialout(priv, A1X_UART_LCR_OFFSET, lcr);
+}
+
+/************************************************************************************
+ * Name: a1x_uart0config, uart1config, uart2config, ..., uart7config
+ *
+ * Descrption:
+ *   Configure the UART
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_A1X_UART0
+static inline void a1x_uart0config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART0 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART0 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART0_TX);
+  a1x_pio_config(PIO_UART0_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART1
+static inline void a1x_uart1config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART1 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART1 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART1_TX);
+  a1x_pio_config(PIO_UART1_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART2
+static inline void a1x_uart2config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART2 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking on UART2 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART2_TX);
+  a1x_pio_config(PIO_UART2_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART3
+static inline void a1x_uart3config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART3 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART3 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART3_TX);
+  a1x_pio_config(PIO_UART3_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART4
+static inline void a1x_uart4config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART4 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART4 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART4_TX);
+  a1x_pio_config(PIO_UART4_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART5
+static inline void a1x_uart5config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART5 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART5 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART5_TX);
+  a1x_pio_config(PIO_UART5_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART6
+static inline void a1x_uart6config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART6 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART6 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART6_TX);
+  a1x_pio_config(PIO_UART6_RX);
+  irqrestore(flags);
+};
+#endif
+
+#ifdef CONFIG_A1X_UART7
+static inline void a1x_uart7config(void)
+{
+  uint32_t   regval;
+  irqstate_t flags;
+
+  /* Step 1: Enable power to UART7 */
+
+  flags   = irqsave();
+#warning Missing logic
+
+  /* Step 2: Enable clocking to UART7 */
+#warning Missing logic
+
+  /* Step 3: Configure I/O pins */
+
+  a1x_pio_config(PIO_UART7_TX);
+  a1x_pio_config(PIO_UART7_RX);
+  irqrestore(flags);
+};
+#endif
+
+/************************************************************************************
+ * Name: a1x_uartdl
+ *
+ * Descrption:
+ *   Select a divider to produce the BAUD from the UART PCLK.
+ *
+ *     BAUD = PCLK / (16 * DL), or
+ *     DL   = PCLK / BAUD / 16
+ *
+ ************************************************************************************/
+
+static inline uint32_t a1x_uartdl(uint32_t baud)
+{
+  return A1X_SCLK / (baud << 4);
+}
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This method is
+ *   called the first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifndef CONFIG_SUPPRESS_A1X_UART_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint16_t dl;
+  uint32_t lcr;
+
+  /* Clear fifos */
+
+  up_serialout(priv, A1X_UART_FCR_OFFSET, (UART_FCR_RFIFOR|UART_FCR_XFIFOR));
+
+  /* Set trigger */
+
+  up_serialout(priv, A1X_UART_FCR_OFFSET, (UART_FCR_FIFOE|UART_FCR_RT_HALF));
+
+  /* Set up the IER */
+
+  priv->ier = up_serialin(priv, A1X_UART_IER_OFFSET);
+
+  /* Set up the LCR */
+
+  lcr = 0;
+
+  switch (priv->bits)
+    {
+    case 5:
+      lcr |= UART_LCR_DLS_5BITS;
+      break;
+
+    case 6:
+      lcr |= UART_LCR_DLS_6BITS;
+      break;
+
+    case 7:
+      lcr |= UART_LCR_DLS_7BITS;
+      break;
+
+    case 8:
+    default:
+      lcr |= UART_LCR_DLS_8BITS;
+      break;
+    }
+
+  if (priv->stopbits2)
+    {
+      lcr |= UART_LCR_STOP;
+    }
+
+  if (priv->parity == 1)
+    {
+      lcr |= UART_LCR_PEN;
+    }
+  else if (priv->parity == 2)
+    {
+      lcr |= (UART_LCR_PEN|UART_LCR_EPS);
+    }
+
+  /* Enter DLAB=1 */
+
+  up_serialout(priv, A1X_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
+
+  /* Set the BAUD divisor */
+
+  dl = a1x_uartdl(priv->baud);
+  up_serialout(priv, A1X_UART_DLH_OFFSET, dl >> 8);
+  up_serialout(priv, A1X_UART_DLL_OFFSET, dl & 0xff);
+
+  /* Clear DLAB */
+
+  up_serialout(priv, A1X_UART_LCR_OFFSET, lcr);
+
+  /* Configure the FIFOs */
+
+  up_serialout(priv, A1X_UART_FCR_OFFSET,
+               (UART_FCR_RT_HALF|UART_FCR_XFIFOR|UART_FCR_RFIFOR|UART_FCR_FIFOE));
+
+  /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */
+  
+#if defined(CONFIG_UART1_IFLOWCONTROL) || defined(CONFIG_UART1_OFLOWCONTROL)
+  if (priv->uartbase == A1X_UART1_BASE)
+    {
+#if defined(CONFIG_UART1_IFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
+      up_serialout(priv, A1X_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN));
+#elif defined(CONFIG_UART1_IFLOWCONTROL)
+      up_serialout(priv, A1X_UART_MCR_OFFSET, UART_MCR_RTSEN);
+#else
+      up_serialout(priv, A1X_UART_MCR_OFFSET, UART_MCR_CTSEN);
+#endif
+    }
+#endif
+
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt);
+  if (ret == OK)
+    {
+       /* Enable the interrupt (RX and TX interrupts are still disabled
+        * in the UART
+        */
+
+       up_enable_irq(priv->irq);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception is
+ *   the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked when an
+ *   interrupt received on the 'irq'  It should call uart_transmitchars or
+ *   uart_receivechar to perform the appropriate data transfers.  The
+ *   interrupt handling logic must be able to map the 'irq' number into the
+ *   appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint32_t           status;
+  int                passes;
+
+#ifdef CONFIG_A1X_UART0
+  if (g_uart0priv.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+#endif
+#ifdef CONFIG_A1X_UART1
+  if (g_uart1priv.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else
+#endif
+#ifdef CONFIG_A1X_UART2
+  if (g_uart2priv.irq == irq)
+    {
+      dev = &g_uart2port;
+    }
+  else
+#endif
+#ifdef CONFIG_A1X_UART3
+  if (g_uart3priv.irq == irq)
+    {
+      dev = &g_uart3port;
+    }
+  else
+#endif
+    {
+      PANIC();
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for (passes = 0; passes < 256; passes++)
+    {
+      /* Get the current UART status */
+
+      status = up_serialin(priv, A1X_UART_IIR_OFFSET);
+
+      /* Handle the interrupt by its interrupt ID field */
+
+      switch (status & UART_IIR_IID_MASK)
+        {
+          /* Handle incoming, receive bytes (with or without timeout) */
+
+          case UART_IIR_IID_RECV:
+          case UART_IIR_IID_TIMEOUT:
+            {
+              uart_recvchars(dev);
+              break;
+            }
+
+          /* Handle outgoing, transmit bytes */
+
+          case UART_IIR_IID_TXEMPTY:
+            {
+              uart_xmitchars(dev);
+              break;
+            }
+
+          /* Just clear modem status interrupts (UART1 only) */
+
+          case UART_IIR_IID_MODEM:
+            {
+              /* Read the modem status register (MSR) to clear */
+
+              status = up_serialin(priv, A1X_UART_MSR_OFFSET);
+              vdbg("MSR: %02x\n", status);
+              break;
+            }
+
+          /* Just clear any line status interrupts */
+
+          case UART_IIR_IID_LINESTATUS:
+            {
+              /* Read the line status register (LSR) to clear */
+
+              status = up_serialin(priv, A1X_UART_LSR_OFFSET);
+              vdbg("LSR: %02x\n", status);
+              break;
+            }
+
+          /* Otherwise, there is no (handled) interrupt pending */
+
+          case UART_IIR_IID_NONE:
+          default:
+            {
+              dbg("Unexpected IIR: %02x\n", status);
+              break;
+            }
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+    case TIOCSERGSTRUCT:
+      {
+        struct up_dev_s *user = (struct up_dev_s*)arg;
+        if (!user)
+          {
+            ret = -EINVAL;
+          }
+        else
+          {
+            memcpy(user, dev, sizeof(struct up_dev_s));
+          }
+      }
+      break;
+#endif
+
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags = irqsave();
+        up_enablebreaks(priv, true);
+        irqrestore(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+        flags = irqsave();
+        up_enablebreaks(priv, false);
+        irqrestore(flags);
+      }
+      break;
+
+#ifdef CONFIG_SERIAL_TERMIOS
+    case TCGETS:
+      {
+        struct termios *termiosp = (struct termios*)arg;
+
+        if (!termiosp)
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        /* TODO:  Other termios fields are not yet returned.
+         * Note that cfsetospeed is not necessary because we have
+         * knowledge that only one speed is supported.
+         * Both cfset(i|o)speed() translate to cfsetspeed.
+         */
+
+        cfsetispeed(termiosp, priv->baud);
+      }
+      break;
+
+    case TCSETS:
+      {
+        struct termios *termiosp = (struct termios*)arg;
+        uint32_t           lcr;  /* Holds current values of line control register */
+        uint16_t           dl;   /* Divisor latch */
+
+        if (!termiosp)
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        /* TODO:  Handle other termios settings.
+         * Note that only cfgetispeed is used because we have knowledge
+         * that only one speed is supported.
+         */
+
+        /* Get the c_speed field in the termios struct */
+
+        priv->baud = cfgetispeed(termiosp);
+
+        /* TODO: Re-calculate the optimal CCLK divisor for the new baud and
+         * and reset the divider in the CLKSEL0/1 register.
+         */
+
+        /* DLAB open latch */
+        /* REVISIT:  Shouldn't we just call up_setup() to do all of the following? */
+
+        lcr = getreg32(priv->uartbase + A1X_UART_LCR_OFFSET);
+        up_serialout(priv, A1X_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
+
+        /* Set the BAUD divisor */
+
+        dl = a1x_uartdl(priv->baud);
+        up_serialout(priv, A1X_UART_DLH_OFFSET, dl >> 8);
+        up_serialout(priv, A1X_UART_DLL_OFFSET, dl & 0xff);
+
+        /* Clear DLAB */
+
+        up_serialout(priv, A1X_UART_LCR_OFFSET, lcr);
+      }
+      break;
+#endif
+
+    default:
+      ret = -ENOTTY;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32_t *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32_t rbr;
+
+  *status = up_serialin(priv, A1X_UART_LSR_OFFSET);
+  rbr     = up_serialin(priv, A1X_UART_RBR_OFFSET);
+  return rbr;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= UART_IER_ERBFI;
+#endif
+    }
+  else
+    {
+      priv->ier &= ~UART_IER_ERBFI;
+    }
+
+  up_serialout(priv, A1X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, A1X_UART_LSR_OFFSET) & UART_LSR_DR) != 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, A1X_UART_THR_OFFSET, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  flags = irqsave();
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= UART_IER_PTIME;
+      up_serialout(priv, A1X_UART_IER_OFFSET, priv->ier);
+
+      /* Fake a TX interrupt here by just calling uart_xmitchars() with
+       * interrupts disabled (note this may recurse).
+       */
+
+      uart_xmitchars(dev);
+#endif
+    }
+  else
+    {
+      priv->ier &= ~UART_IER_PTIME;
+      up_serialout(priv, A1X_UART_IER_OFFSET, priv->ier);
+    }
+
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, A1X_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return true if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, A1X_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
+}
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ *   NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
+ *   very early in the boot sequence.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
+
+#ifdef CONFIG_A1X_UART0
+#ifndef CONFIG_UART0_SERIAL_CONSOLE
+  a1x_uart0config();
+#endif
+  up_disableuartint(&g_uart0priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART1
+#ifndef CONFIG_UART1_SERIAL_CONSOLE
+  a1x_uart1config();
+#else
+#endif
+  up_disableuartint(&g_uart1priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART2
+#ifndef CONFIG_UART2_SERIAL_CONSOLE
+  a1x_uart2config();
+#endif
+  up_disableuartint(&g_uart2priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART3
+#ifndef CONFIG_UART3_SERIAL_CONSOLE
+  a1x_uart3config();
+#endif
+  up_disableuartint(&g_uart3priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART4
+#ifndef CONFIG_UART4_SERIAL_CONSOLE
+  a1x_uart4config();
+#endif
+  up_disableuartint(&g_uart4priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART5
+#ifndef CONFIG_UART5_SERIAL_CONSOLE
+  a1x_uart5config();
+#endif
+  up_disableuartint(&g_uart5priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART6
+#ifndef CONFIG_UART6_SERIAL_CONSOLE
+  a1x_uart6config();
+#endif
+  up_disableuartint(&g_uart6priv, NULL);
+#endif
+
+#ifdef CONFIG_A1X_UART7
+#ifndef CONFIG_UART7_SERIAL_CONSOLE
+  a1x_uart7config();
+#endif
+  up_disableuartint(&g_uart7priv, NULL);
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef CONSOLE_DEV
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes that
+ *   up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+#ifdef CONSOLE_DEV
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+#ifdef TTYS0_DEV
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+#ifdef TTYS3_DEV
+  (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+#endif
+#ifdef TTYS4_DEV
+  (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+#endif
+#ifdef TTYS5_DEV
+  (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+#endif
+#ifdef TTYS6_DEV
+  (void)uart_register("/dev/ttyS6", &TTYS6_DEV);
+#endif
+#ifdef TTYS7_DEV
+  (void)uart_register("/dev/ttyS7", &TTYS7_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint32_t ier;
+  up_disableuartint(priv, &ier);
+#endif
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#ifdef HAVE_SERIAL_CONSOLE
+  up_restoreuartint(priv, ier);
+#endif
+
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_UART_DEVICE
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/nuttx/arch/arm/src/a1x/a1x_serial.h b/nuttx/arch/arm/src/a1x/a1x_serial.h
new file mode 100644
index 000000000..47957ac12
--- /dev/null
+++ b/nuttx/arch/arm/src/a1x/a1x_serial.h
@@ -0,0 +1,79 @@
+/************************************************************************************
+ * arch/arm/src/a1x/a1x_serial.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_A1X_A1X_SERIAL_H
+#define __ARCH_ARM_SRC_A1X_A1X_SERIAL_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/board/board.h>
+
+#include "chip/a1x_uart.h"
+
+#include "a1x_config.h"
+#include "a1x_pio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration *********************************************************************/
+
+/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
+ * much accuracy.  This following is a "fudge factor" that represents the minimum
+ * value of the divisor that we will permit.
+ */
+
+#define UART_MINDL 32
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_A1X_A1X_SERIAL_H */
diff --git a/nuttx/arch/arm/src/a1x/chip/a1x_uart.h b/nuttx/arch/arm/src/a1x/chip/a1x_uart.h
index fe73e8233..d70069301 100755
--- a/nuttx/arch/arm/src/a1x/chip/a1x_uart.h
+++ b/nuttx/arch/arm/src/a1x/chip/a1x_uart.h
@@ -246,6 +246,7 @@
 #define UART_IER_ELSI             (1 << 2) /* Bit 2:  Enable Receiver Line Status Interrupt */
 #define UART_IER_EDSSI            (1 << 3) /* Bit 3:  Enable Modem Status Interrupt */
 #define UART_IER_PTIME            (1 << 7) /* Bit 7:  Programmable THRE Interrupt Mode Enable */
+#define UART_IER_ALLIE            0x0000008f
 
 /* UART Interrupt Identity Register */
 
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_serial.c b/nuttx/arch/arm/src/kinetis/kinetis_serial.c
index 5bce5060f..fc74f22ba 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_serial.c
+++ b/nuttx/arch/arm/src/kinetis/kinetis_serial.c
@@ -108,6 +108,7 @@
 #elif defined(CONFIG_UART5_SERIAL_CONSOLE)
 #    define CONSOLE_DEV         g_uart5port /* UART5 is console */
 #    define TTYS5_DEV           g_uart5port /* UART5 is ttyS0 */
+#    define UART5_ASSIGNED      1
 #else
 #  undef CONSOLE_DEV                        /* No console */
 #  if defined(CONFIG_KINETIS_UART0)