Fix all occurrences of "the the" in documentation and comments

39 files changed, 82 insertions, 82 deletions

diff --git a/nuttx/arch/arm/src/arm/up_head.S b/nuttx/arch/arm/src/arm/up_head.S
index d9f8166b2..f969b4f34 100644
--- a/nuttx/arch/arm/src/arm/up_head.S
+++ b/nuttx/arch/arm/src/arm/up_head.S
@@ -275,7 +275,7 @@ __start:
 	 * effect.  First populate the L1 table for the locked and paged
 	 * text regions.
 	 *
-	 * We could probably make the the pg_l1span and pg_l2map macros into
+	 * We could probably make the pg_l1span and pg_l2map macros into
 	 * call-able subroutines, but we would have to be carefully during
 	 * this phase while we are operating in a physical address space.
 	 *
diff --git a/nuttx/arch/arm/src/armv7-a/arm_pghead.S b/nuttx/arch/arm/src/armv7-a/arm_pghead.S
index 931217e3f..e3730745a 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_pghead.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_pghead.S
@@ -265,7 +265,7 @@ __start:
 	 * effect.  First populate the L1 table for the locked and paged
 	 * text regions.
 	 *
-	 * We could probably make the the pg_l1span and pg_l2map macros into
+	 * We could probably make the pg_l1span and pg_l2map macros into
 	 * call-able subroutines, but we would have to be carefully during
 	 * this phase while we are operating in a physical address space.
 	 *
diff --git a/nuttx/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S b/nuttx/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S
index b23f6af1a..044a441c0 100644
--- a/nuttx/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S
+++ b/nuttx/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S
@@ -75,7 +75,7 @@
  * Description:
  *   Shouldn't happen.  This exception handler is in a separate file from
  *   other vector handlers because some processors (e.g., Cortex-A5) do not
- *   support the the Address Exception vector.
+ *   support the Address Exception vector.
  *
  ****************************************************************************/
 
diff --git a/nuttx/arch/arm/src/armv7-a/cache.h b/nuttx/arch/arm/src/armv7-a/cache.h
index 19d385944..aa1c7c3f1 100644
--- a/nuttx/arch/arm/src/armv7-a/cache.h
+++ b/nuttx/arch/arm/src/armv7-a/cache.h
@@ -968,7 +968,7 @@ void cp15_clean_dcache(uintptr_t start, uintptr_t end);
  *
  * Description:
  *   Flush the data cache within the specified region by cleaning and
- *   invalidating the the D cache.
+ *   invalidating the D cache.
  *
  * Input Parameters:
  *   start - virtual start address of region
diff --git a/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S b/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S
index b73abf7d9..9ff8e1972 100755
--- a/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S
+++ b/nuttx/arch/arm/src/armv7-a/cp15_flush_dcache.S
@@ -76,7 +76,7 @@
  *
  * Description:
  *   Flush the data cache within the specified region by cleaning and
- *   invalidating the the D cache.
+ *   invalidating the D cache.
  *
  * Input Parameters:
  *   start - virtual start address of region
diff --git a/nuttx/arch/arm/src/armv7-m/ram_vectors.h b/nuttx/arch/arm/src/armv7-m/ram_vectors.h
index 90bcc30e6..5b228d69c 100644
--- a/nuttx/arch/arm/src/armv7-m/ram_vectors.h
+++ b/nuttx/arch/arm/src/armv7-m/ram_vectors.h
@@ -77,7 +77,7 @@
 /* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
  * ARM-specific implementations of irq_initialize(), irq_attach(), and
  * irq_dispatch.  In this case, it is also assumed that the ARM vector
- * table resides in RAM, has the the name up_ram_vectors, and has been
+ * table resides in RAM, has the name up_ram_vectors, and has been
  * properly positioned and aligned in memory by the linker script.
  */
 
diff --git a/nuttx/arch/arm/src/armv7-m/up_ramvec_initialize.c b/nuttx/arch/arm/src/armv7-m/up_ramvec_initialize.c
index 806bdf3fc..ee8ac43d0 100644
--- a/nuttx/arch/arm/src/armv7-m/up_ramvec_initialize.c
+++ b/nuttx/arch/arm/src/armv7-m/up_ramvec_initialize.c
@@ -65,7 +65,7 @@
 /* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
  * ARM-specific implementations of up_ramvec_initialize(), irq_attach(), and
  * irq_dispatch.  In this case, it is also assumed that the ARM vector
- * table resides in RAM, has the the name up_ram_vectors, and has been
+ * table resides in RAM, has the name up_ram_vectors, and has been
  * properly positioned and aligned in memory by the linker script.
  */
 
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_sdhc.c b/nuttx/arch/arm/src/kinetis/kinetis_sdhc.c
index eec5fba0e..4c392cbf8 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/nuttx/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -742,7 +742,7 @@ static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
  * Name: kinetis_datadisable
  *
  * Description:
- *   Disable the the SDIO data path setup by kinetis_dataconfig() and
+ *   Disable the SDIO data path setup by kinetis_dataconfig() and
  *   disable DMA.
  *
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_serial.c b/nuttx/arch/arm/src/kinetis/kinetis_serial.c
index f176f5fa0..5bce5060f 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_serial.c
+++ b/nuttx/arch/arm/src/kinetis/kinetis_serial.c
@@ -900,8 +900,8 @@ static int up_interrupts(int irq, void *context)
       if (count > 0)
 #else
       /* Check if the receive data register is full (RDRF).  NOTE:  If
-       * FIFOS are enabled, this does not mean that the the FIFO is full,
-       * rather, it means that the the number of bytes in the RX FIFO has
+       * FIFOS are enabled, this does not mean that the FIFO is full,
+       * rather, it means that the number of bytes in the RX FIFO has
        * exceeded the watermark setting.  There may actually be RX data
        * available!
        *
@@ -929,8 +929,8 @@ static int up_interrupts(int irq, void *context)
 #  error "Missing logic"
 #else
       /* Check if the transmit data register is "empty."  NOTE:  If FIFOS
-       * are enabled, this does not mean that the the FIFO is empty, rather,
-       * it means that the the number of bytes in the TX FIFO is below the
+       * are enabled, this does not mean that the FIFO is empty, rather,
+       * it means that the number of bytes in the TX FIFO is below the
        * watermark setting.  There could actually be space for additional TX
        * data.
        *
@@ -1090,8 +1090,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
   return count > 0;
 #else
   /* Return true if the receive data register is full (RDRF).  NOTE:  If
-   * FIFOS are enabled, this does not mean that the the FIFO is full,
-   * rather, it means that the the number of bytes in the RX FIFO has
+   * FIFOS are enabled, this does not mean that the FIFO is full,
+   * rather, it means that the number of bytes in the RX FIFO has
    * exceeded the watermark setting.  There may actually be RX data
    * available!
    */
@@ -1175,8 +1175,8 @@ static bool up_txready(struct uart_dev_s *dev)
 #  error "Missing logic"
 #else
   /* Return true if the transmit data register is "empty."  NOTE:  If
-   * FIFOS are enabled, this does not mean that the the FIFO is empty,
-   * rather, it means that the the number of bytes in the TX FIFO is
+   * FIFOS are enabled, this does not mean that the FIFO is empty,
+   * rather, it means that the number of bytes in the TX FIFO is
    * below the watermark setting.  There may actually be space for
    * additional TX data.
    */
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S
index 220c64053..8394ff916 100644
--- a/nuttx/arch/arm/src/kinetis/kinetis_vectors.S
+++ b/nuttx/arch/arm/src/kinetis/kinetis_vectors.S
@@ -626,7 +626,7 @@ kinetis_common:
 	sub		r1, #(4*SW_FPU_REGS)
 #endif
 
-	/* Save the the remaining registers on the stack after the registers pushed
+	/* Save the remaining registers on the stack after the registers pushed
 	 * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
 	 * r14=register values.
 	 */
diff --git a/nuttx/arch/arm/src/kl/kl_serial.c b/nuttx/arch/arm/src/kl/kl_serial.c
index a2f3918c7..10f4f7d6e 100644
--- a/nuttx/arch/arm/src/kl/kl_serial.c
+++ b/nuttx/arch/arm/src/kl/kl_serial.c
@@ -547,8 +547,8 @@ static int up_interrupts(int irq, void *context)
       s1 = up_serialin(priv, KL_UART_S1_OFFSET);
 
       /* Check if the receive data register is full (RDRF).  NOTE:  If
-       * FIFOS are enabled, this does not mean that the the FIFO is full,
-       * rather, it means that the the number of bytes in the RX FIFO has
+       * FIFOS are enabled, this does not mean that the FIFO is full,
+       * rather, it means that the number of bytes in the RX FIFO has
        * exceeded the watermark setting.  There may actually be RX data
        * available!
        *
@@ -567,8 +567,8 @@ static int up_interrupts(int irq, void *context)
       /* Handle outgoing, transmit bytes */
 
       /* Check if the transmit data register is "empty."  NOTE:  If FIFOS
-       * are enabled, this does not mean that the the FIFO is empty, rather,
-       * it means that the the number of bytes in the TX FIFO is below the
+       * are enabled, this does not mean that the FIFO is empty, rather,
+       * it means that the number of bytes in the TX FIFO is below the
        * watermark setting.  There could actually be space for additional TX
        * data.
        *
@@ -728,8 +728,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
 
   /* Return true if the receive data register is full (RDRF).  NOTE:  If
-   * FIFOS are enabled, this does not mean that the the FIFO is full,
-   * rather, it means that the the number of bytes in the RX FIFO has
+   * FIFOS are enabled, this does not mean that the FIFO is full,
+   * rather, it means that the number of bytes in the RX FIFO has
    * exceeded the watermark setting.  There may actually be RX data
    * available!
    */
@@ -804,8 +804,8 @@ static bool up_txready(struct uart_dev_s *dev)
   struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
 
   /* Return true if the transmit data register is "empty."  NOTE:  If
-   * FIFOS are enabled, this does not mean that the the FIFO is empty,
-   * rather, it means that the the number of bytes in the TX FIFO is
+   * FIFOS are enabled, this does not mean that the FIFO is empty,
+   * rather, it means that the number of bytes in the TX FIFO is
    * below the watermark setting.  There may actually be space for
    * additional TX data.
    */
diff --git a/nuttx/arch/arm/src/lm/lm_vectors.S b/nuttx/arch/arm/src/lm/lm_vectors.S
index 0f5a8e555..0a146d691 100644
--- a/nuttx/arch/arm/src/lm/lm_vectors.S
+++ b/nuttx/arch/arm/src/lm/lm_vectors.S
@@ -229,7 +229,7 @@ lm_irqcommon:
 	sub		r1, #(4*SW_FPU_REGS)
 #endif
 
-	/* Save the the remaining registers on the stack after the registers pushed
+	/* Save the remaining registers on the stack after the registers pushed
 	 * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
 	 * r14=register values.
 	 */
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
index 0241d4bf7..b6be03e50 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -2495,7 +2495,7 @@ static inline int lpc17_ethinitialize(int intf)
 #endif
   if (ret != 0)
     {
-      /* We could not attach the ISR to the the interrupt */
+      /* We could not attach the ISR to the interrupt */
 
       return -EAGAIN;
     }
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.c b/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.c
index 28a74deed..0fd719f24 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_sdcard.c
@@ -636,7 +636,7 @@ static void lpc17_setpwrctrl(uint32_t pwrctrl)
  *
  * Description:
  *   Return the current value of the  the PWRCTRL field of the SD card P
- *   register.  This function can be used to see the the SD card is power ON
+ *   register.  This function can be used to see if the SD card is powered ON
  *   or OFF
  *
  * Input Parameters:
@@ -908,7 +908,7 @@ static void lpc17_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
  * Name: lpc17_datadisable
  *
  * Description:
- *   Disable the the SD card data path setup by lpc17_dataconfig() and
+ *   Disable the SD card data path setup by lpc17_dataconfig() and
  *   disable DMA.
  *
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
index 569559079..66e76932d 100644
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
@@ -238,7 +238,7 @@ lpc17_common:
 	sub		r1, #(4*SW_FPU_REGS)
 #endif
 
-	/* Save the the remaining registers on the stack after the registers pushed
+	/* Save the remaining registers on the stack after the registers pushed
 	 * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
 	 * r14=register values.
 	 */
diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h b/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h
index a408f56b2..8aae207ed 100644
--- a/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h
+++ b/nuttx/arch/arm/src/lpc31xx/lpc31_cgudrvr.h
@@ -794,7 +794,7 @@ EXTERN uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid,
  * Name: lpc31_enableexten
  *
  * Description:
- *   Enable external enabling for the the specified possible clocks.
+ *   Enable external enabling for the specified possible clocks.
  *
  ************************************************************************/
 
@@ -804,7 +804,7 @@ EXTERN void lpc31_enableexten(enum lpc31_clockid_e clkid);
  * Name: lpc31_disableexten
  *
  * Description:
- *   Disable external enabling for the the specified possible clocks.
+ *   Disable external enabling for the specified possible clocks.
  *
  ************************************************************************/
 
diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c b/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c
index 20bd0c776..4ed0e5f73 100644
--- a/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c
+++ b/nuttx/arch/arm/src/lpc31xx/lpc31_clkexten.c
@@ -69,7 +69,7 @@
  * Name: lpc31_enableexten
  *
  * Description:
- *   Enable external enabling for the the specified possible clocks.
+ *   Enable external enabling for the specified possible clocks.
  *
  ****************************************************************************/
 
@@ -112,7 +112,7 @@ void lpc31_enableexten(enum lpc31_clockid_e clkid)
  * Name: lpc31_disableexten
  *
  * Description:
- *   Disable external enabling for the the specified possible clocks.
+ *   Disable external enabling for the specified possible clocks.
  *
  ****************************************************************************/
 
diff --git a/nuttx/arch/arm/src/lpc31xx/lpc31_softreset.c b/nuttx/arch/arm/src/lpc31xx/lpc31_softreset.c
index fcade115a..7deb33a24 100644
--- a/nuttx/arch/arm/src/lpc31xx/lpc31_softreset.c
+++ b/nuttx/arch/arm/src/lpc31xx/lpc31_softreset.c
@@ -84,7 +84,7 @@ void lpc31_softreset(enum lpc31_resetid_e resetid)
 
   for (i = 0;i < 1000; i++);
 
-  /* Then set the the soft reset bit */
+  /* Then set the soft reset bit */
 
   putreg32(CGU_SOFTRESET, address);
 }
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
index d5ab819dc..f42fda3c2 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.c
@@ -76,7 +76,7 @@
  *   Reset as many of the LPC43 peripherals as possible. This is necessary
  *   because the LPC43 does not provide any way of performing a full system
  *   reset under debugger control.  So, if CONFIG_DEBUG is set (indicating
- *   that a debugger is being used?), the the boot logic will call this 
+ *   that a debugger is being used?), the boot logic will call this
  *   function on all restarts.
  *
  * Assumptions:
@@ -93,7 +93,7 @@ void lpc43_softreset(void)
   /* Disable interrupts */
 
   flags = irqsave();
- 
+
   /* Reset all of the peripherals that we can (safely) */
 
   putreg32((RGU_CTRL0_LCD_RST     | RGU_CTRL0_USB0_RST     |
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h
index 364b4d066..80b56adde 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_rgu.h
@@ -76,7 +76,7 @@ extern "C" {
  *   Reset as many of the LPC43 peripherals as possible. This is necessary
  *   because the LPC43 does not provide any way of performing a full system
  *   reset under debugger control.  So, if CONFIG_DEBUG is set (indicating
- *   that a debugger is being used?), the the boot logic will call this 
+ *   that a debugger is being used?), the boot logic will call this
  *   function on all restarts.
  *
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
index bb9d8c6ab..8dc9f66b9 100644
--- a/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/nuttx/arch/arm/src/lpc43xx/lpc43_start.c
@@ -114,7 +114,7 @@ static inline void lpc43_setbootrom(void)
 
   putreg32(LPC43_ROM_BASE, LPC43_CREG_M4MEMMAP);
 
-  /* Address zero now maps to the Boot ROM.  Make sure the the VTOR will
+  /* Address zero now maps to the Boot ROM.  Make sure that the VTOR will
    * use the ROM vector table at that address.
    */
 
@@ -197,7 +197,7 @@ static inline void lpc43_fpuconfig(void)
    * with the volatile FP registers stacked above the basic context.
    */
 
-  regval = getcontrol(); 
+  regval = getcontrol();
   regval |= (1 << 2);
   setcontrol(regval);
 
@@ -227,7 +227,7 @@ static inline void lpc43_fpuconfig(void)
    * with the volatile FP registers stacked in the saved context.
    */
 
-  regval = getcontrol(); 
+  regval = getcontrol();
   regval &= ~(1 << 2);
   setcontrol(regval);
 
@@ -273,7 +273,7 @@ void __start(void)
   /* Reset as many of the LPC43 peripherals as possible. This is necessary
    * because the LPC43 does not provide any way of performing a full system
    * reset under debugger control.  So, if CONFIG_DEBUG is set (indicating
-   * that a debugger is being used?), the the boot logic will call this 
+   * that a debugger is being used?), the boot logic will call this
    * function on all restarts.
    */
 
diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c b/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c
index 366226a8c..95f1ff143 100644
--- a/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c
+++ b/nuttx/arch/arm/src/nuc1xx/nuc_gpio.c
@@ -101,7 +101,7 @@ int nuc_configgpio(gpio_cfgset_t cfgset)
   DEBUGASSERT((unsigned)port <= NUC_GPIO_PORTE);
   base = NUC_GPIO_CTRL_BASE(port);
 
-  /* Set the the GPIO PMD register */
+  /* Set the GPIO PMD register */
 
   regaddr = base + NUC_GPIO_PMD_OFFSET;
   regval = getreg32(regaddr);
diff --git a/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c b/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c
index 7e8766a73..f8fe44145 100644
--- a/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c
+++ b/nuttx/arch/arm/src/nuc1xx/nuc_lowputc.c
@@ -86,7 +86,7 @@
 #endif
 
 /* Select either the external high speed crystal, the PLL output, or
- * the internal high speed clock as the the UART clock source.
+ * the internal high speed clock as the UART clock source.
  */
 
 #if defined(CONFIG_NUC_UARTCLK_XTALHI)
diff --git a/nuttx/arch/arm/src/sam34/sam3u_dmac.c b/nuttx/arch/arm/src/sam34/sam3u_dmac.c
index 32a693d4d..9a5d85aa6 100644
--- a/nuttx/arch/arm/src/sam34/sam3u_dmac.c
+++ b/nuttx/arch/arm/src/sam34/sam3u_dmac.c
@@ -298,7 +298,7 @@ static inline uint32_t sam_fifocfg(struct sam_dma_s *dmach)
  * Name: sam_txcfg
  *
  * Description:
- *  Decode the the flags to get the correct CFG register bit settings for
+ *  Decode the flags to get the correct CFG register bit settings for
  *  a transmit (memory to peripheral) transfer.
  *
  ****************************************************************************/
@@ -322,7 +322,7 @@ static inline uint32_t sam_txcfg(struct sam_dma_s *dmach)
  * Name: sam_rxcfg
  *
  * Description:
- *  Decode the the flags to get the correct CFG register bit settings for
+ *  Decode the flags to get the correct CFG register bit settings for
  *  a receive (peripheral to memory) transfer.
  *
  ****************************************************************************/
@@ -346,7 +346,7 @@ static inline uint32_t sam_rxcfg(struct sam_dma_s *dmach)
  * Name: sam_txctrlabits
  *
  * Description:
- *  Decode the the flags to get the correct CTRLA register bit settings for
+ *  Decode the flags to get the correct CTRLA register bit settings for
  *  a transmit (memory to peripheral) transfer.  These are only the "fixed"
  *  CTRLA values and  need to be updated with the actual transfer size before
  *  being written to CTRLA sam_txctrla).
@@ -492,7 +492,7 @@ static inline uint32_t sam_txctrla(struct sam_dma_s *dmach,
  * Name: sam_rxctrlabits
  *
  * Description:
- *  Decode the the flags to get the correct CTRLA register bit settings for
+ *  Decode the flags to get the correct CTRLA register bit settings for
  *  a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
  *  values and need to be updated with the actual transfer size before being
  *  written to CTRLA sam_rxctrla).
@@ -637,7 +637,7 @@ static inline uint32_t sam_rxctrla(struct sam_dma_s *dmach,
  * Name: sam_txctrlb
  *
  * Description:
- *  Decode the the flags to get the correct CTRLB register bit settings for
+ *  Decode the flags to get the correct CTRLB register bit settings for
  *  a transmit (memory to peripheral) transfer.
  *
  ****************************************************************************/
@@ -716,7 +716,7 @@ static inline uint32_t sam_txctrlb(struct sam_dma_s *dmach)
  * Name: sam_rxctrlb
  *
  * Description:
- *  Decode the the flags to get the correct CTRLB register bit settings for
+ *  Decode the flags to get the correct CTRLB register bit settings for
  *  a receive (peripheral to memory) transfer.
  *
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/sam34/sam_vectors.S b/nuttx/arch/arm/src/sam34/sam_vectors.S
index b38adf05f..fde817be4 100644
--- a/nuttx/arch/arm/src/sam34/sam_vectors.S
+++ b/nuttx/arch/arm/src/sam34/sam_vectors.S
@@ -244,7 +244,7 @@ sam_common:
 	sub		r1, #(4*SW_FPU_REGS)
 #endif
 
-	/* Save the the remaining registers on the stack after the registers pushed
+	/* Save the remaining registers on the stack after the registers pushed
 	 * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
 	 * r14=register values.
 	 */
diff --git a/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h b/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
index a24f9d834..db1f82939 100644
--- a/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
+++ b/nuttx/arch/arm/src/sama5/chip/sama5d3x_memorymap.h
@@ -527,7 +527,7 @@
    * in the file mmu.h
    *
    * We must declare the page table at the bottom or at the top of internal
-   * SRAM.  We pick the the bottom of internal SRAM *unless* there are vectors
+   * SRAM.  We pick the bottom of internal SRAM *unless* there are vectors
    * in the way at that position.
    */
 
diff --git a/nuttx/arch/arm/src/sama5/sam_boot.c b/nuttx/arch/arm/src/sama5/sam_boot.c
index f3b342707..49dd5e540 100644
--- a/nuttx/arch/arm/src/sama5/sam_boot.c
+++ b/nuttx/arch/arm/src/sama5/sam_boot.c
@@ -172,7 +172,7 @@ static const struct section_mapping_s section_mapping[] =
 /* SAMA5 External SDRAM Memory.  The SDRAM is not usable until it has been
  * initialized.  If we are running out of SDRAM now, we can assume that some
  * second level boot loader has properly configured SRAM for us.  In that
- * case, we set the the MMU flags for the final, fully cache-able state.
+ * case, we set the MMU flags for the final, fully cache-able state.
  *
  * If we are running from ISRAM or NOR flash, then we will need to configure
  * the SDRAM ourselves.  In this case, we set the MMU flags to the strongly
diff --git a/nuttx/arch/arm/src/sama5/sam_dmac.c b/nuttx/arch/arm/src/sama5/sam_dmac.c
index 84e1fb8d0..07ec99946 100644
--- a/nuttx/arch/arm/src/sama5/sam_dmac.c
+++ b/nuttx/arch/arm/src/sama5/sam_dmac.c
@@ -748,7 +748,7 @@ static uint32_t sam_sink_channel(struct sam_dmach_s *dmach, uint8_t pid,
  * Name: sam_txcfg
  *
  * Description:
- *  Decode the the flags to get the correct CFG register bit settings for
+ *  Decode the flags to get the correct CFG register bit settings for
  *  a transmit (memory to peripheral) transfer.
  *
  ****************************************************************************/
@@ -788,7 +788,7 @@ static inline uint32_t sam_txcfg(struct sam_dmach_s *dmach)
  * Name: sam_rxcfg
  *
  * Description:
- *  Decode the the flags to get the correct CFG register bit settings for
+ *  Decode the flags to get the correct CFG register bit settings for
  *  a receive (peripheral to memory) transfer.
  *
  ****************************************************************************/
@@ -828,7 +828,7 @@ static inline uint32_t sam_rxcfg(struct sam_dmach_s *dmach)
  * Name: sam_txctrlabits
  *
  * Description:
- *  Decode the the flags to get the correct CTRLA register bit settings for
+ *  Decode the flags to get the correct CTRLA register bit settings for
  *  a transmit (memory to peripheral) transfer.  These are only the "fixed"
  *  CTRLA values and  need to be updated with the actual transfer size before
  *  being written to CTRLA sam_txctrla).
@@ -932,7 +932,7 @@ static uint32_t sam_ntxtransfers(struct sam_dmach_s *dmach, uint32_t dmasize)
 {
   unsigned int srcwidth;
 
-  /* Adjust the the source transfer size for the source chunk size (memory
+  /* Adjust the source transfer size for the source chunk size (memory
    * chunk size).  BTSIZE is "the number of transfers to be performed, that
    * is, for writes it refers to the number of source width transfers
    * to perform when DMAC is flow controller. For Reads, BTSIZE refers to
@@ -992,7 +992,7 @@ static inline uint32_t sam_txctrla(struct sam_dmach_s *dmach,
  * Name: sam_rxctrlabits
  *
  * Description:
- *  Decode the the flags to get the correct CTRLA register bit settings for
+ *  Decode the flags to get the correct CTRLA register bit settings for
  *  a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
  *  values and need to be updated with the actual transfer size before being
  *  written to CTRLA sam_rxctrla).
@@ -1100,7 +1100,7 @@ static uint32_t sam_nrxtransfers(struct sam_dmach_s *dmach, uint32_t dmasize)
 {
   unsigned int srcwidth;
 
-  /* Adjust the the source transfer size for the source chunk size (peripheral
+  /* Adjust the source transfer size for the source chunk size (peripheral
    * chunk size).  BTSIZE is "the number of transfers to be performed, that
    * is, for writes it refers to the number of source width transfers
    * to perform when DMAC is flow controller. For Reads, BTSIZE refers to
@@ -1160,7 +1160,7 @@ static inline uint32_t sam_rxctrla(struct sam_dmach_s *dmach,
  * Name: sam_txctrlb
  *
  * Description:
- *  Decode the the flags to get the correct CTRLB register bit settings for
+ *  Decode the flags to get the correct CTRLB register bit settings for
  *  a transmit (memory to peripheral) transfer.
  *
  ****************************************************************************/
@@ -1251,7 +1251,7 @@ static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
  * Name: sam_rxctrlb
  *
  * Description:
- *  Decode the the flags to get the correct CTRLB register bit settings for
+ *  Decode the flags to get the correct CTRLB register bit settings for
  *  a receive (peripheral to memory) transfer.
  *
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/sama5/sam_ehci.c b/nuttx/arch/arm/src/sama5/sam_ehci.c
index 3ad06d0e4..cbc0bb1bd 100755
--- a/nuttx/arch/arm/src/sama5/sam_ehci.c
+++ b/nuttx/arch/arm/src/sama5/sam_ehci.c
@@ -1389,7 +1389,7 @@ static void sam_qh_enqueue(struct sam_qh_s *qh)
 {
   uintptr_t physaddr;
 
-  /* Set the internal fqp field.  When we transverse the the QH list later,
+  /* Set the internal fqp field.  When we transverse the QH list later,
    * we need to know the correct place to start because the overlay may no
    * longer point to the first qTD entry.
    */
@@ -1554,7 +1554,7 @@ static int sam_qtd_addbpl(struct sam_qtd_s *qtd, const void *buffer, size_t bufl
 
       next = (physaddr + 4096) & ~4095;
 
-      /* How many bytes were included in the last buffer?  Was the the whole
+      /* How many bytes were included in the last buffer?  Was it the whole
        * thing?
        */
 
@@ -2059,7 +2059,7 @@ static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
   **bp = qtd->hw.nqp;
 
   /* Subtract the number of bytes left untransferred.  The epinfo->xfrd
-   * field is initialized to the the total number of bytes to be transferred
+   * field is initialized to the total number of bytes to be transferred
    * (all qTDs in the list).  We subtract out the number of untransferred
    * bytes on each transfer and the final result will be the number of bytes
    * actually transferred.
@@ -3825,7 +3825,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
   regval16 = sam_swap16(HCCR->hciversion);
   uvdbg("HCIVERSION %x.%02x\n", regval16 >> 8, regval16 & 0xff);
 
-  /* Verify the the correct number of ports is reported */
+  /* Verify that the correct number of ports is reported */
 
   regval = sam_getreg(&HCCR->hcsparams);
   nports = (regval & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;
diff --git a/nuttx/arch/arm/src/stm32/stm32_can.c b/nuttx/arch/arm/src/stm32/stm32_can.c
index a3011cde4..9333baec3 100644
--- a/nuttx/arch/arm/src/stm32/stm32_can.c
+++ b/nuttx/arch/arm/src/stm32/stm32_can.c
@@ -1332,7 +1332,7 @@ static int can_bittiming(struct stm32_can_s *priv)
 
   canllvdbg("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
 
- /* Configure bit timing.  This also does the the following, less obvious
+ /* Configure bit timing.  This also does the following, less obvious
    * things.  Unless loopback mode is enabled, it:
    *
    * - Disables silent mode.
diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c
index 09efaf193..c61ea1f7c 100644
--- a/nuttx/arch/arm/src/stm32/stm32_eth.c
+++ b/nuttx/arch/arm/src/stm32/stm32_eth.c
@@ -1219,7 +1219,7 @@ static int stm32_uiptxpoll(struct uip_driver_s *dev)
  *
  * Description:
  *   The function is called when a frame is received using the DMA receive
- *   interrupt.  It scans the RX descriptors to the the received frame.
+ *   interrupt.  It scans the RX descriptors to the received frame.
  *
  * Parameters:
  *   priv  - Reference to the driver state structure
@@ -1347,7 +1347,7 @@ static void stm32_disableint(FAR struct stm32_ethmac_s *priv, uint32_t ierbit)
  *
  * Description:
  *   The function is called when a frame is received using the DMA receive
- *   interrupt.  It scans the RX descriptors to the the received frame.
+ *   interrupt.  It scans the RX descriptors to the received frame.
  *
  * Parameters:
  *   priv  - Reference to the driver state structure
@@ -1506,7 +1506,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
               dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >> ETH_RDES0_FL_SHIFT) - 4;
 
               /* Get a buffer from the free list.  We don't even check if
-               * this is successful because we already assure the the free
+               * this is successful because we already assure the free
                * list is not empty above.
                */
 
@@ -2536,7 +2536,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
       return ret;
     }
 
-  /* Bit 8 of the DSCR register is zero, the the DM9161 has not selected RMII.
+  /* Bit 8 of the DSCR register is zero, then the DM9161 has not selected RMII.
    * If RMII is not selected, then reset the MCU to recover.
    */
  
diff --git a/nuttx/arch/arm/src/stm32/stm32_iwdg.c b/nuttx/arch/arm/src/stm32/stm32_iwdg.c
index fd51ba0fe..6b4bc5b65 100644
--- a/nuttx/arch/arm/src/stm32/stm32_iwdg.c
+++ b/nuttx/arch/arm/src/stm32/stm32_iwdg.c
@@ -673,7 +673,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
 
   /* Make sure that the LSI ocsillator is enabled.  NOTE:  The LSI oscillator
    * is enabled here but is not disabled by this file (because this file does
-   * not know the the global usage of the oscillator.  Any clock management
+   * not know the global usage of the oscillator.  Any clock management
    * logic (say, as part of a power management scheme) needs handle other
    * LSI controls outside of this file.
    */
diff --git a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c
index 84903b3f8..c3a795faf 100644
--- a/nuttx/arch/arm/src/stm32/stm32_otgfshost.c
+++ b/nuttx/arch/arm/src/stm32/stm32_otgfshost.c
@@ -996,7 +996,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
 static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
                               FAR struct stm32_chan_s *chan)
 {
-  /* Is the the transfer complete? Is there a thread waiting for this transfer
+  /* Is the transfer complete? Is there a thread waiting for this transfer
    * to complete?
    */
 
@@ -1774,7 +1774,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
           stm32_chan_halt(priv, chidx, CHREASON_XFRC);
 
           /* Clear any pending NAK condition.  The 'indata1' data toggle
-           * should have been appropriately updated by the the RxFIFO
+           * should have been appropriately updated by the RxFIFO
            * logic as each packet was received.
            */
 
@@ -2961,7 +2961,7 @@ static inline void stm32_hostinit_enable(void)
  *   Enable Tx FIFO empty interrupts.  This is necessary when the entire
  *   transfer will not fit into Tx FIFO.  The transfer will then be completed
  *   when the Tx FIFO is empty.  NOTE:  The Tx FIFO interrupt is disabled
- *   the the fifo empty interrupt handler when the transfer is complete.
+ *   the fifo empty interrupt handler when the transfer is complete.
  *
  * Input Parameters:
  *   priv - Driver state structure reference
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h
index 4f96f21da..76c47680e 100644
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.h
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h
@@ -76,7 +76,7 @@ extern "C"
  * Public Data
  ************************************************************************************/
 
-/* This symbol references the Cortex-M3 vector table (as positioned by the the linker
+/* This symbol references the Cortex-M3 vector table (as positioned by the linker
  * script, ld.script or ld.script.dfu.  The standard location for the vector table is
  * at the beginning of FLASH at address 0x0800:0000.  If we are using the STMicro DFU
  * bootloader, then the vector table will be offset to a different location in FLASH
diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.c b/nuttx/arch/arm/src/stm32/stm32_sdio.c
index 8b8d4d1de..6e94b16a1 100644
--- a/nuttx/arch/arm/src/stm32/stm32_sdio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_sdio.c
@@ -203,7 +203,7 @@
 #  error "Unknown STM32 DMA"
 #endif
 
-/* SDIO DMA Channel/Stream selection.  For the the case of the STM32 F4, there
+/* SDIO DMA Channel/Stream selection.  For the case of the STM32 F4, there
  * are multiple DMA stream options that must be dis-ambiguated in the board.h
  * file.
  */
@@ -682,7 +682,7 @@ static void stm32_setpwrctrl(uint32_t pwrctrl)
  *
  * Description:
  *   Return the current value of the  the PWRCTRL field of the SDIO POWER
- *   register.  This function can be used to see the the SDIO is power ON
+ *   register.  This function can be used to see if the SDIO is powered ON
  *   or OFF
  *
  * Input Parameters:
@@ -952,7 +952,7 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
  * Name: stm32_datadisable
  *
  * Description:
- *   Disable the the SDIO data path setup by stm32_dataconfig() and
+ *   Disable the SDIO data path setup by stm32_dataconfig() and
  *   disable DMA.
  *
  ****************************************************************************/
diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S
index 37c53e8d5..a49729de3 100644
--- a/nuttx/arch/arm/src/stm32/stm32_vectors.S
+++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S
@@ -251,7 +251,7 @@ stm32_common:
 	sub		r1, #(4*SW_FPU_REGS)
 #endif
 
-	/* Save the the remaining registers on the stack after the registers pushed
+	/* Save the remaining registers on the stack after the registers pushed
 	 * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
 	 * r14=register values.
 	 */
diff --git a/nuttx/arch/arm/src/stm32/stm32_wwdg.c b/nuttx/arch/arm/src/stm32/stm32_wwdg.c
index 4506fa4e0..ed3721cfe 100644
--- a/nuttx/arch/arm/src/stm32/stm32_wwdg.c
+++ b/nuttx/arch/arm/src/stm32/stm32_wwdg.c
@@ -623,7 +623,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
  *   lower      - A pointer the publicly visible representation of the "lower-half"
  *                driver state structure.
  *   newhandler - The new watchdog expiration function pointer.  If this
- *                function pointer is NULL, then the the reset-on-expiration
+ *                function pointer is NULL, then the reset-on-expiration
  *                behavior is restored,
  *
  * Returned Values:
diff --git a/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c
index 71ac263fb..0186bec15 100644
--- a/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c
+++ b/nuttx/arch/arm/src/stm32/stm32f20xxx_dma.c
@@ -521,7 +521,7 @@ void weak_function up_dmainitialize(void)
  *
  * Input parameter:
  *   dmamap - Identifies the stream/channel resource. For the STM32 F2, this
- *     is a bit-encoded  value as provided by the the DMAMAP_* definitions
+ *     is a bit-encoded value as provided by the DMAMAP_* definitions
  *     in chip/stm32f20xxx_dma.h
  *
  * Returned Value:
diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
index 5bff603b9..235e40441 100644
--- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
+++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c
@@ -520,7 +520,7 @@ void weak_function up_dmainitialize(void)
  *
  * Input parameter:
  *   dmamap - Identifies the stream/channel resource. For the STM32 F4, this
- *     is a bit-encoded  value as provided by the the DMAMAP_* definitions
+ *     is a bit-encoded  value as provided by the DMAMAP_* definitions
  *     in chip/stm32f40xxx_dma.h
  *
  * Returned Value: