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authorGregory Nutt <gnutt@nuttx.org>2014-04-26 13:58:38 -0600
committerGregory Nutt <gnutt@nuttx.org>2014-04-26 13:58:38 -0600
commita003b3b5a00f417a1f6df8811c404a82626e94b4 (patch)
tree464fd7c176f01c4d3586c1a6410544b94af92f23 /nuttx/arch/z16
parentef04398d2597c3c726de8d197b1a357061d4a3df (diff)
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Zneo: ESPI needs to configure GPIO for ESPI
Diffstat (limited to 'nuttx/arch/z16')
-rw-r--r--nuttx/arch/z16/src/z16f/z16f_espi.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/nuttx/arch/z16/src/z16f/z16f_espi.c b/nuttx/arch/z16/src/z16f/z16f_espi.c
index e0366f3b3..acbb38e25 100644
--- a/nuttx/arch/z16/src/z16f/z16f_espi.c
+++ b/nuttx/arch/z16/src/z16f/z16f_espi.c
@@ -838,9 +838,9 @@ struct spi_dev_s *up_spiinitialize(int port)
FAR struct z16f_spi_s *priv;
irqstate_t flags;
#ifndef CONFIG_SPI_OWNBUS
- uint8_t regval;
unsigned int offset;
#endif
+ uint8_t regval;
spivdbg("port: %d\n", port);
DEBUGASSERT(port == 0);
@@ -858,6 +858,22 @@ struct spi_dev_s *up_spiinitialize(int port)
sem_init(&priv->exclsem, 0, 1);
#endif
+ /* Set up the SPI pin configuration (board-specific logic is required to
+ * configure and manage all chip selects).
+ *
+ * SCK - PC3, Alternate function 1
+ * MOSI - PC4, Alternate function 1
+ * MISO - PC5, Alternate function 1
+ */
+
+ regval = getreg8(Z16F_GPIOC_AFL);
+ regval |= 0x38;
+ putreg8(regval, Z16F_GPIOC_AFL);
+
+ regval = getreg8(Z16F_GPIOC_AFH);
+ regval &= ~0x38;
+ putreg8(regval, Z16F_GPIOC_AFH);
+
/* Initialize the hardware. Mode 0, 8-bits, 400KHz */
spi_putreg8(priv, 0x00, Z16F_ESPI_CTL); /* Disabled the ESPI */