Remove packaging indications for TM4C129 configuration variables

3 files changed, 76 insertions, 76 deletions

diff --git a/nuttx/arch/arm/include/tiva/chip.h b/nuttx/arch/arm/include/tiva/chip.h
index 73d23f2ef..3d3d75989 100644
--- a/nuttx/arch/arm/include/tiva/chip.h
+++ b/nuttx/arch/arm/include/tiva/chip.h
@@ -208,7 +208,7 @@
 #  define TIVA_NCANCONTROLLER  2  /* Two CAN controllers */
 #  define TIVA_NUSBOTGFS       1  /* One USB 2.0 OTG FS */
 #  define TIVA_NUSBOTGHS       0  /* No USB 2.0 OTG HS */
-#elif defined(CONFIG_ARCH_CHIP_TM4C129XNCZAD) || defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC) || defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  undef  LM3S                    /* Not LM3S family */
 #  undef  LM4F                    /* Not LM4F family */
 #  define TM4C                 1  /* TM4C family */
diff --git a/nuttx/arch/arm/src/tiva/Kconfig b/nuttx/arch/arm/src/tiva/Kconfig
index 5544437e9..a2c5e1476 100644
--- a/nuttx/arch/arm/src/tiva/Kconfig
+++ b/nuttx/arch/arm/src/tiva/Kconfig
@@ -67,15 +67,15 @@ config ARCH_CHIP_TM4C123GH6PMI
 	select ARCH_CHIP_TM4C
 	select ARCH_HAVE_FPU
 
-config ARCH_CHIP_TM4C129XNCZAD
-	bool "TM4C129XNCZAD"
+config ARCH_CHIP_TM4C1294NC
+	bool "TM4C1294NC"
 	depends on ARCH_CHIP_TIVA
 	select ARCH_CORTEXM4
 	select ARCH_CHIP_TM4C
 	select ARCH_HAVE_FPU
 
-config ARCH_CHIP_TM4C1294NCPDT
-	bool "TM4C1294NCPDT"
+config ARCH_CHIP_TM4C129XNC
+	bool "TM4C129XNC"
 	depends on ARCH_CHIP_TIVA
 	select ARCH_CORTEXM4
 	select ARCH_CHIP_TM4C
diff --git a/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h b/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h
index 5a4f2130c..dccd8f955 100644
--- a/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h
+++ b/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h
@@ -61,12 +61,12 @@
 #define TIVA_I2CM_CR_OFFSET            0x0020 /* I2C Master Configuration */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM_CLKOCNT_OFFSET     0x0024 /* I2C Master Clock Low Timeout Count */
 #  define TIVA_I2CM_BMON_OFFSET        0x002c /* I2C Master Configuration */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM_BLEN_OFFSET        0x0030 /* I2C Master Burst Length */
 #  define TIVA_I2CM_BCNT_OFFSET        0x0034 /* I2C Master Burst Count */
 #endif
@@ -86,21 +86,21 @@
 #define TIVA_I2CS_ICR_OFFSET           0x0818 /* I2C Slave Interrupt Clear */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS_SOAR2_OFFSET       0x081c /* I2C Slave Own Address 2 */
 #  define TIVA_I2CS_ACKCTL_OFFSET      0x0820 /* I2C Slave ACK Control */
 #endif
 
 /* I2C Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC_FIFODATA_OFFSET   0x0f00 /* I2C FIFO Data */
 #  define TIVA_I2CSC_FIFOCTL_OFFSET    0x0f04 /* I2C FIFO Control */
 #  define TIVA_I2CSC_FIFOSTATUS_OFFSET 0x0f08 /* I2C FIFO Status */
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC_PP_OFFSET         0x0fc0 /* I2C Peripheral Properties */
 #  define TIVA_I2CSC_PC_OFFSET         0x0fc4 /* I2C Peripheral Configuration */
 #endif
@@ -122,12 +122,12 @@
 #define TIVA_I2CM0_CR                  (TIVA_I2C0_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM0_CLKOCNT           (TIVA_I2C0_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
 #  define TIVA_I2CM0_BMON              (TIVA_I2C0_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM0_BLEN              (TIVA_I2C0_BASE + TIVA_I2CM_BLEN_OFFSET)
 #  define TIVA_I2CM0_BCNT              (TIVA_I2C0_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
@@ -147,21 +147,21 @@
 #define TIVA_I2CS0_ICR                 (TIVA_I2C0_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS0_SOAR2             (TIVA_I2C0_BASE + TIVA_I2CS_SOAR2_OFFSET)
 #  define TIVA_I2CS0_ACKCTL            (TIVA_I2C0_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C0 Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC0_FIFODATA         (TIVA_I2C0_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
 #  define TIVA_I2CSC0_FIFOCTL          (TIVA_I2C0_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
 #  define TIVA_I2CSC0_FIFOSTATUS       (TIVA_I2C0_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC0_PP               (TIVA_I2C0_BASE + TIVA_I2CSC_PP_OFFSET)
 #  define TIVA_I2CSC0_PC               (TIVA_I2C0_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
@@ -182,12 +182,12 @@
 #define TIVA_I2CM1_CR                  (TIVA_I2C1_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM1_CLKOCNT           (TIVA_I2C1_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
 #  define TIVA_I2CM1_BMON              (TIVA_I2C1_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM1_BLEN              (TIVA_I2C1_BASE + TIVA_I2CM_BLEN_OFFSET)
 #  define TIVA_I2CM1_BCNT              (TIVA_I2C1_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
@@ -207,21 +207,21 @@
 #define TIVA_I2CS1_ICR                 (TIVA_I2C1_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS1_SOAR2             (TIVA_I2C1_BASE + TIVA_I2CS_SOAR2_OFFSET)
 #  define TIVA_I2CS1_ACKCTL            (TIVA_I2C1_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C1 Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC1_FIFODATA         (TIVA_I2C1_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
 #  define TIVA_I2CSC1_FIFOCTL          (TIVA_I2C1_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
 #  define TIVA_I2CSC1_FIFOSTATUS       (TIVA_I2C1_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC1_PP               (TIVA_I2C1_BASE + TIVA_I2CSC_PP_OFFSET)
 #  define TIVA_I2CSC1_PC               (TIVA_I2C1_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
@@ -242,12 +242,12 @@
 #define TIVA_I2CM2_CR                  (TIVA_I2C2_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM2_CLKOCNT           (TIVA_I2C2_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
 #  define TIVA_I2CM2_BMON              (TIVA_I2C2_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM2_BLEN              (TIVA_I2C2_BASE + TIVA_I2CM_BLEN_OFFSET)
 #  define TIVA_I2CM2_BCNT              (TIVA_I2C2_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
@@ -267,21 +267,21 @@
 #define TIVA_I2CS2_ICR                 (TIVA_I2C2_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS2_SOAR2             (TIVA_I2C2_BASE + TIVA_I2CS_SOAR2_OFFSET)
 #  define TIVA_I2CS2_ACKCTL            (TIVA_I2C2_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C2 Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC2_FIFODATA         (TIVA_I2C2_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
 #  define TIVA_I2CSC2_FIFOCTL          (TIVA_I2C2_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
 #  define TIVA_I2CSC2_FIFOSTATUS       (TIVA_I2C2_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC2_PP               (TIVA_I2C2_BASE + TIVA_I2CSC_PP_OFFSET)
 #  define TIVA_I2CSC2_PC               (TIVA_I2C2_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
@@ -302,12 +302,12 @@
 #define TIVA_I2CM3_CR                  (TIVA_I2C3_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM3_CLKOCNT           (TIVA_I2C3_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
 #  define TIVA_I2CM3_BMON              (TIVA_I2C3_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM3_BLEN              (TIVA_I2C3_BASE + TIVA_I2CM_BLEN_OFFSET)
 #  define TIVA_I2CM3_BCNT              (TIVA_I2C3_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
@@ -327,21 +327,21 @@
 #define TIVA_I2CS3_ICR                 (TIVA_I2C3_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS3_SOAR2             (TIVA_I2C3_BASE + TIVA_I2CS_SOAR2_OFFSET)
 #  define TIVA_I2CS3_ACKCTL            (TIVA_I2C3_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C3 Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC3_FIFODATA         (TIVA_I2C3_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
 #  define TIVA_I2CSC3_FIFOCTL          (TIVA_I2C3_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
 #  define TIVA_I2CSC3_FIFOSTATUS       (TIVA_I2C3_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC3_PP               (TIVA_I2C3_BASE + TIVA_I2CSC_PP_OFFSET)
 #  define TIVA_I2CSC3_PC               (TIVA_I2C3_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
@@ -362,12 +362,12 @@
 #define TIVA_I2CM4_CR                  (TIVA_I2C4_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM4_CLKOCNT           (TIVA_I2C4_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
 #  define TIVA_I2CM4_BMON              (TIVA_I2C4_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM4_BLEN              (TIVA_I2C4_BASE + TIVA_I2CM_BLEN_OFFSET)
 #  define TIVA_I2CM4_BCNT              (TIVA_I2C4_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
@@ -387,21 +387,21 @@
 #define TIVA_I2CS4_ICR                 (TIVA_I2C4_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS4_SOAR2             (TIVA_I2C4_BASE + TIVA_I2CS_SOAR2_OFFSET)
 #  define TIVA_I2CS4_ACKCTL            (TIVA_I2C4_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C4 Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC4_FIFODATA         (TIVA_I2C4_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
 #  define TIVA_I2CSC4_FIFOCTL          (TIVA_I2C4_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
 #  define TIVA_I2CSC4_FIFOSTATUS       (TIVA_I2C4_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC4_PP               (TIVA_I2C4_BASE + TIVA_I2CSC_PP_OFFSET)
 #  define TIVA_I2CSC4_PC               (TIVA_I2C4_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
@@ -422,12 +422,12 @@
 #define TIVA_I2CM5_CR                  (TIVA_I2C5_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM5_CLKOCNT           (TIVA_I2C5_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
 #  define TIVA_I2CM5_BMON              (TIVA_I2C5_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CM5_BLEN              (TIVA_I2C5_BASE + TIVA_I2CM_BLEN_OFFSET)
 #  define TIVA_I2CM5_BCNT              (TIVA_I2C5_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
@@ -447,21 +447,21 @@
 #define TIVA_I2CS5_ICR                 (TIVA_I2C5_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CS5_SOAR2             (TIVA_I2C5_BASE + TIVA_I2CS_SOAR2_OFFSET)
 #  define TIVA_I2CS5_ACKCTL            (TIVA_I2C5_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C Status and control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC5_FIFODATA         (TIVA_I2C5_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
 #  define TIVA_I2CSC5_FIFOCTL          (TIVA_I2C5_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
 #  define TIVA_I2CSC5_FIFOSTATUS       (TIVA_I2C5_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define TIVA_I2CSC5_PP               (TIVA_I2C5_BASE + TIVA_I2CSC_PP_OFFSET)
 #  define TIVA_I2CSC5_PC               (TIVA_I2C5_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
@@ -486,11 +486,11 @@
 #define I2CM_CS_BUSBSY                 (1 << 6)  /* Bit 6:  Bus Busy (read) */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_CS_CLKTO                (1 << 7)  /* Bit 7:  Clock Timeout Error (read) */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_CS_ACTDMATX             (1 << 30) /* Bit 30: DMA TX Active Status (read) */
 #  define I2CM_CS_ACTDMARX             (1 << 31) /* Bit 31: DMA RX Active Status (read) */
 #endif
@@ -501,11 +501,11 @@
 #define I2CM_CS_ACK                    (1 << 3)  /* Bit 3:  Data Acknowledge Enable (write) */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_CS_HS                   (1 << 4)  /* Bit 4:  High-Speed Enable (write) */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_CS_QCMD                 (1 << 5)  /* Bit 5:  Quick Command (write) */
 #  define I2CM_CS_BURST                (1 << 6)  /* Bit 6:  Burst Enable (write) */
 #endif
@@ -518,12 +518,12 @@
 /* I2C Master Timer Period (I2CM_TPR) */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_TPR_SHIFT               (0)      /* Bits 6-0: SCL Clock Period */
 #  define I2CM_TPR_MASK                (0x7f << I2CM_TPR_SHIFT)
 #  define I2CM_TPR_HS                  (1 << 7) /* Bit 7:  High-Speed Enable (write) */
 
-#  if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#  if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #    define I2CM_TPR_PULSEL_SHIFT      (16)  /* Bits 18-16: Glitch Suppression Pulse Width (write) */
 #    define I2CM_TPR_PULSEL_MASK       (7 << I2CM_TPR_PULSEL_SHIFT)
 #      define I2CM_TPR_PULSEL_BYPASS   (0 << I2CM_TPR_PULSEL_SHIFT) /* Bypass */
@@ -546,11 +546,11 @@
 #define I2CM_IMR_MIM                  (1 << 0)  /* Bit 0:  Master Interrupt Mask */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_IMR_CLKIM              (1 << 1)  /* Bit 1:  Clock Timeout Interrupt Mask */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_IMR_DMARXIM            (1 << 2)  /* Bit 2:  Receive DMA Interrupt Mask */
 #  define I2CM_IMR_DMATXIM            (1 << 3)  /* Bit 3:  Transmit DMA Interrupt Mask */
 #  define I2CM_IMR_NACKIM             (1 << 4)  /* Bit 4:  Address/Data NACK Interrupt Mask */
@@ -568,11 +568,11 @@
 #define I2CM_RIS_MRIS                 (1 << 0)  /* Bit 0:  Master Raw Interrupt Status */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_RIS_CLKRIS             (1 << 1)  /* Bit 1:  Clock Timeout Raw Interrupt Status */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_RIS_DMARXRIS           (1 << 2)  /* Bit 2:  Receive DMA Interrupt Status */
 #  define I2CM_RIS_DMATXRIS           (1 << 3)  /* Bit 3:  Transmit DMA Interrupt Status */
 #  define I2CM_RIS_NACKRIS            (1 << 4)  /* Bit 4:  Address/Data NACK Interrupt Status */
@@ -590,11 +590,11 @@
 #define I2CM_MIS_MMIS                 (1 << 0)  /* Bit 0:  Maseter Masked Interrupt Status */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_MIS_CLKMIS             (1 << 1)  /* Bit 1:  Clock Timeout Masked Interrupt Status */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_MIS_DMARXMIS           (1 << 2)  /* Bit 2:  Receive DMA Interrupt Status */
 #  define I2CM_MIS_DMATXMIS           (1 << 3)  /* Bit 3:  Transmit DMA Interrupt Status */
 #  define I2CM_MIS_NACKMIS            (1 << 4)  /* Bit 4:  Address/Data NACK Interrupt Status */
@@ -612,11 +612,11 @@
 #define I2CM_ICR_MIC                  (1 << 0)  /* Bit 0:  Master Masked Interrupt Clear */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_ICR_CLKC               (1 << 1)  /* Bit 1:  Clock Timeout Interrupt Clear */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_ICR_DMARXIC            (1 << 2)  /* Bit 2:  Receive DMA Interrupt Clear */
 #  define I2CM_ICR_DMATXIC            (1 << 3)  /* Bit 3:  Transmit DMA Interrupt Clear */
 #  define I2CM_ICR_NACKIC             (1 << 4)  /* Bit 4:  Address/Data NACK Interrupt Clear */
@@ -642,7 +642,7 @@
 /* I2C Master Clock Low Timeout Count */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_CLKOCNT_CNTL_SHIFT      (0)       /* Bits 7-0: I2C Master Count */
 #  define I2CM_CLKOCNT_CNTL_MASK       (0xff << I2CM_CLKOCNT_CNTL_SHIFT)
 #endif
@@ -650,21 +650,21 @@
 /* I2C Master Configuration */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_BMON_SCL                (1 << 0)  /* Bit 0:  II2C SCL Status */
 #  define I2CM_BMON_SCA                (1 << 1)  /* Bit 1:  II2C SDA Status */
 #endif
 
 /* I2C Master Burst Length */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_BLEN_SHIFT              (0)       /* Bits 7-0: I2C Burst Length */
 #  define I2CM_BLEN_MASK               (0xff << I2CM_BLEN_SHIFT)
 #endif
 
 /* I2C Master Burst Count */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_BCNT_SHIFT              (0)       /* Bits 7-0: I2C Burst Count */
 #  define I2CM_BCNT_MASK               (0xff << I2CM_BCNT_SHIFT)
 #endif
@@ -695,11 +695,11 @@
 #define I2CS_CSR_FBR                   (1 << 2)  /* Bit 2:  First Byte Received (read) */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CS_CSR_OAR2SEL             (1 << 3)  /* Bit 3:  OAR2 Address Matched (read) */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CS_CSR_QCMDST             (1 << 4)  /* Bit 4:  Quick Command Status (read) */
 #  define I2CS_CSR_QCMDRW             (1 << 5)  /* Bit 5:  Quick Command Read / Write (read) */
 #  define I2CS_CSR_ACTDMATX           (1 << 30) /* Bit 30: DMA TX Active Status (read) */
@@ -708,7 +708,7 @@
 
 #define I2CS_CSR_DA                    (1 << 0)  /* Bit 0:  Device Active (write) */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CS_CSR_TXFIFO              (1 << 1)  /* Bit 1:  TX FIFO Enable (write) */
 #  define I2CS_CSR_RXFIFO              (1 << 2)  /* Bit 2:  RX FIFO Enable (write) */
 #endif
@@ -723,12 +723,12 @@
 #define I2CM_IMR_DATAIM                (1 << 0)  /* Bit 0:  Data Interrupt Mask */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_IMR_STARTIM             (1 << 1)  /* Bit 1:  Start Condition Interrupt Mask */
 #  define I2CM_IMR_STOPIM              (1 << 2)  /* Bit 2:  Stop Condition Interrupt Mask */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_IMR_DMARXIM             (1 << 3)  /* Bit 3:  Receive DMA Interrupt Mask */
 #  define I2CM_IMR_DMATXIM             (1 << 4)  /* Bit 4:  Transmit DMA Interrupt Mask */
 #  define I2CM_IMR_TXIM                (1 << 5)  /* Bit 5:  Transmit FIFO Request Interrupt Mask */
@@ -742,12 +742,12 @@
 #define I2CM_RIS_DATARIS               (1 << 0)  /* Bit 0:  Data Raw Interrupt Status */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_RIS_STARTRIS            (1 << 1)  /* Bit 1:  Start Condition Raw Interrupt Status */
 #  define I2CM_RIS_STOPRIS             (1 << 2)  /* Bit 2:  Stop Condition Raw Interrupt Status */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_RIS_DMARXRIS            (1 << 3)  /* Bit 3:  Receive DMA Interrupt Mask */
 #  define I2CM_RIS_DMATXRIS            (1 << 4)  /* Bit 4:  Transmit DMA Interrupt Mask */
 #  define I2CM_RIS_TXRIS               (1 << 5)  /* Bit 5:  Transmit FIFO Request Interrupt Mask */
@@ -761,12 +761,12 @@
 #define I2CM_MIS_DATAMIS               (1 << 0)  /* Bit 0:  Data Masked Interrupt Status */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_MIS_STARTMIS            (1 << 1)  /* Bit 1:  Start Condition Masked Interrupt Status */
 #  define I2CM_MIS_STOPMIS             (1 << 2)  /* Bit 2:  Stop Condition Masked Interrupt Status */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_MIS_DMARXMIS            (1 << 3)  /* Bit 3:  Receive DMA Interrupt Mask */
 #  define I2CM_MIS_DMATXMIS            (1 << 4)  /* Bit 4:  Transmit DMA Interrupt Mask */
 #  define I2CM_MIS_TXMIS               (1 << 5)  /* Bit 5:  Transmit FIFO Request Interrupt Mask */
@@ -780,12 +780,12 @@
 #define I2CM_ICR_DATAIC                (1 << 0)  /* Bit 0:  Data Interrupt Clear */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_ICR_STARTIC             (1 << 1)  /* Bit 1:  Start Condition Interrupt Clear */
 #  define I2CM_ICR_STOPIC              (1 << 2)  /* Bit 2:  Stop Condition Interrupt Clear */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CM_ICR_DMARXIC             (1 << 3)  /* Bit 3:  Receive DMA Interrupt Mask */
 #  define I2CM_ICR_DMATXIC             (1 << 4)  /* Bit 4:  Transmit DMA Interrupt Mask */
 #  define I2CM_ICR_TXIC                (1 << 5)  /* Bit 5:  Transmit FIFO Request Interrupt Mask */
@@ -797,7 +797,7 @@
 /* I2C Slave Own Address 2 */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CS_SOAR2_SHIFT             (0)       /* Bits 0-6: I2C Slave Own Address 2 */
 #  define I2CS_SOAR2_MASK              (0x7f << I2CS_SOAR2_SHIFT)
 #  define I2CS_SOAR2_OAR2EN            (1 << 7)  /* Bit 7:  I2C Slave Own Address 2 Enable */
@@ -806,21 +806,21 @@
 /* I2C Slave ACK Control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CS_ACKCTL_ACKOEN           (1 << 0)  /* Bit 0:  I2C Slave ACK Override Enable */
 #  define I2CS_ACKCTL_ACKOVAL          (1 << 1)  /* Bit 1:  I2C Slave ACK Override Value */
 #endif
 
 /* I2C FIFO Data */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CSC_FIFODATA_SHIFT         (0)       /* Bits 7-0: I2C RX FIFO Read / Write Data Byte */
 #  define I2CSC_FIFODATA_MASK          (0xff << I2CSC_FIFODATA_SHIFT)
 #endif
 
 /* I2C FIFO Control */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CSC_FIFOCTRL_TXTRIG_SHIFT  (0)       /* Bits 2-0: TX FIFO Trigger */
 #  define I2CSC_FIFOCTRL_TXTRIG_MASK   (7 << I2CSC_FIFOCTRL_TXTRIG_SHIFT)
 #    define I2CSC_FIFOCTRL_TXTRIG(n)   ((uint32_)(n) << I2CSC_FIFOCTRL_TXTRIG_SHIFT)
@@ -837,7 +837,7 @@
 
 /* I2C FIFO Status */
 
-#if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CSC_FIFOSTATUS_TXFE        (1 << 0)  /* Bit 0:  TX FIFO Empty */
 #  define I2CSC_FIFOSTATUS_TXFF        (1 << 1)  /* Bit 1:  TX FIFO Full */
 #  define I2CSC_FIFOSTATUS_TXBLWTRIG   (1 << 2)  /* Bit 2:  TX FIFO Below Trigger Level */
@@ -849,14 +849,14 @@
 /* I2C Peripheral Properties */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CSC_PP_HS                  (1 << 0)  /* Bit 0:  High-Speed Capable */ 
 #endif
 
 /* I2C Peripheral Configuration */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
-    defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
+    defined(CONFIG_ARCH_CHIP_TM4C1294NC)
 #  define I2CSC_PC_HS                  (1 << 0)  /* Bit 0:  High-Speed Capable */ 
 #endif