diff options
author | Gregory Nutt <gnutt@nuttx.org> | 2014-10-08 10:18:58 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2014-10-08 10:18:58 -0600 |
commit | 9a5382c33e63c2d36462f368657e87168fe5c3d8 (patch) | |
tree | 7480f45364d79730cad0eb4e74188a109da378ce /nuttx/drivers/audio | |
parent | fcb644c3ce3d4fc6eab79ccde3ed50f5ac4d1a7f (diff) | |
download | nuttx-9a5382c33e63c2d36462f368657e87168fe5c3d8.tar.gz nuttx-9a5382c33e63c2d36462f368657e87168fe5c3d8.tar.bz2 nuttx-9a5382c33e63c2d36462f368657e87168fe5c3d8.zip |
Update everything under nuttx/drivers to use the corrected syslog interfaces
Diffstat (limited to 'nuttx/drivers/audio')
-rw-r--r-- | nuttx/drivers/audio/wm8904_debug.c | 82 |
1 files changed, 44 insertions, 38 deletions
diff --git a/nuttx/drivers/audio/wm8904_debug.c b/nuttx/drivers/audio/wm8904_debug.c index 13b64c6ad..a45573ee2 100644 --- a/nuttx/drivers/audio/wm8904_debug.c +++ b/nuttx/drivers/audio/wm8904_debug.c @@ -215,10 +215,10 @@ void wm8904_dump_registers(FAR struct audio_lowerhalf_s *dev, { int i; - syslog("WM8904 Registers: %s\n", msg); + syslog(LOG_INFO, "WM8904 Registers: %s\n", msg); for (i = 0; i < WM8904_NREGISTERS; i++) { - syslog("%16s[%02x]: %04x\n", + syslog(LOG_INFO, "%16s[%02x]: %04x\n", g_wm8904_debug[i].regname, g_wm8904_debug[i].regaddr, wm8904_readreg((FAR struct wm8904_dev_s *)dev, g_wm8904_debug[i].regaddr)); @@ -252,9 +252,10 @@ void wm8904_clock_analysis(FAR struct audio_lowerhalf_s *dev, unsigned int tmp; double ftmp; - syslog("WM8904 Clock Analysis: %s\n", msg); + syslog(LOG_INFO, "WM8904 Clock Analysis: %s\n", msg); DEBUGASSERT(priv && priv->lower); - syslog(" MCLK: %lu Hz\n", (unsigned long)priv->lower->mclk); + syslog(LOG_INFO, " MCLK: %lu Hz\n", + (unsigned long)priv->lower->mclk); /* Is the SYSCLK source the FLL? Or MCK? */ @@ -266,7 +267,7 @@ void wm8904_clock_analysis(FAR struct audio_lowerhalf_s *dev, */ sysclk = priv->lower->mclk; - syslog(" SYSCLK Source: MCLK (%s)\n", + syslog(LOG_INFO, " SYSCLK Source: MCLK (%s)\n", (regval & WM8904_MCLK_INV) != 0 ? "inverted" : "not inverted"); } else @@ -291,116 +292,121 @@ void wm8904_clock_analysis(FAR struct audio_lowerhalf_s *dev, switch (regval & WM8904_FLL_CLK_REF_SRC_MASK) { case WM8904_FLL_CLK_REF_SRC_MCLK: - syslog(" FLL Source: MCLK\n"); + syslog(LOG_INFO, " FLL Source: MCLK\n"); break; case WM8904_FLL_CLK_REF_SRC_BCLK: - syslog(" ERROR: FLL source is BCLK: %04x\n", regval); + syslog(LOG_INFO, " ERROR: FLL source is BCLK: %04x\n", + regval); break; case WM8904_FLL_CLK_REF_SRC_LRCLK: - syslog(" ERROR: FLL source is LRCLK: %04x\n", regval); + syslog(LOG_INFO, " ERROR: FLL source is LRCLK: %04x\n", + regval); break; default: - syslog(" ERROR: Unrecognized FLL source: %04x\n", regval); + syslog(LOG_INFO, " ERROR: Unrecognized FLL source: %04x\n", + regval); } - syslog(" Fref: %lu Hz (before divider)\n", fref); + syslog(LOG_INFO, " Fref: %lu Hz (before divider)\n", + fref); switch (regval & WM8904_FLL_CLK_REF_DIV_MASK) { case WM8904_FLL_CLK_REF_DIV1: - syslog(" FLL_CLK_REF_DIV: 1\n"); + syslog(LOG_INFO, " FLL_CLK_REF_DIV: 1\n"); break; case WM8904_FLL_CLK_REF_DIV2: - syslog(" FLL_CLK_REF_DIV: 2\n"); + syslog(LOG_INFO, " FLL_CLK_REF_DIV: 2\n"); fref >>= 1; break; case WM8904_FLL_CLK_REF_DIV4: - syslog(" FLL_CLK_REF_DIV: 4\n"); + syslog(LOG_INFO, " FLL_CLK_REF_DIV: 4\n"); fref >>= 2; break; case WM8904_FLL_CLK_REF_DIV8: - syslog(" FLL_CLK_REF_DIV: 8\n"); + syslog(LOG_INFO, " FLL_CLK_REF_DIV: 8\n"); fref >>= 3; break; } - syslog(" Fref: %lu Hz (after divider)\n", fref); + syslog(LOG_INFO, " Fref: %lu Hz (after divider)\n", fref); regval = wm8904_readreg(priv, WM8904_FLL_CTRL2); frndx = (regval & WM8904_FLL_FRATIO_MASK) >> WM8904_FLL_FRATIO_SHIFT; tmp = (regval & WM8904_FLL_CTRL_RATE_MASK) >> WM8904_FLL_CTRL_RATE_SHIFT; outdiv = ((regval & WM8904_FLL_OUTDIV_MASK) >> WM8904_FLL_OUTDIV_SHIFT) + 1; - syslog(" FLL_CTRL_RATE: Fvco / %u\n", tmp + 1); + syslog(LOG_INFO, " FLL_CTRL_RATE: Fvco / %u\n", tmp + 1); regval = wm8904_readreg(priv, WM8904_FLL_CTRL4); flln = (regval & WM8904_FLL_N_MASK) >> WM8904_FLL_N_SHIFT; tmp = (regval & WM8904_FLL_GAIN_MASK) >> WM8904_FLL_GAIN_SHIFT; - syslog(" FLL_GAIN: %u\n", (1 << tmp)); + syslog(LOG_INFO, " FLL_GAIN: %u\n", (1 << tmp)); fllk = wm8904_readreg(priv, WM8904_FLL_CTRL3); nk = (double)flln + ((double)fllk / 65536.0); fratio = g_fllratio[frndx]; - syslog(" FLL_FRATIO: %u\n", fratio); - syslog(" FLL_OUTDIV: %u\n", outdiv); - syslog(" FLL_N.K: %u.%05u\n", flln, fllk); + syslog(LOG_INFO, " FLL_FRATIO: %u\n", fratio); + syslog(LOG_INFO, " FLL_OUTDIV: %u\n", outdiv); + syslog(LOG_INFO, " FLL_N.K: %u.%05u\n", flln, fllk); ftmp = nk * (double)fref * (double)fratio; fvco = (uint32_t)ftmp; - syslog(" Fvco: %lu Hz\n", (unsigned long)fvco); + syslog(LOG_INFO, " Fvco: %lu Hz\n", (unsigned long)fvco); fout = fvco / outdiv; - syslog(" Fout: %lu Hz\n", (unsigned long)fout); + syslog(LOG_INFO, " Fout: %lu Hz\n", (unsigned long)fout); regval = wm8904_readreg(priv, WM8904_FLL_CTRL1); - syslog(" FLL_FRACN_ENA: %s\n", + syslog(LOG_INFO, " FLL_FRACN_ENA: %s\n", (regval & WM8904_FLL_FRACN_ENA) != 0 ? "Enabled" : "Disabled"); - syslog(" FLL_OSC_ENA: %s\n", + syslog(LOG_INFO, " FLL_OSC_ENA: %s\n", (regval & WM8904_FLL_OSC_ENA) != 0 ? "Enabled" : "Disabled"); - syslog(" FLL_ENA: %s\n", + syslog(LOG_INFO, " FLL_ENA: %s\n", (regval & WM8904_FLL_ENA) != 0 ? "Enabled" : "Disabled"); if ((regval & WM8904_FLL_ENA) == 0) { - syslog(" No SYSCLK\n"); + syslog(LOG_INFO, " No SYSCLK\n"); return; } sysclk = fout; } - syslog(" SYSCLK: %lu Hz (before divider)\n", (unsigned long)sysclk); + syslog(LOG_INFO, " SYSCLK: %lu Hz (before divider)\n", + (unsigned long)sysclk); regval = wm8904_readreg(priv, WM8904_CLKRATE0); if ((regval & WM8904_MCLK_DIV) == WM8904_MCLK_DIV1) { - syslog(" MCLK_DIV: 1\n"); + syslog(LOG_INFO, " MCLK_DIV: 1\n"); } else { - syslog(" MCLK_DIV: 2\n"); + syslog(LOG_INFO, " MCLK_DIV: 2\n"); sysclk >>=1; } - syslog(" SYSCLK: %lu (after divider)\n", (unsigned long)sysclk); + syslog(LOG_INFO, " SYSCLK: %lu (after divider)\n", (unsigned long)sysclk); regval = wm8904_readreg(priv, WM8904_CLKRATE2); - syslog(" CLK_SYS_ENA: %s\n", + syslog(LOG_INFO, " CLK_SYS_ENA: %s\n", (regval & WM8904_CLK_SYS_ENA) != 0 ? "Enabled" : "Disabled"); if ((regval & WM8904_CLK_SYS_ENA) == 0) { - syslog(" No SYSCLK\n"); + syslog(LOG_INFO, " No SYSCLK\n"); return; } @@ -409,15 +415,15 @@ void wm8904_clock_analysis(FAR struct audio_lowerhalf_s *dev, tmp = g_sysclk_scaleb1[tmp]; ftmp = (double)tmp / 2.0; - syslog(" BCLK_DIV: SYSCLK / %u.%01u\n", + syslog(LOG_INFO, " BCLK_DIV: SYSCLK / %u.%01u\n", (unsigned int)(tmp >> 1), (unsigned int)(5 * (tmp & 1))); bclk = (uint32_t)(sysclk / ftmp); - syslog(" BCLK: %lu Hz\n", (unsigned long)bclk); + syslog(LOG_INFO, " BCLK: %lu Hz\n", (unsigned long)bclk); regval = wm8904_readreg(priv, WM8904_AIF1); - syslog(" BCLK_DIR: %s\n", + syslog(LOG_INFO, " BCLK_DIR: %s\n", (regval & WM8904_BCLK_DIR) != 0 ? "Output" : "Input"); regval = wm8904_readreg(priv, WM8904_AIF3); @@ -425,9 +431,9 @@ void wm8904_clock_analysis(FAR struct audio_lowerhalf_s *dev, lrclk = bclk / tmp; - syslog(" LRCLK_RATE: BCLK / %lu\n", (unsigned long)tmp); - syslog(" LRCLK: %lu Hz\n", (unsigned long)lrclk); - syslog(" LRCLK_DIR: %s\n", + syslog(LOG_INFO, " LRCLK_RATE: BCLK / %lu\n", (unsigned long)tmp); + syslog(LOG_INFO, " LRCLK: %lu Hz\n", (unsigned long)lrclk); + syslog(LOG_INFO, " LRCLK_DIR: %s\n", (regval & WM8904_LRCLK_DIR) != 0 ? "Output" : "Input"); } #endif /* CONFIG_WM8904_CLKDEBUG */ |