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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-07-04 13:50:14 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-07-04 13:50:14 +0000 |
commit | b786ce10919fd75dee9475558a329eec631fc43b (patch) | |
tree | 075f2a24c1e41a4e3e96517495ca1cba328f0f69 /nuttx | |
parent | ed4eae60aaa1d95708a752971ab30c5587878268 (diff) | |
download | nuttx-b786ce10919fd75dee9475558a329eec631fc43b.tar.gz nuttx-b786ce10919fd75dee9475558a329eec631fc43b.tar.bz2 nuttx-b786ce10919fd75dee9475558a329eec631fc43b.zip |
Fix SSP0 hard fault
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2771 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx')
-rw-r--r-- | nuttx/ChangeLog | 4 | ||||
-rw-r--r-- | nuttx/Documentation/NuttX.html | 4 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c | 154 |
3 files changed, 115 insertions, 47 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 73d58ff8e..0c89ae7e9 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -1164,3 +1164,7 @@ interrupts. * arch/arm/src/lpc17xx/lp17_clockconfig.c - Power was not being provided to GPIO module. This is a critical bugfix! + * arch/arm/src/lpc17xx/lpc17_serial.c - Improved logic to handle + missed TX interrupts. + * arch/arm/src/lpc17xx/lpc17_ssp.c - Fix a hard fault during SSP + initialization.
\ No newline at end of file diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index b735eacd3..9d5530b02 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -1839,6 +1839,10 @@ nuttx-5.8 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr> interrupts. * arch/arm/src/lpc17xx/lp17_clockconfig.c - Power was not being provided to GPIO module. This is a critical bugfix! + * arch/arm/src/lpc17xx/lpc17_serial.c - Improved logic to handle + missed TX interrupts. + * arch/arm/src/lpc17xx/lpc17_ssp.c - Fix a hard fault during SSP + initialization. pascal-2.1 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr> diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c index 8e6a25da4..a4ead4c20 100755 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ssp.c @@ -142,6 +142,15 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t ch); static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords); static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords); +/* Initialization */ + +#ifdef CONFIG_LPC17_SSP0 +static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void); +#endif +#ifdef CONFIG_LPC17_SSP1 +static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void); +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -225,7 +234,7 @@ static struct lpc17_sspdev_s g_ssp1dev = static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset) { - return ssp_getreg(priv, priv->sspbase + offset); + return getreg32(priv->sspbase + (uint32_t)offset); } /************************************************************************************ @@ -246,7 +255,7 @@ static inline uint32_t ssp_getreg(FAR struct lpc17_sspdev_s *priv, uint8_t offse static inline void ssp_putreg(FAR struct lpc17_sspdev_s *priv, uint8_t offset, uint32_t value) { - putreg32(value, priv->sspbase + offset); + putreg32(value, priv->sspbase + (uint32_t)offset); } /**************************************************************************** @@ -671,47 +680,24 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw } /**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_spiinitialize + * Name: lpc17_ssp0initialize * * Description: - * Initialize the selected SPI port + * Initialize the SSP0 * * Input Parameter: - * Port number (for hardware that has mutiple SPI interfaces) + * None * * Returned Value: * Valid SPI device structure reference on succcess; a NULL on failure * ****************************************************************************/ -FAR struct spi_dev_s *up_spiinitialize(int port) +#ifdef CONFIG_LPC17_SSP0 +static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void) { - FAR struct lpc17_sspdev_s *priv; irqstate_t flags; uint32_t regval; - int i; - - /* Only the SSP0 and SSP1 interfaces are supported */ - - switch (port) - { -#ifdef CONFIG_LPC17_SSP0 - case 0: - priv = &g_ssp0dev; - break; -#endif -#ifdef CONFIG_LPC17_SSP1 - case 1: - priv = &g_ssp1dev; - break; -#endif - default: - return NULL; - } /* Configure multiplexed pins as connected on the board. Chip select * pins must be configured by board-specific logic. All SSP0 pins and @@ -723,47 +709,122 @@ FAR struct spi_dev_s *up_spiinitialize(int port) */ flags = irqsave(); -#ifdef CONFIG_LPC17_SSP0 lpc17_configgpio(GPIO_SSP0_SCK); lpc17_configgpio(GPIO_SSP0_MISO); lpc17_configgpio(GPIO_SSP0_MOSI); -#endif - -#ifdef CONFIG_LPC17_SSP1 - lpc17_configgpio(GPIO_SSP1_SCK); - lpc17_configgpio(GPIO_SSP1_MISO); - lpc17_configgpio(GPIO_SSP1_MOSI); -#endif /* Configure clocking */ -#ifdef CONFIG_LPC17_SSP0 regval = getreg32(LPC17_SYSCON_PCLKSEL1); regval &= ~SYSCON_PCLKSEL1_SSP0_MASK; regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT); putreg32(regval, LPC17_SYSCON_PCLKSEL1); + + /* Enable peripheral clocking to SSP0 */ + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCSSP0; + putreg32(regval, LPC17_SYSCON_PCONP); + irqrestore(flags); + + return &g_ssp0dev; +} #endif +/**************************************************************************** + * Name: lpc17_ssp1initialize + * + * Description: + * Initialize the SSP1 + * + * Input Parameter: + * None + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + #ifdef CONFIG_LPC17_SSP1 +static inline FAR struct spi_dev_s *lpc17_ssp1initialize(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Configure multiplexed pins as connected on the board. Chip select + * pins must be configured by board-specific logic. All SSP0 pins and + * one SSP1 pin (SCK) have multiple, alternative pin selection. + * Definitions in the board.h file must be provided to resolve the + * board-specific pin configuration like: + * + * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 + */ + + flags = irqsave(); + lpc17_configgpio(GPIO_SSP1_SCK); + lpc17_configgpio(GPIO_SSP1_MISO); + lpc17_configgpio(GPIO_SSP1_MOSI); + + /* Configure clocking */ + regval = getreg32(LPC17_SYSCON_PCLKSEL0); regval &= ~SYSCON_PCLKSEL0_SSP1_MASK; regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT); putreg32(regval, LPC17_SYSCON_PCLKSEL0); -#endif /* Enable peripheral clocking to SSP0 and SSP1 */ regval = getreg32(LPC17_SYSCON_PCONP); - regval &= ~(SYSCON_PCONP_PCSSP0|SYSCON_PCONP_PCSSP1); + regval |= SYSCON_PCONP_PCSSP1; + putreg32(regval, LPC17_SYSCON_PCONP); + irqrestore(flags); + + return &g_ssp1dev; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize the selected SPI port + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *up_spiinitialize(int port) +{ + FAR struct lpc17_sspdev_s *priv; + uint32_t regval; + int i; + + /* Only the SSP0 and SSP1 interfaces are supported */ + + switch (port) + { #ifdef CONFIG_LPC17_SSP0 - regval |= SYSCON_PCONP_PCSSP0; + case 0: + priv = lpc17_ssp0initialize(); + break; #endif #ifdef CONFIG_LPC17_SSP1 - regval |= SYSCON_PCONP_PCSSP1; + case 1: + priv = lpc17_ssp1initialize(); + break; #endif - putreg32(regval, LPC17_SYSCON_PCONP); - irqrestore(flags); - + default: + return NULL; + } + /* Configure 8-bit SPI mode */ ssp_putreg(priv, LPC17_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI); @@ -795,7 +856,6 @@ FAR struct spi_dev_s *up_spiinitialize(int port) regval = ssp_getreg(priv, LPC17_SSP_CR1_OFFSET); ssp_putreg(priv, LPC17_SSP_CR1_OFFSET, regval | SSP_CR1_SSE); - for (i = 0; i < LPC17_SSP_FIFOSZ; i++) { (void)ssp_getreg(priv, LPC17_SSP_DR_OFFSET); |