Simplify I2C master/slave addresing to simplify driver development

5 files changed, 216 insertions, 261 deletions

diff --git a/nuttx/arch/arm/src/tiva/chip/cc3200_memorymap.h b/nuttx/arch/arm/src/tiva/chip/cc3200_memorymap.h
index d47971574..a48500f63 100644
--- a/nuttx/arch/arm/src/tiva/chip/cc3200_memorymap.h
+++ b/nuttx/arch/arm/src/tiva/chip/cc3200_memorymap.h
@@ -84,18 +84,17 @@
 
 #if defined(CONFIG_ARCH_CHIP_CC3200)
 
-#  define TIVA_WDOG0_BASE     (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
+#  define TIVA_WDOG0_BASE     (TIVA_PERIPH_BASE + 0x00000)  /* -0x00fff: Watchdog Timer 0 */
 
-#  define TIVA_GPIOA_BASE     (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
-#  define TIVA_GPIOB_BASE     (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
-#  define TIVA_GPIOC_BASE     (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
-#  define TIVA_GPIOD_BASE     (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+#  define TIVA_GPIOA_BASE     (TIVA_PERIPH_BASE + 0x04000)  /* -0x04fff: GPIO Port A */
+#  define TIVA_GPIOB_BASE     (TIVA_PERIPH_BASE + 0x05000)  /* -0x05fff: GPIO Port B */
+#  define TIVA_GPIOC_BASE     (TIVA_PERIPH_BASE + 0x06000)  /* -0x06fff: GPIO Port C */
+#  define TIVA_GPIOD_BASE     (TIVA_PERIPH_BASE + 0x07000)  /* -0x07fff: GPIO Port D */
 
-#  define TIVA_UART0_BASE     (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
-#  define TIVA_UART1_BASE     (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+#  define TIVA_UART0_BASE     (TIVA_PERIPH_BASE + 0x0c000)  /* -0x0cfff: UART0 */
+#  define TIVA_UART1_BASE     (TIVA_PERIPH_BASE + 0x0d000)  /* -0x0dfff: UART1 */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fbf: I2C Slave 0 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C0 */
 
 #  define TIVA_TIMER0_BASE    (TIVA_PERIPH_BASE + 0x30000)  /* -0x30fff: 16/32 Timer 0 */
 #  define TIVA_TIMER1_BASE    (TIVA_PERIPH_BASE + 0x31000)  /* -0x31fff: 16/32 Timer 1 */
diff --git a/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h
index 36dee7215..8d3b5097d 100644
--- a/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h
+++ b/nuttx/arch/arm/src/tiva/chip/lm3s_memorymap.h
@@ -116,10 +116,8 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x21fff: I2C1 */
                                                             /* -0x23fff: Reserved */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
@@ -157,8 +155,7 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
                                                             /* -0x23fff: Reserved */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
@@ -198,10 +195,8 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x21fff: I2C1 */
                                                             /* -0x23fff: Reserved */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
@@ -243,8 +238,7 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
                                                             /* -0x23fff: Reserved */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
@@ -290,10 +284,8 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fff: I2C Slave 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fff: I2C Slave 1 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C1 */
                                                             /* -0x23fff: Reserved */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
diff --git a/nuttx/arch/arm/src/tiva/chip/lm4f_memorymap.h b/nuttx/arch/arm/src/tiva/chip/lm4f_memorymap.h
index f4f97edc2..4ec56359c 100644
--- a/nuttx/arch/arm/src/tiva/chip/lm4f_memorymap.h
+++ b/nuttx/arch/arm/src/tiva/chip/lm4f_memorymap.h
@@ -101,18 +101,10 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fbf: I2C Slave 0 */
-#  define TIVA_I2CSC0_BASE    (TIVA_PERIPH_BASE + 0x20fc0)  /* -0x20fff: I2C Status and Control 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fbf: I2C Slave 1 */
-#  define TIVA_I2CSC1_BASE    (TIVA_PERIPH_BASE + 0x21fc0)  /* -0x21fff: I2C Status and Control 1 */
-#  define TIVA_I2CM2_BASE     (TIVA_PERIPH_BASE + 0x22000)  /* -0x227ff: I2C Master 2 */
-#  define TIVA_I2CS2_BASE     (TIVA_PERIPH_BASE + 0x22800)  /* -0x22fbf: I2C Slave 2 */
-#  define TIVA_I2CSC2_BASE    (TIVA_PERIPH_BASE + 0x22fc0)  /* -0x22fff: I2C Status and Control 2 */
-#  define TIVA_I2CM3_BASE     (TIVA_PERIPH_BASE + 0x23000)  /* -0x237ff: I2C Master 3 */
-#  define TIVA_I2CS3_BASE     (TIVA_PERIPH_BASE + 0x23800)  /* -0x23fbf: I2C Slave 3 */
-#  define TIVA_I2CSC3_BASE    (TIVA_PERIPH_BASE + 0x23fc0)  /* -0x23fff: I2C Status and Control 3 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x21fff: I2C1 */
+#  define TIVA_I2C2_BASE      (TIVA_PERIPH_BASE + 0x22000)  /* -0x22fff: I2C2 */
+#  define TIVA_I2C3_BASE      (TIVA_PERIPH_BASE + 0x23000)  /* -0x23fff: I2C3 */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
                                                             /* -0x2ffff: Reserved */
diff --git a/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h b/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h
index 1c13464b5..9d2358a43 100644
--- a/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h
+++ b/nuttx/arch/arm/src/tiva/chip/tiva_i2c.h
@@ -77,32 +77,32 @@
 
 /* I2C Slave */
 
-#define TIVA_I2CS_OAR_OFFSET           0x0000 /* I2C Slave Own Address */
-#define TIVA_I2CS_CSR_OFFSET           0x0004 /* I2C Slave Control/Status */
-#define TIVA_I2CS_DR_OFFSET            0x0008 /* I2C Slave Data */
-#define TIVA_I2CS_IMR_OFFSET           0x000c /* I2C Slave Interrupt Mask */
-#define TIVA_I2CS_RIS_OFFSET           0x0010 /* I2C Slave Raw Interrupt Status */
-#define TIVA_I2CS_MIS_OFFSET           0x0014 /* I2C Slave Masked Interrupt Status */
-#define TIVA_I2CS_ICR_OFFSET           0x0018 /* I2C Slave Interrupt Clear */
+#define TIVA_I2CS_OAR_OFFSET           0x0800 /* I2C Slave Own Address */
+#define TIVA_I2CS_CSR_OFFSET           0x0804 /* I2C Slave Control/Status */
+#define TIVA_I2CS_DR_OFFSET            0x0808 /* I2C Slave Data */
+#define TIVA_I2CS_IMR_OFFSET           0x080c /* I2C Slave Interrupt Mask */
+#define TIVA_I2CS_RIS_OFFSET           0x0810 /* I2C Slave Raw Interrupt Status */
+#define TIVA_I2CS_MIS_OFFSET           0x0814 /* I2C Slave Masked Interrupt Status */
+#define TIVA_I2CS_ICR_OFFSET           0x0818 /* I2C Slave Interrupt Clear */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS_SOAR2_OFFSET       0x001c /* I2C Slave Own Address 2 */
-#  define TIVA_I2CS_ACKCTL_OFFSET      0x0020 /* I2C Slave ACK Control */
+#  define TIVA_I2CS_SOAR2_OFFSET       0x081c /* I2C Slave Own Address 2 */
+#  define TIVA_I2CS_ACKCTL_OFFSET      0x0820 /* I2C Slave ACK Control */
 #endif
 
 /* I2C Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC_FIFODATA_OFFSET   0x0000 /* I2C FIFO Data */
-#  define TIVA_I2CSC_FIFOCTL_OFFSET    0x0004 /* I2C FIFO Control */
-#  define TIVA_I2CSC_FIFOSTATUS_OFFSET 0x0008 /* I2C FIFO Status */
+#  define TIVA_I2CSC_FIFODATA_OFFSET   0x0f00 /* I2C FIFO Data */
+#  define TIVA_I2CSC_FIFOCTL_OFFSET    0x0f04 /* I2C FIFO Control */
+#  define TIVA_I2CSC_FIFOSTATUS_OFFSET 0x0f08 /* I2C FIFO Status */
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC_PP_OFFSET         0x00c0 /* I2C Peripheral Properties */
-#  define TIVA_I2CSC_PC_OFFSET         0x00c4 /* I2C Peripheral Configuration */
+#  define TIVA_I2CSC_PP_OFFSET         0x0fc0 /* I2C Peripheral Properties */
+#  define TIVA_I2CSC_PC_OFFSET         0x0fc4 /* I2C Peripheral Configuration */
 #endif
 
 /* I2C Register Addresses ***********************************************************/
@@ -111,59 +111,59 @@
 
 /* I2C0 Master */
 
-#define TIVA_I2CM0_SA                  (TIVA_I2CM0_BASE + TIVA_I2CM_SA_OFFSET)
-#define TIVA_I2CM0_CS                  (TIVA_I2CM0_BASE + TIVA_I2CM_CS_OFFSET)
-#define TIVA_I2CM0_DR                  (TIVA_I2CM0_BASE + TIVA_I2CM_DR_OFFSET)
-#define TIVA_I2CM0_TPR                 (TIVA_I2CM0_BASE + TIVA_I2CM_TPR_OFFSET)
-#define TIVA_I2CM0_IMR                 (TIVA_I2CM0_BASE + TIVA_I2CM_IMR_OFFSET)
-#define TIVA_I2CM0_RIS                 (TIVA_I2CM0_BASE + TIVA_I2CM_RIS_OFFSET)
-#define TIVA_I2CM0_MIS                 (TIVA_I2CM0_BASE + TIVA_I2CM_MIS_OFFSET)
-#define TIVA_I2CM0_ICR                 (TIVA_I2CM0_BASE + TIVA_I2CM_ICR_OFFSET)
-#define TIVA_I2CM0_CR                  (TIVA_I2CM0_BASE + TIVA_I2CM_CR_OFFSET)
+#define TIVA_I2CM0_SA                  (TIVA_I2C0_BASE + TIVA_I2CM_SA_OFFSET)
+#define TIVA_I2CM0_CS                  (TIVA_I2C0_BASE + TIVA_I2CM_CS_OFFSET)
+#define TIVA_I2CM0_DR                  (TIVA_I2C0_BASE + TIVA_I2CM_DR_OFFSET)
+#define TIVA_I2CM0_TPR                 (TIVA_I2C0_BASE + TIVA_I2CM_TPR_OFFSET)
+#define TIVA_I2CM0_IMR                 (TIVA_I2C0_BASE + TIVA_I2CM_IMR_OFFSET)
+#define TIVA_I2CM0_RIS                 (TIVA_I2C0_BASE + TIVA_I2CM_RIS_OFFSET)
+#define TIVA_I2CM0_MIS                 (TIVA_I2C0_BASE + TIVA_I2CM_MIS_OFFSET)
+#define TIVA_I2CM0_ICR                 (TIVA_I2C0_BASE + TIVA_I2CM_ICR_OFFSET)
+#define TIVA_I2CM0_CR                  (TIVA_I2C0_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM0_CLKOCNT           (TIVA_I2CM0_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
-#  define TIVA_I2CM0_BMON              (TIVA_I2CM0_BASE + TIVA_I2CM_BMON_OFFSET)
+#  define TIVA_I2CM0_CLKOCNT           (TIVA_I2C0_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
+#  define TIVA_I2CM0_BMON              (TIVA_I2C0_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM0_BLEN              (TIVA_I2CM0_BASE + TIVA_I2CM_BLEN_OFFSET)
-#  define TIVA_I2CM0_BCNT              (TIVA_I2CM0_BASE + TIVA_I2CM_BCNT_OFFSET)
+#  define TIVA_I2CM0_BLEN              (TIVA_I2C0_BASE + TIVA_I2CM_BLEN_OFFSET)
+#  define TIVA_I2CM0_BCNT              (TIVA_I2C0_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
-#  define TIVA_I2CM0_CR2               (TIVA_I2CM0_BASE + TIVA_I2CM_CR2_OFFSET)
+#  define TIVA_I2CM0_CR2               (TIVA_I2C0_BASE + TIVA_I2CM_CR2_OFFSET)
 #endif
 
 /* I2C0 Slave */
 
-#define TIVA_I2CS0_OAR                 (TIVA_I2CS0_BASE + TIVA_I2CS_OAR_OFFSET)
-#define TIVA_I2CS0_CSR                 (TIVA_I2CS0_BASE + TIVA_I2CS_CSR_OFFSET)
-#define TIVA_I2CS0_DR                  (TIVA_I2CS0_BASE + TIVA_I2CS_DR_OFFSET)
-#define TIVA_I2CS0_IMR                 (TIVA_I2CS0_BASE + TIVA_I2CS_IMR_OFFSET)
-#define TIVA_I2CS0_RIS                 (TIVA_I2CS0_BASE + TIVA_I2CS_RIS_OFFSET)
-#define TIVA_I2CS0_MIS                 (TIVA_I2CS0_BASE + TIVA_I2CS_MIS_OFFSET)
-#define TIVA_I2CS0_ICR                 (TIVA_I2CS0_BASE + TIVA_I2CS_ICR_OFFSET)
+#define TIVA_I2CS0_OAR                 (TIVA_I2C0_BASE + TIVA_I2CS_OAR_OFFSET)
+#define TIVA_I2CS0_CSR                 (TIVA_I2C0_BASE + TIVA_I2CS_CSR_OFFSET)
+#define TIVA_I2CS0_DR                  (TIVA_I2C0_BASE + TIVA_I2CS_DR_OFFSET)
+#define TIVA_I2CS0_IMR                 (TIVA_I2C0_BASE + TIVA_I2CS_IMR_OFFSET)
+#define TIVA_I2CS0_RIS                 (TIVA_I2C0_BASE + TIVA_I2CS_RIS_OFFSET)
+#define TIVA_I2CS0_MIS                 (TIVA_I2C0_BASE + TIVA_I2CS_MIS_OFFSET)
+#define TIVA_I2CS0_ICR                 (TIVA_I2C0_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS0_SOAR2             (TIVA_I2CS0_BASE + TIVA_I2CS_SOAR2_OFFSET)
-#  define TIVA_I2CS0_ACKCTL            (TIVA_I2CS0_BASE + TIVA_I2CS_ACKCTL_OFFSET)
+#  define TIVA_I2CS0_SOAR2             (TIVA_I2C0_BASE + TIVA_I2CS_SOAR2_OFFSET)
+#  define TIVA_I2CS0_ACKCTL            (TIVA_I2C0_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C0 Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC0_FIFODATA         (TIVA_I2CSC0_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
-#  define TIVA_I2CSC0_FIFOCTL          (TIVA_I2CSC0_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
-#  define TIVA_I2CSC0_FIFOSTATUS       (TIVA_I2CSC0_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
+#  define TIVA_I2CSC0_FIFODATA         (TIVA_I2C0_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
+#  define TIVA_I2CSC0_FIFOCTL          (TIVA_I2C0_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
+#  define TIVA_I2CSC0_FIFOSTATUS       (TIVA_I2C0_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC0_PP               (TIVA_I2CSC0_BASE + TIVA_I2CSC_PP_OFFSET)
-#  define TIVA_I2CSC0_PC               (TIVA_I2CSC0_BASE + TIVA_I2CSC_PC_OFFSET)
+#  define TIVA_I2CSC0_PP               (TIVA_I2C0_BASE + TIVA_I2CSC_PP_OFFSET)
+#  define TIVA_I2CSC0_PC               (TIVA_I2C0_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
 #endif /* TIVA_NI2C > 0 */
 
@@ -171,59 +171,59 @@
 
 /* I2C1 Master */
 
-#define TIVA_I2CM1_SA                  (TIVA_I2CM1_BASE + TIVA_I2CM_SA_OFFSET)
-#define TIVA_I2CM1_CS                  (TIVA_I2CM1_BASE + TIVA_I2CM_CS_OFFSET)
-#define TIVA_I2CM1_DR                  (TIVA_I2CM1_BASE + TIVA_I2CM_DR_OFFSET)
-#define TIVA_I2CM1_TPR                 (TIVA_I2CM1_BASE + TIVA_I2CM_TPR_OFFSET)
-#define TIVA_I2CM1_IMR                 (TIVA_I2CM1_BASE + TIVA_I2CM_IMR_OFFSET)
-#define TIVA_I2CM1_RIS                 (TIVA_I2CM1_BASE + TIVA_I2CM_RIS_OFFSET)
-#define TIVA_I2CM1_MIS                 (TIVA_I2CM1_BASE + TIVA_I2CM_MIS_OFFSET)
-#define TIVA_I2CM1_ICR                 (TIVA_I2CM1_BASE + TIVA_I2CM_ICR_OFFSET)
-#define TIVA_I2CM1_CR                  (TIVA_I2CM1_BASE + TIVA_I2CM_CR_OFFSET)
+#define TIVA_I2CM1_SA                  (TIVA_I2C1_BASE + TIVA_I2CM_SA_OFFSET)
+#define TIVA_I2CM1_CS                  (TIVA_I2C1_BASE + TIVA_I2CM_CS_OFFSET)
+#define TIVA_I2CM1_DR                  (TIVA_I2C1_BASE + TIVA_I2CM_DR_OFFSET)
+#define TIVA_I2CM1_TPR                 (TIVA_I2C1_BASE + TIVA_I2CM_TPR_OFFSET)
+#define TIVA_I2CM1_IMR                 (TIVA_I2C1_BASE + TIVA_I2CM_IMR_OFFSET)
+#define TIVA_I2CM1_RIS                 (TIVA_I2C1_BASE + TIVA_I2CM_RIS_OFFSET)
+#define TIVA_I2CM1_MIS                 (TIVA_I2C1_BASE + TIVA_I2CM_MIS_OFFSET)
+#define TIVA_I2CM1_ICR                 (TIVA_I2C1_BASE + TIVA_I2CM_ICR_OFFSET)
+#define TIVA_I2CM1_CR                  (TIVA_I2C1_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM1_CLKOCNT           (TIVA_I2CM1_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
-#  define TIVA_I2CM1_BMON              (TIVA_I2CM1_BASE + TIVA_I2CM_BMON_OFFSET)
+#  define TIVA_I2CM1_CLKOCNT           (TIVA_I2C1_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
+#  define TIVA_I2CM1_BMON              (TIVA_I2C1_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM1_BLEN              (TIVA_I2CM1_BASE + TIVA_I2CM_BLEN_OFFSET)
-#  define TIVA_I2CM1_BCNT              (TIVA_I2CM1_BASE + TIVA_I2CM_BCNT_OFFSET)
+#  define TIVA_I2CM1_BLEN              (TIVA_I2C1_BASE + TIVA_I2CM_BLEN_OFFSET)
+#  define TIVA_I2CM1_BCNT              (TIVA_I2C1_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
-#  define TIVA_I2CM1_CR2               (TIVA_I2CM1_BASE + TIVA_I2CM_CR2_OFFSET)
+#  define TIVA_I2CM1_CR2               (TIVA_I2C1_BASE + TIVA_I2CM_CR2_OFFSET)
 #endif
 
 /* I2C1 Slave */
 
-#define TIVA_I2CS1_OAR                 (TIVA_I2CS1_BASE + TIVA_I2CS_OAR_OFFSET)
-#define TIVA_I2CS1_CSR                 (TIVA_I2CS1_BASE + TIVA_I2CS_CSR_OFFSET)
-#define TIVA_I2CS1_DR                  (TIVA_I2CS1_BASE + TIVA_I2CS_DR_OFFSET)
-#define TIVA_I2CS1_IMR                 (TIVA_I2CS1_BASE + TIVA_I2CS_IMR_OFFSET)
-#define TIVA_I2CS1_RIS                 (TIVA_I2CS1_BASE + TIVA_I2CS_RIS_OFFSET)
-#define TIVA_I2CS1_MIS                 (TIVA_I2CS1_BASE + TIVA_I2CS_MIS_OFFSET)
-#define TIVA_I2CS1_ICR                 (TIVA_I2CS1_BASE + TIVA_I2CS_ICR_OFFSET)
+#define TIVA_I2CS1_OAR                 (TIVA_I2C1_BASE + TIVA_I2CS_OAR_OFFSET)
+#define TIVA_I2CS1_CSR                 (TIVA_I2C1_BASE + TIVA_I2CS_CSR_OFFSET)
+#define TIVA_I2CS1_DR                  (TIVA_I2C1_BASE + TIVA_I2CS_DR_OFFSET)
+#define TIVA_I2CS1_IMR                 (TIVA_I2C1_BASE + TIVA_I2CS_IMR_OFFSET)
+#define TIVA_I2CS1_RIS                 (TIVA_I2C1_BASE + TIVA_I2CS_RIS_OFFSET)
+#define TIVA_I2CS1_MIS                 (TIVA_I2C1_BASE + TIVA_I2CS_MIS_OFFSET)
+#define TIVA_I2CS1_ICR                 (TIVA_I2C1_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS1_SOAR2             (TIVA_I2CS1_BASE + TIVA_I2CS_SOAR2_OFFSET)
-#  define TIVA_I2CS1_ACKCTL            (TIVA_I2CS1_BASE + TIVA_I2CS_ACKCTL_OFFSET)
+#  define TIVA_I2CS1_SOAR2             (TIVA_I2C1_BASE + TIVA_I2CS_SOAR2_OFFSET)
+#  define TIVA_I2CS1_ACKCTL            (TIVA_I2C1_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C1 Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC1_FIFODATA         (TIVA_I2CSC1_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
-#  define TIVA_I2CSC1_FIFOCTL          (TIVA_I2CSC1_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
-#  define TIVA_I2CSC1_FIFOSTATUS       (TIVA_I2CSC1_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
+#  define TIVA_I2CSC1_FIFODATA         (TIVA_I2C1_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
+#  define TIVA_I2CSC1_FIFOCTL          (TIVA_I2C1_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
+#  define TIVA_I2CSC1_FIFOSTATUS       (TIVA_I2C1_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC1_PP               (TIVA_I2CSC1_BASE + TIVA_I2CSC_PP_OFFSET)
-#  define TIVA_I2CSC1_PC               (TIVA_I2CSC1_BASE + TIVA_I2CSC_PC_OFFSET)
+#  define TIVA_I2CSC1_PP               (TIVA_I2C1_BASE + TIVA_I2CSC_PP_OFFSET)
+#  define TIVA_I2CSC1_PC               (TIVA_I2C1_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
 #endif /* TIVA_NI2C > 1 */
 
@@ -231,59 +231,59 @@
 
 /* I2C2 Master */
 
-#define TIVA_I2CM2_SA                  (TIVA_I2CM2_BASE + TIVA_I2CM_SA_OFFSET)
-#define TIVA_I2CM2_CS                  (TIVA_I2CM2_BASE + TIVA_I2CM_CS_OFFSET)
-#define TIVA_I2CM2_DR                  (TIVA_I2CM2_BASE + TIVA_I2CM_DR_OFFSET)
-#define TIVA_I2CM2_TPR                 (TIVA_I2CM2_BASE + TIVA_I2CM_TPR_OFFSET)
-#define TIVA_I2CM2_IMR                 (TIVA_I2CM2_BASE + TIVA_I2CM_IMR_OFFSET)
-#define TIVA_I2CM2_RIS                 (TIVA_I2CM2_BASE + TIVA_I2CM_RIS_OFFSET)
-#define TIVA_I2CM2_MIS                 (TIVA_I2CM2_BASE + TIVA_I2CM_MIS_OFFSET)
-#define TIVA_I2CM2_ICR                 (TIVA_I2CM2_BASE + TIVA_I2CM_ICR_OFFSET)
-#define TIVA_I2CM2_CR                  (TIVA_I2CM2_BASE + TIVA_I2CM_CR_OFFSET)
+#define TIVA_I2CM2_SA                  (TIVA_I2C2_BASE + TIVA_I2CM_SA_OFFSET)
+#define TIVA_I2CM2_CS                  (TIVA_I2C2_BASE + TIVA_I2CM_CS_OFFSET)
+#define TIVA_I2CM2_DR                  (TIVA_I2C2_BASE + TIVA_I2CM_DR_OFFSET)
+#define TIVA_I2CM2_TPR                 (TIVA_I2C2_BASE + TIVA_I2CM_TPR_OFFSET)
+#define TIVA_I2CM2_IMR                 (TIVA_I2C2_BASE + TIVA_I2CM_IMR_OFFSET)
+#define TIVA_I2CM2_RIS                 (TIVA_I2C2_BASE + TIVA_I2CM_RIS_OFFSET)
+#define TIVA_I2CM2_MIS                 (TIVA_I2C2_BASE + TIVA_I2CM_MIS_OFFSET)
+#define TIVA_I2CM2_ICR                 (TIVA_I2C2_BASE + TIVA_I2CM_ICR_OFFSET)
+#define TIVA_I2CM2_CR                  (TIVA_I2C2_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM2_CLKOCNT           (TIVA_I2CM2_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
-#  define TIVA_I2CM2_BMON              (TIVA_I2CM2_BASE + TIVA_I2CM_BMON_OFFSET)
+#  define TIVA_I2CM2_CLKOCNT           (TIVA_I2C2_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
+#  define TIVA_I2CM2_BMON              (TIVA_I2C2_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM2_BLEN              (TIVA_I2CM2_BASE + TIVA_I2CM_BLEN_OFFSET)
-#  define TIVA_I2CM2_BCNT              (TIVA_I2CM2_BASE + TIVA_I2CM_BCNT_OFFSET)
+#  define TIVA_I2CM2_BLEN              (TIVA_I2C2_BASE + TIVA_I2CM_BLEN_OFFSET)
+#  define TIVA_I2CM2_BCNT              (TIVA_I2C2_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
-#  define TIVA_I2CM2_CR2               (TIVA_I2CM2_BASE + TIVA_I2CM_CR2_OFFSET)
+#  define TIVA_I2CM2_CR2               (TIVA_I2C2_BASE + TIVA_I2CM_CR2_OFFSET)
 #endif
 
 /* I2C2 Slave */
 
-#define TIVA_I2CS2_OAR                 (TIVA_I2CS2_BASE + TIVA_I2CS_OAR_OFFSET)
-#define TIVA_I2CS2_CSR                 (TIVA_I2CS2_BASE + TIVA_I2CS_CSR_OFFSET)
-#define TIVA_I2CS2_DR                  (TIVA_I2CS2_BASE + TIVA_I2CS_DR_OFFSET)
-#define TIVA_I2CS2_IMR                 (TIVA_I2CS2_BASE + TIVA_I2CS_IMR_OFFSET)
-#define TIVA_I2CS2_RIS                 (TIVA_I2CS2_BASE + TIVA_I2CS_RIS_OFFSET)
-#define TIVA_I2CS2_MIS                 (TIVA_I2CS2_BASE + TIVA_I2CS_MIS_OFFSET)
-#define TIVA_I2CS2_ICR                 (TIVA_I2CS2_BASE + TIVA_I2CS_ICR_OFFSET)
+#define TIVA_I2CS2_OAR                 (TIVA_I2C2_BASE + TIVA_I2CS_OAR_OFFSET)
+#define TIVA_I2CS2_CSR                 (TIVA_I2C2_BASE + TIVA_I2CS_CSR_OFFSET)
+#define TIVA_I2CS2_DR                  (TIVA_I2C2_BASE + TIVA_I2CS_DR_OFFSET)
+#define TIVA_I2CS2_IMR                 (TIVA_I2C2_BASE + TIVA_I2CS_IMR_OFFSET)
+#define TIVA_I2CS2_RIS                 (TIVA_I2C2_BASE + TIVA_I2CS_RIS_OFFSET)
+#define TIVA_I2CS2_MIS                 (TIVA_I2C2_BASE + TIVA_I2CS_MIS_OFFSET)
+#define TIVA_I2CS2_ICR                 (TIVA_I2C2_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS2_SOAR2             (TIVA_I2CS2_BASE + TIVA_I2CS_SOAR2_OFFSET)
-#  define TIVA_I2CS2_ACKCTL            (TIVA_I2CS2_BASE + TIVA_I2CS_ACKCTL_OFFSET)
+#  define TIVA_I2CS2_SOAR2             (TIVA_I2C2_BASE + TIVA_I2CS_SOAR2_OFFSET)
+#  define TIVA_I2CS2_ACKCTL            (TIVA_I2C2_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C2 Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC2_FIFODATA         (TIVA_I2CSC2_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
-#  define TIVA_I2CSC2_FIFOCTL          (TIVA_I2CSC2_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
-#  define TIVA_I2CSC2_FIFOSTATUS       (TIVA_I2CSC2_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
+#  define TIVA_I2CSC2_FIFODATA         (TIVA_I2C2_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
+#  define TIVA_I2CSC2_FIFOCTL          (TIVA_I2C2_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
+#  define TIVA_I2CSC2_FIFOSTATUS       (TIVA_I2C2_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC2_PP               (TIVA_I2CSC2_BASE + TIVA_I2CSC_PP_OFFSET)
-#  define TIVA_I2CSC2_PC               (TIVA_I2CSC2_BASE + TIVA_I2CSC_PC_OFFSET)
+#  define TIVA_I2CSC2_PP               (TIVA_I2C2_BASE + TIVA_I2CSC_PP_OFFSET)
+#  define TIVA_I2CSC2_PC               (TIVA_I2C2_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
 #endif /* TIVA_NI2C > 2 */
 
@@ -291,59 +291,59 @@
 
 /* I2C3 Master */
 
-#define TIVA_I2CM3_SA                  (TIVA_I2CM3_BASE + TIVA_I2CM_SA_OFFSET)
-#define TIVA_I2CM3_CS                  (TIVA_I2CM3_BASE + TIVA_I2CM_CS_OFFSET)
-#define TIVA_I2CM3_DR                  (TIVA_I2CM3_BASE + TIVA_I2CM_DR_OFFSET)
-#define TIVA_I2CM3_TPR                 (TIVA_I2CM3_BASE + TIVA_I2CM_TPR_OFFSET)
-#define TIVA_I2CM3_IMR                 (TIVA_I2CM3_BASE + TIVA_I2CM_IMR_OFFSET)
-#define TIVA_I2CM3_RIS                 (TIVA_I2CM3_BASE + TIVA_I2CM_RIS_OFFSET)
-#define TIVA_I2CM3_MIS                 (TIVA_I2CM3_BASE + TIVA_I2CM_MIS_OFFSET)
-#define TIVA_I2CM3_ICR                 (TIVA_I2CM3_BASE + TIVA_I2CM_ICR_OFFSET)
-#define TIVA_I2CM3_CR                  (TIVA_I2CM3_BASE + TIVA_I2CM_CR_OFFSET)
+#define TIVA_I2CM3_SA                  (TIVA_I2C3_BASE + TIVA_I2CM_SA_OFFSET)
+#define TIVA_I2CM3_CS                  (TIVA_I2C3_BASE + TIVA_I2CM_CS_OFFSET)
+#define TIVA_I2CM3_DR                  (TIVA_I2C3_BASE + TIVA_I2CM_DR_OFFSET)
+#define TIVA_I2CM3_TPR                 (TIVA_I2C3_BASE + TIVA_I2CM_TPR_OFFSET)
+#define TIVA_I2CM3_IMR                 (TIVA_I2C3_BASE + TIVA_I2CM_IMR_OFFSET)
+#define TIVA_I2CM3_RIS                 (TIVA_I2C3_BASE + TIVA_I2CM_RIS_OFFSET)
+#define TIVA_I2CM3_MIS                 (TIVA_I2C3_BASE + TIVA_I2CM_MIS_OFFSET)
+#define TIVA_I2CM3_ICR                 (TIVA_I2C3_BASE + TIVA_I2CM_ICR_OFFSET)
+#define TIVA_I2CM3_CR                  (TIVA_I2C3_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM3_CLKOCNT           (TIVA_I2CM3_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
-#  define TIVA_I2CM3_BMON              (TIVA_I2CM3_BASE + TIVA_I2CM_BMON_OFFSET)
+#  define TIVA_I2CM3_CLKOCNT           (TIVA_I2C3_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
+#  define TIVA_I2CM3_BMON              (TIVA_I2C3_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM3_BLEN              (TIVA_I2CM3_BASE + TIVA_I2CM_BLEN_OFFSET)
-#  define TIVA_I2CM3_BCNT              (TIVA_I2CM3_BASE + TIVA_I2CM_BCNT_OFFSET)
+#  define TIVA_I2CM3_BLEN              (TIVA_I2C3_BASE + TIVA_I2CM_BLEN_OFFSET)
+#  define TIVA_I2CM3_BCNT              (TIVA_I2C3_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
-#  define TIVA_I2CM3_CR2               (TIVA_I2CM3_BASE + TIVA_I2CM_CR2_OFFSET)
+#  define TIVA_I2CM3_CR2               (TIVA_I2C3_BASE + TIVA_I2CM_CR2_OFFSET)
 #endif
 
 /* I2C3 Slave */
 
-#define TIVA_I2CS3_OAR                 (TIVA_I2CS3_BASE + TIVA_I2CS_OAR_OFFSET)
-#define TIVA_I2CS3_CSR                 (TIVA_I2CS3_BASE + TIVA_I2CS_CSR_OFFSET)
-#define TIVA_I2CS3_DR                  (TIVA_I2CS3_BASE + TIVA_I2CS_DR_OFFSET)
-#define TIVA_I2CS3_IMR                 (TIVA_I2CS3_BASE + TIVA_I2CS_IMR_OFFSET)
-#define TIVA_I2CS3_RIS                 (TIVA_I2CS3_BASE + TIVA_I2CS_RIS_OFFSET)
-#define TIVA_I2CS3_MIS                 (TIVA_I2CS3_BASE + TIVA_I2CS_MIS_OFFSET)
-#define TIVA_I2CS3_ICR                 (TIVA_I2CS3_BASE + TIVA_I2CS_ICR_OFFSET)
+#define TIVA_I2CS3_OAR                 (TIVA_I2C3_BASE + TIVA_I2CS_OAR_OFFSET)
+#define TIVA_I2CS3_CSR                 (TIVA_I2C3_BASE + TIVA_I2CS_CSR_OFFSET)
+#define TIVA_I2CS3_DR                  (TIVA_I2C3_BASE + TIVA_I2CS_DR_OFFSET)
+#define TIVA_I2CS3_IMR                 (TIVA_I2C3_BASE + TIVA_I2CS_IMR_OFFSET)
+#define TIVA_I2CS3_RIS                 (TIVA_I2C3_BASE + TIVA_I2CS_RIS_OFFSET)
+#define TIVA_I2CS3_MIS                 (TIVA_I2C3_BASE + TIVA_I2CS_MIS_OFFSET)
+#define TIVA_I2CS3_ICR                 (TIVA_I2C3_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS3_SOAR2             (TIVA_I2CS3_BASE + TIVA_I2CS_SOAR2_OFFSET)
-#  define TIVA_I2CS3_ACKCTL            (TIVA_I2CS3_BASE + TIVA_I2CS_ACKCTL_OFFSET)
+#  define TIVA_I2CS3_SOAR2             (TIVA_I2C3_BASE + TIVA_I2CS_SOAR2_OFFSET)
+#  define TIVA_I2CS3_ACKCTL            (TIVA_I2C3_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C3 Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC3_FIFODATA         (TIVA_I2CSC3_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
-#  define TIVA_I2CSC3_FIFOCTL          (TIVA_I2CSC3_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
-#  define TIVA_I2CSC3_FIFOSTATUS       (TIVA_I2CSC3_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
+#  define TIVA_I2CSC3_FIFODATA         (TIVA_I2C3_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
+#  define TIVA_I2CSC3_FIFOCTL          (TIVA_I2C3_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
+#  define TIVA_I2CSC3_FIFOSTATUS       (TIVA_I2C3_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC3_PP               (TIVA_I2CSC3_BASE + TIVA_I2CSC_PP_OFFSET)
-#  define TIVA_I2CSC3_PC               (TIVA_I2CSC3_BASE + TIVA_I2CSC_PC_OFFSET)
+#  define TIVA_I2CSC3_PP               (TIVA_I2C3_BASE + TIVA_I2CSC_PP_OFFSET)
+#  define TIVA_I2CSC3_PC               (TIVA_I2C3_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
 #endif /* TIVA_NI2C > 3 */
 
@@ -351,59 +351,59 @@
 
 /* I2C4 Master */
 
-#define TIVA_I2CM4_SA                  (TIVA_I2CM4_BASE + TIVA_I2CM_SA_OFFSET)
-#define TIVA_I2CM4_CS                  (TIVA_I2CM4_BASE + TIVA_I2CM_CS_OFFSET)
-#define TIVA_I2CM4_DR                  (TIVA_I2CM4_BASE + TIVA_I2CM_DR_OFFSET)
-#define TIVA_I2CM4_TPR                 (TIVA_I2CM4_BASE + TIVA_I2CM_TPR_OFFSET)
-#define TIVA_I2CM4_IMR                 (TIVA_I2CM4_BASE + TIVA_I2CM_IMR_OFFSET)
-#define TIVA_I2CM4_RIS                 (TIVA_I2CM4_BASE + TIVA_I2CM_RIS_OFFSET)
-#define TIVA_I2CM4_MIS                 (TIVA_I2CM4_BASE + TIVA_I2CM_MIS_OFFSET)
-#define TIVA_I2CM4_ICR                 (TIVA_I2CM4_BASE + TIVA_I2CM_ICR_OFFSET)
-#define TIVA_I2CM4_CR                  (TIVA_I2CM4_BASE + TIVA_I2CM_CR_OFFSET)
+#define TIVA_I2CM4_SA                  (TIVA_I2C4_BASE + TIVA_I2CM_SA_OFFSET)
+#define TIVA_I2CM4_CS                  (TIVA_I2C4_BASE + TIVA_I2CM_CS_OFFSET)
+#define TIVA_I2CM4_DR                  (TIVA_I2C4_BASE + TIVA_I2CM_DR_OFFSET)
+#define TIVA_I2CM4_TPR                 (TIVA_I2C4_BASE + TIVA_I2CM_TPR_OFFSET)
+#define TIVA_I2CM4_IMR                 (TIVA_I2C4_BASE + TIVA_I2CM_IMR_OFFSET)
+#define TIVA_I2CM4_RIS                 (TIVA_I2C4_BASE + TIVA_I2CM_RIS_OFFSET)
+#define TIVA_I2CM4_MIS                 (TIVA_I2C4_BASE + TIVA_I2CM_MIS_OFFSET)
+#define TIVA_I2CM4_ICR                 (TIVA_I2C4_BASE + TIVA_I2CM_ICR_OFFSET)
+#define TIVA_I2CM4_CR                  (TIVA_I2C4_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM4_CLKOCNT           (TIVA_I2CM4_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
-#  define TIVA_I2CM4_BMON              (TIVA_I2CM4_BASE + TIVA_I2CM_BMON_OFFSET)
+#  define TIVA_I2CM4_CLKOCNT           (TIVA_I2C4_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
+#  define TIVA_I2CM4_BMON              (TIVA_I2C4_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM4_BLEN              (TIVA_I2CM4_BASE + TIVA_I2CM_BLEN_OFFSET)
-#  define TIVA_I2CM4_BCNT              (TIVA_I2CM4_BASE + TIVA_I2CM_BCNT_OFFSET)
+#  define TIVA_I2CM4_BLEN              (TIVA_I2C4_BASE + TIVA_I2CM_BLEN_OFFSET)
+#  define TIVA_I2CM4_BCNT              (TIVA_I2C4_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
-#  define TIVA_I2CM4_CR2               (TIVA_I2CM4_BASE + TIVA_I2CM_CR2_OFFSET)
+#  define TIVA_I2CM4_CR2               (TIVA_I2C4_BASE + TIVA_I2CM_CR2_OFFSET)
 #endif
 
 /* I2C4 Slave */
 
-#define TIVA_I2CS4_OAR                 (TIVA_I2CS4_BASE + TIVA_I2CS_OAR_OFFSET)
-#define TIVA_I2CS4_CSR                 (TIVA_I2CS4_BASE + TIVA_I2CS_CSR_OFFSET)
-#define TIVA_I2CS4_DR                  (TIVA_I2CS4_BASE + TIVA_I2CS_DR_OFFSET)
-#define TIVA_I2CS4_IMR                 (TIVA_I2CS4_BASE + TIVA_I2CS_IMR_OFFSET)
-#define TIVA_I2CS4_RIS                 (TIVA_I2CS4_BASE + TIVA_I2CS_RIS_OFFSET)
-#define TIVA_I2CS4_MIS                 (TIVA_I2CS4_BASE + TIVA_I2CS_MIS_OFFSET)
-#define TIVA_I2CS4_ICR                 (TIVA_I2CS4_BASE + TIVA_I2CS_ICR_OFFSET)
+#define TIVA_I2CS4_OAR                 (TIVA_I2C4_BASE + TIVA_I2CS_OAR_OFFSET)
+#define TIVA_I2CS4_CSR                 (TIVA_I2C4_BASE + TIVA_I2CS_CSR_OFFSET)
+#define TIVA_I2CS4_DR                  (TIVA_I2C4_BASE + TIVA_I2CS_DR_OFFSET)
+#define TIVA_I2CS4_IMR                 (TIVA_I2C4_BASE + TIVA_I2CS_IMR_OFFSET)
+#define TIVA_I2CS4_RIS                 (TIVA_I2C4_BASE + TIVA_I2CS_RIS_OFFSET)
+#define TIVA_I2CS4_MIS                 (TIVA_I2C4_BASE + TIVA_I2CS_MIS_OFFSET)
+#define TIVA_I2CS4_ICR                 (TIVA_I2C4_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS4_SOAR2             (TIVA_I2CS4_BASE + TIVA_I2CS_SOAR2_OFFSET)
-#  define TIVA_I2CS4_ACKCTL            (TIVA_I2CS4_BASE + TIVA_I2CS_ACKCTL_OFFSET)
+#  define TIVA_I2CS4_SOAR2             (TIVA_I2C4_BASE + TIVA_I2CS_SOAR2_OFFSET)
+#  define TIVA_I2CS4_ACKCTL            (TIVA_I2C4_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C4 Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC4_FIFODATA         (TIVA_I2CSC4_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
-#  define TIVA_I2CSC4_FIFOCTL          (TIVA_I2CSC4_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
-#  define TIVA_I2CSC4_FIFOSTATUS       (TIVA_I2CSC4_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
+#  define TIVA_I2CSC4_FIFODATA         (TIVA_I2C4_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
+#  define TIVA_I2CSC4_FIFOCTL          (TIVA_I2C4_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
+#  define TIVA_I2CSC4_FIFOSTATUS       (TIVA_I2C4_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC4_PP               (TIVA_I2CSC4_BASE + TIVA_I2CSC_PP_OFFSET)
-#  define TIVA_I2CSC4_PC               (TIVA_I2CSC4_BASE + TIVA_I2CSC_PC_OFFSET)
+#  define TIVA_I2CSC4_PP               (TIVA_I2C4_BASE + TIVA_I2CSC_PP_OFFSET)
+#  define TIVA_I2CSC4_PC               (TIVA_I2C4_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
 #endif /* TIVA_NI2C > 4 */
 
@@ -411,59 +411,59 @@
 
 /* I2C5 Master */
 
-#define TIVA_I2CM5_SA                  (TIVA_I2CM5_BASE + TIVA_I2CM_SA_OFFSET)
-#define TIVA_I2CM5_CS                  (TIVA_I2CM5_BASE + TIVA_I2CM_CS_OFFSET)
-#define TIVA_I2CM5_DR                  (TIVA_I2CM5_BASE + TIVA_I2CM_DR_OFFSET)
-#define TIVA_I2CM5_TPR                 (TIVA_I2CM5_BASE + TIVA_I2CM_TPR_OFFSET)
-#define TIVA_I2CM5_IMR                 (TIVA_I2CM5_BASE + TIVA_I2CM_IMR_OFFSET)
-#define TIVA_I2CM5_RIS                 (TIVA_I2CM5_BASE + TIVA_I2CM_RIS_OFFSET)
-#define TIVA_I2CM5_MIS                 (TIVA_I2CM5_BASE + TIVA_I2CM_MIS_OFFSET)
-#define TIVA_I2CM5_ICR                 (TIVA_I2CM5_BASE + TIVA_I2CM_ICR_OFFSET)
-#define TIVA_I2CM5_CR                  (TIVA_I2CM5_BASE + TIVA_I2CM_CR_OFFSET)
+#define TIVA_I2CM5_SA                  (TIVA_I2C5_BASE + TIVA_I2CM_SA_OFFSET)
+#define TIVA_I2CM5_CS                  (TIVA_I2C5_BASE + TIVA_I2CM_CS_OFFSET)
+#define TIVA_I2CM5_DR                  (TIVA_I2C5_BASE + TIVA_I2CM_DR_OFFSET)
+#define TIVA_I2CM5_TPR                 (TIVA_I2C5_BASE + TIVA_I2CM_TPR_OFFSET)
+#define TIVA_I2CM5_IMR                 (TIVA_I2C5_BASE + TIVA_I2CM_IMR_OFFSET)
+#define TIVA_I2CM5_RIS                 (TIVA_I2C5_BASE + TIVA_I2CM_RIS_OFFSET)
+#define TIVA_I2CM5_MIS                 (TIVA_I2C5_BASE + TIVA_I2CM_MIS_OFFSET)
+#define TIVA_I2CM5_ICR                 (TIVA_I2C5_BASE + TIVA_I2CM_ICR_OFFSET)
+#define TIVA_I2CM5_CR                  (TIVA_I2C5_BASE + TIVA_I2CM_CR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM5_CLKOCNT           (TIVA_I2CM5_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
-#  define TIVA_I2CM5_BMON              (TIVA_I2CM5_BASE + TIVA_I2CM_BMON_OFFSET)
+#  define TIVA_I2CM5_CLKOCNT           (TIVA_I2C5_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
+#  define TIVA_I2CM5_BMON              (TIVA_I2C5_BASE + TIVA_I2CM_BMON_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CM5_BLEN              (TIVA_I2CM5_BASE + TIVA_I2CM_BLEN_OFFSET)
-#  define TIVA_I2CM5_BCNT              (TIVA_I2CM5_BASE + TIVA_I2CM_BCNT_OFFSET)
+#  define TIVA_I2CM5_BLEN              (TIVA_I2C5_BASE + TIVA_I2CM_BLEN_OFFSET)
+#  define TIVA_I2CM5_BCNT              (TIVA_I2C5_BASE + TIVA_I2CM_BCNT_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
-#  define TIVA_I2CM5_CR2               (TIVA_I2CM5_BASE + TIVA_I2CM_CR2_OFFSET)
+#  define TIVA_I2CM5_CR2               (TIVA_I2C5_BASE + TIVA_I2CM_CR2_OFFSET)
 #endif
 
 /* I2C5 Slave */
 
-#define TIVA_I2CS5_OAR                 (TIVA_I2CS5_BASE + TIVA_I2CS_OAR_OFFSET)
-#define TIVA_I2CS5_CSR                 (TIVA_I2CS5_BASE + TIVA_I2CS_CSR_OFFSET)
-#define TIVA_I2CS5_DR                  (TIVA_I2CS5_BASE + TIVA_I2CS_DR_OFFSET)
-#define TIVA_I2CS5_IMR                 (TIVA_I2CS5_BASE + TIVA_I2CS_IMR_OFFSET)
-#define TIVA_I2CS5_RIS                 (TIVA_I2CS5_BASE + TIVA_I2CS_RIS_OFFSET)
-#define TIVA_I2CS5_MIS                 (TIVA_I2CS5_BASE + TIVA_I2CS_MIS_OFFSET)
-#define TIVA_I2CS5_ICR                 (TIVA_I2CS5_BASE + TIVA_I2CS_ICR_OFFSET)
+#define TIVA_I2CS5_OAR                 (TIVA_I2C5_BASE + TIVA_I2CS_OAR_OFFSET)
+#define TIVA_I2CS5_CSR                 (TIVA_I2C5_BASE + TIVA_I2CS_CSR_OFFSET)
+#define TIVA_I2CS5_DR                  (TIVA_I2C5_BASE + TIVA_I2CS_DR_OFFSET)
+#define TIVA_I2CS5_IMR                 (TIVA_I2C5_BASE + TIVA_I2CS_IMR_OFFSET)
+#define TIVA_I2CS5_RIS                 (TIVA_I2C5_BASE + TIVA_I2CS_RIS_OFFSET)
+#define TIVA_I2CS5_MIS                 (TIVA_I2C5_BASE + TIVA_I2CS_MIS_OFFSET)
+#define TIVA_I2CS5_ICR                 (TIVA_I2C5_BASE + TIVA_I2CS_ICR_OFFSET)
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CS5_SOAR2             (TIVA_I2CS5_BASE + TIVA_I2CS_SOAR2_OFFSET)
-#  define TIVA_I2CS5_ACKCTL            (TIVA_I2CS5_BASE + TIVA_I2CS_ACKCTL_OFFSET)
+#  define TIVA_I2CS5_SOAR2             (TIVA_I2C5_BASE + TIVA_I2CS_SOAR2_OFFSET)
+#  define TIVA_I2CS5_ACKCTL            (TIVA_I2C5_BASE + TIVA_I2CS_ACKCTL_OFFSET)
 #endif
 
 /* I2C Status and control */
 
 #if defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC5_FIFODATA         (TIVA_I2CSC5_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
-#  define TIVA_I2CSC5_FIFOCTL          (TIVA_I2CSC5_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
-#  define TIVA_I2CSC5_FIFOSTATUS       (TIVA_I2CSC5_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
+#  define TIVA_I2CSC5_FIFODATA         (TIVA_I2C5_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
+#  define TIVA_I2CSC5_FIFOCTL          (TIVA_I2C5_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
+#  define TIVA_I2CSC5_FIFOSTATUS       (TIVA_I2C5_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
 #endif
 
 #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
     defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT)
-#  define TIVA_I2CSC5_PP               (TIVA_I2CSC5_BASE + TIVA_I2CSC_PP_OFFSET)
-#  define TIVA_I2CSC5_PC               (TIVA_I2CSC5_BASE + TIVA_I2CSC_PC_OFFSET)
+#  define TIVA_I2CSC5_PP               (TIVA_I2C5_BASE + TIVA_I2CSC_PP_OFFSET)
+#  define TIVA_I2CSC5_PC               (TIVA_I2C5_BASE + TIVA_I2CSC_PC_OFFSET)
 #endif
 #endif /* TIVA_NI2C > 5 */
 
diff --git a/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h b/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h
index 24f25e2f3..06f99ab9d 100644
--- a/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h
+++ b/nuttx/arch/arm/src/tiva/chip/tm4c_memorymap.h
@@ -121,18 +121,10 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fbf: I2C Slave 0 */
-#  define TIVA_I2CSC0_BASE    (TIVA_PERIPH_BASE + 0x20f00)  /* -0x20fff: I2C Status and Control 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fbf: I2C Slave 1 */
-#  define TIVA_I2CSC1_BASE    (TIVA_PERIPH_BASE + 0x21f00)  /* -0x21fff: I2C Status and Control 1 */
-#  define TIVA_I2CM2_BASE     (TIVA_PERIPH_BASE + 0x22000)  /* -0x227ff: I2C Master 2 */
-#  define TIVA_I2CS2_BASE     (TIVA_PERIPH_BASE + 0x22800)  /* -0x22fbf: I2C Slave 2 */
-#  define TIVA_I2CSC2_BASE    (TIVA_PERIPH_BASE + 0x22f00)  /* -0x22fff: I2C Status and Control 2 */
-#  define TIVA_I2CM3_BASE     (TIVA_PERIPH_BASE + 0x23000)  /* -0x237ff: I2C Master 3 */
-#  define TIVA_I2CS3_BASE     (TIVA_PERIPH_BASE + 0x23800)  /* -0x23fbf: I2C Slave 3 */
-#  define TIVA_I2CSC3_BASE    (TIVA_PERIPH_BASE + 0x23f00)  /* -0x23fff: I2C Status and Control 3 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x21fff: I2C1 */
+#  define TIVA_I2C2_BASE      (TIVA_PERIPH_BASE + 0x22000)  /* -0x22fff: I2C2 */
+#  define TIVA_I2C3_BASE      (TIVA_PERIPH_BASE + 0x23000)  /* -0x23fff: I2C3 */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
 #  define TIVA_GPIOG_BASE     (TIVA_PERIPH_BASE + 0x26000)  /* -0x26fff: GPIO Port G */
@@ -181,12 +173,8 @@
                                                             /* -0xaefff: Reserved */
 #  define TIVA_EEPROM_BASE    (TIVA_PERIPH_BASE + 0xaf000)  /* -0xaffff: EEPROM and Key Locker */
                                                             /* -0xbffff: Reserved */
-#  define TIVA_I2CM4_BASE     (TIVA_PERIPH_BASE + 0xc0000)  /* -0x207ff: I2C Master 4 */
-#  define TIVA_I2CS4_BASE     (TIVA_PERIPH_BASE + 0xc0800)  /* -0x20fbf: I2C Slave 4 */
-#  define TIVA_I2CSC4_BASE    (TIVA_PERIPH_BASE + 0xc0f00)  /* -0x20fff: I2C Status and Control 4 */
-#  define TIVA_I2CM5_BASE     (TIVA_PERIPH_BASE + 0xc1000)  /* -0x207ff: I2C Master 5 */
-#  define TIVA_I2CS5_BASE     (TIVA_PERIPH_BASE + 0xc1800)  /* -0x20fbf: I2C Slave 5 */
-#  define TIVA_I2CSC5_BASE    (TIVA_PERIPH_BASE + 0xc1f00)  /* -0x20fff: I2C Status and Control 5 */
+#  define TIVA_I2C4_BASE      (TIVA_PERIPH_BASE + 0xc0000)  /* -0x20fff: I2C4 */
+#  define TIVA_I2C5_BASE      (TIVA_PERIPH_BASE + 0xc1000)  /* -0x21fff: I2C5 */
                                                             /* -0xf8fff: Reserved */
 #  define TIVA_SYSEXC_BASE    (TIVA_PERIPH_BASE + 0xf9000)  /* -0xf9fff: System Exception Control */
                                                             /* -0xfbfff: Reserved */
@@ -219,18 +207,10 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fbf: I2C Slave 0 */
-#  define TIVA_I2CSC0_BASE    (TIVA_PERIPH_BASE + 0x20f00)  /* -0x20fff: I2C Status and Control 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fbf: I2C Slave 1 */
-#  define TIVA_I2CSC1_BASE    (TIVA_PERIPH_BASE + 0x21f00)  /* -0x21fff: I2C Status and Control 1 */
-#  define TIVA_I2CM2_BASE     (TIVA_PERIPH_BASE + 0x22000)  /* -0x227ff: I2C Master 2 */
-#  define TIVA_I2CS2_BASE     (TIVA_PERIPH_BASE + 0x22800)  /* -0x22fbf: I2C Slave 2 */
-#  define TIVA_I2CSC2_BASE    (TIVA_PERIPH_BASE + 0x22f00)  /* -0x22fff: I2C Status and Control 2 */
-#  define TIVA_I2CM3_BASE     (TIVA_PERIPH_BASE + 0x23000)  /* -0x237ff: I2C Master 3 */
-#  define TIVA_I2CS3_BASE     (TIVA_PERIPH_BASE + 0x23800)  /* -0x23fbf: I2C Slave 3 */
-#  define TIVA_I2CSC3_BASE    (TIVA_PERIPH_BASE + 0x23f00)  /* -0x23fff: I2C Status and Control 3 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x21fff: I2C1 */
+#  define TIVA_I2C2_BASE      (TIVA_PERIPH_BASE + 0x22000)  /* -0x22fff: I2C2 */
+#  define TIVA_I2C3_BASE      (TIVA_PERIPH_BASE + 0x23000)  /* -0x23fff: I2C3 */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
 #  define TIVA_PWM0_BASE      (TIVA_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM 0 */
@@ -297,18 +277,10 @@
                                                            /* -0x1ffff: Reserved */
 /* Peripheral Base Addresses */
 
-#  define TIVA_I2CM0_BASE     (TIVA_PERIPH_BASE + 0x20000)  /* -0x207ff: I2C Master 0 */
-#  define TIVA_I2CS0_BASE     (TIVA_PERIPH_BASE + 0x20800)  /* -0x20fbf: I2C Slave 0 */
-#  define TIVA_I2CSC0_BASE    (TIVA_PERIPH_BASE + 0x20f00)  /* -0x20fff: I2C Status and Control 0 */
-#  define TIVA_I2CM1_BASE     (TIVA_PERIPH_BASE + 0x21000)  /* -0x217ff: I2C Master 1 */
-#  define TIVA_I2CS1_BASE     (TIVA_PERIPH_BASE + 0x21800)  /* -0x21fbf: I2C Slave 1 */
-#  define TIVA_I2CSC1_BASE    (TIVA_PERIPH_BASE + 0x21f00)  /* -0x21fff: I2C Status and Control 1 */
-#  define TIVA_I2CM2_BASE     (TIVA_PERIPH_BASE + 0x22000)  /* -0x227ff: I2C Master 2 */
-#  define TIVA_I2CS2_BASE     (TIVA_PERIPH_BASE + 0x22800)  /* -0x22fbf: I2C Slave 2 */
-#  define TIVA_I2CSC2_BASE    (TIVA_PERIPH_BASE + 0x22f00)  /* -0x22fff: I2C Status and Control 2 */
-#  define TIVA_I2CM3_BASE     (TIVA_PERIPH_BASE + 0x23000)  /* -0x237ff: I2C Master 3 */
-#  define TIVA_I2CS3_BASE     (TIVA_PERIPH_BASE + 0x23800)  /* -0x23fbf: I2C Slave 3 */
-#  define TIVA_I2CSC3_BASE    (TIVA_PERIPH_BASE + 0x23f00)  /* -0x23fff: I2C Status and Control 3 */
+#  define TIVA_I2C0_BASE      (TIVA_PERIPH_BASE + 0x20000)  /* -0x20fff: I2C0 */
+#  define TIVA_I2C1_BASE      (TIVA_PERIPH_BASE + 0x21000)  /* -0x21fff: I2C1 */
+#  define TIVA_I2C2_BASE      (TIVA_PERIPH_BASE + 0x22000)  /* -0x22fff: I2C2 */
+#  define TIVA_I2C3_BASE      (TIVA_PERIPH_BASE + 0x23000)  /* -0x23fff: I2C3 */
 #  define TIVA_GPIOE_BASE     (TIVA_PERIPH_BASE + 0x24000)  /* -0x24fff: GPIO Port E */
 #  define TIVA_GPIOF_BASE     (TIVA_PERIPH_BASE + 0x25000)  /* -0x25fff: GPIO Port F */
 #  define TIVA_PWM0_BASE      (TIVA_PERIPH_BASE + 0x28000)  /* -0x28fff: PWM 0 */