diff options
| -rw-r--r-- | nuttx/arch/arm/src/imx/chip.h | 54 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/imx/imx_memorymap.h | 195 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/imx/imx_uart.h | 219 |
3 files changed, 468 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/imx/chip.h b/nuttx/arch/arm/src/imx/chip.h new file mode 100644 index 000000000..10d00fc63 --- /dev/null +++ b/nuttx/arch/arm/src/imx/chip.h @@ -0,0 +1,54 @@ +/************************************************************************************ + * arch/arm/src/imx/chip.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_CHIP_H +#define __ARCH_ARM_IMX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "imx_memorymap.h" +#include "imx_uart.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_CHIP_H */ diff --git a/nuttx/arch/arm/src/imx/imx_memorymap.h b/nuttx/arch/arm/src/imx/imx_memorymap.h new file mode 100644 index 000000000..403906eda --- /dev/null +++ b/nuttx/arch/arm/src/imx/imx_memorymap.h @@ -0,0 +1,195 @@ +/************************************************************************************ + * arch/arm/src/imx/imx_memorymap.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_MEMORYMAP_H +#define __ARCH_ARM_IMX_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Physical Memory Map **************************************************************/ + + /* -0x000fffff Double Map Image 1Mb */ + /* -0x001fffff Bootstrap ROM 1Mb */ +#define IMX_PERIPHERALS_PSECTION 0x00200000 /* -0x002fffff Peripherals 1Mb */ +#define IMX_SDRAM0_PSECTION 0x08000000 /* -0x08ffff00 SDRAM0 16Mb */ +#define IMX_SDRAM1_PSECTION 0x0c000000 /* -0x0cffff00 SDRAM1 16Mb */ +#define IMX_FLASH_PSECTION 0x10000000 /* -0x12000000 FLASH 32Mb */ + +/* Sizes of Address Sections ********************************************************/ + +#define IMX_PERIPHERALS_NSECTIONS 1 /* 1Mb 1 section */ +#define IMX_SDRAM0_NSECTIONS 16 /* 16Mb 16 sections */ +#define IMX_SDRAM1_NSECTIONS 16 /* 16Mb 16 sections */ +#define IMX_FLASH_NSECTIONS 32 /* 32Mb 32 sections */ + +/* Virtual Memory Map ***************************************************************/ + +#define IMX_SDRAM_VSECTION 0x00000000 /* -0x01ffff00 32Mb */ +#define IMX_FLASH_VSECTION 0x80000000 /* -0x81ffffff 32Mb */ +#define IMX_PERIPHERALS_VSECTION 0xe0000000 /* -0xe00fffff 1Mb */ + +/* Peripheral Register Offsets ******************************************************/ + +#define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */ +#define IMX_WDOG_OFFSET 0x00001000 /* -0x00001fff WatchDog 4Kb */ +#define IMX_TIMER1_OFFSET 0x00002000 /* -0x00002fff Timer1 4Kb */ +#define IMX_TIMER2_OFFSET 0x00003000 /* -0x00003fff Timer2 4Kb */ +#define IMX_RTC_OFFSET 0x00004000 /* -0x00004fff RTC 4Kb */ +#define IMX_LCDC_OFFSET 0x00005000 /* -0x00005fff LCD 4Kb */ +#define IMX_LCDC_COLORMAP 0x00005800 +#define IMX_UART1_OFFSET 0x00006000 /* -0x00006fff UART1 4Kb */ +#define IMX_UART2_OFFSET 0x00007000 /* -0x00007fff UART2 4Kb */ +#define IMX_PWM1_OFFSET 0x00008000 /* -0x00008fff PWM 4Kb */ +#define IMX_DMA_OFFSET 0x00009000 /* -0x00009fff DMA 4Kb */ +#define IMX_UART3_OFFSET 0x0000a000 /* -0x0000afff UART3 4Kb */ + /* -0x0000ffff Reserved 20Kb */ +#define IMX_AIPI2_OFFSET 0x00010000 /* -0x00010fff AIPI2 4Kb */ +#define IMX_SIM_OFFSET 0x00011000 /* -0x00011fff SIM 4Kb */ +#define IMX_USBD_OFFSET 0x00012000 /* -0x00012fff USBD 4Kb */ +#define IMX_CSPI1_OFFSET 0x00013000 /* -0x00013fff CSPI1 4Kb */ +#define IMX_MMC_OFFSET 0x00014000 /* -0x00014fff MMC 4Kb */ +#define IMX_ASP_OFFSET 0x00015000 /* -0x00015fff ASP 4Kb */ +#define IMX_BTA_OFFSET 0x00016000 /* -0x00016fff BTA 4Kb */ +#define IMX_I2C_OFFSET 0x00017000 /* -0x00017fff I2C 4Kb */ +#define IMX_SSI_OFFSET 0x00018000 /* -0x00018fff SSI 4Kb */ +#define IMX_CSPI2_OFFSET 0x00019000 /* -0x00019fff CSPI2 4Kb */ +#define IMX_MSHC_OFFSET 0x0001a000 /* -0x0001afff Memory Stick 4Kb */ +#define IMX_CRM_OFFSET 0x0001b000 /* -0x0001bfff CRM 4Kb */ +#define IMX_PLL_OFFSET 0x0001b000 +#define IMX_SC_OFFSET 0x0001b800 +#define IMX_GPIO_OFFSET 0x0001c000 /* -0x0001cfff GPIO 4Kb */ +#define IMX_PTA_OFFSET 0x0001c000 +#define IMX_PTB_OFFSET 0x0001c100 +#define IMX_PTC_OFFSET 0x0001c200 +#define IMX_PTD_OFFSET 0x0001c300 + /* -0x0001ffff Reserved 12Kb */ +#define IMX_EIM_OFFSET 0x00020000 /* -0x00020fff WEIM 4Kb */ +#define IMX_SDRAMC_OFFSET 0x00021000 /* -0x00021fff SDRAMC 4Kb */ +#define IMX_DSPA_OFFSET 0x00022000 /* -0x00022fff DSPA 4Kb */ +#define IMX_AITC_OFFSET 0x00023000 /* -0x00023fff AITC 4Kb */ +#define IMX_CSI_OFFSET 0x00024000 /* -0x00024fff CSI 4Kb */ + /* -0x000fffff Reserved 876Kb */ + +/* Peripheral Register Offsets ******************************************************/ + +#define IMX_AIPI1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AIPI1_OFFSET) +#define IMX_WDOG_VBASE (IMX_PERIPHERALS_VSECTION + IMX_WDOG_OFFSET) +#define IMX_TIMER1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_TIMER1_OFFSET) +#define IMX_TIMER2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_TIMER2_OFFSET) +#define IMX_RTC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_RTC_OFFSET) +#define IMX_LCDC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_LCDC_OFFSET) +#define IMX_LCDC_COLORMAP_VBASE (IMX_PERIPHERALS_VSECTION + IMX_LCDC_COLORMAP) +#define IMX_UART1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_UART1_OFFSET) +#define IMX_UART2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_UART2_OFFSET) +#define IMX_PWM1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PWM1_OFFSET) +#define IMX_DMA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_DMA_OFFSET) +#define IMX_UART3_VBASE (IMX_PERIPHERALS_VSECTION + IMX_UART3_OFFSET) +#define IMX_AIP2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AIPI2_OFFSET) +#define IMX_SIM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SIM_OFFSET) +#define IMX_USBD_VBASE (IMX_PERIPHERALS_VSECTION + IMX_USBD_OFFSET) +#define IMX_CSPI1_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSPI1_OFFSET) +#define IMX_MMC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_MMC_OFFSET) +#define IMX_ASP_VBASE (IMX_PERIPHERALS_VSECTION + IMX_ASP_OFFSET) +#define IMX_BTA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_BTA_OFFSET) +#define IMX_I2C_VBASE (IMX_PERIPHERALS_VSECTION + IMX_I2C_OFFSET) +#define IMX_SSI_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SSI_OFFSET) +#define IMX_CSPI2_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSPI2_OFFSET) +#define IMX_MSHC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_MSHC_OFFSET) +#define IMX_CRM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CRM_OFFSET) +#define IMX_PLL_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PLL_OFFSET) +#define IMX_SC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SC_OFFSET) +#define IMX_GPIO_VBASE (IMX_PERIPHERALS_VSECTION + IMX_GPIO_OFFSET) +#define IMX_PTA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTA_OFFSET) +#define IMX_PTB_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTB_OFFSET) +#define IMX_PTC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTC_OFFSET) +#define IMX_PTD_VBASE (IMX_PERIPHERALS_VSECTION + IMX_PTD_OFFSET) +#define IMX_EIM_VBASE (IMX_PERIPHERALS_VSECTION + IMX_EIM_OFFSET) +#define IMX_SDRAMC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_SDRAMC_OFFSET) +#define IMX_DSPA_VBASE (IMX_PERIPHERALS_VSECTION + IMX_DSPA_OFFSET) +#define IMX_AITC_VBASE (IMX_PERIPHERALS_VSECTION + IMX_AITC_OFFSET) +#define IMX_CSI_VBASE (IMX_PERIPHERALS_VSECTION + IMX_CSI_OFFSET) + +/* Memory Mapping Info **************************************************************/ + +/* The NuttX entry point starts at an offset from the virtual beginning of DRAM. + * This offset reserves space for the MMU page cache. + */ + +#define NUTTX_START_VBASE (IMX_SDRAM_VBASE+PGTABLE_SIZE) + +/* Section MMU Flags */ + +#define IMX_FLASH_MMUFLAGS MMU_IOFLAGS +#define IMX_PERIPHERALS_MMUFLAGS MMU_IOFLAGS + +/* 16Kb of memory is reserved at the beginning of SDRAM to hold the + * page table for the virtual mappings. A portion of this table is + * not accessible in the virtual address space (for normal operation). + * We will reuse this memory for coarse page tables as follows: + */ + +#define PGTABLE_BASE_PBASE IMX_SDRAM0_PSECTION +#define PGTABLE_SDRAM_PBASE PGTABLE_BASE_PBASE +#define PGTABLE_COARSE_BASE_PBASE (PGTABLE_BASE_PBASE+0x00000800) +#define PGTABLE_COARSE_END_PBASE (PGTABLE_BASE_PBASE+0x00003000) +#define PTTABLE_PERIPHERALS_PBASE (PGTABLE_BASE_PBASE+0x00003000) +#define PGTABLE_END_PBASE (PGTABLE_BASE_PBASE+0x00004000) + +#define PGTABLE_BASE_VBASE IMX_SDRAM_VSECTION +#define PGTABLE_SDRAM_VBASE PGTABLE_BASE_VBASE +#define PGTABLE_COARSE_BASE_VBASE (PGTABLE_BASE_VBASE+0x00000800) +#define PGTABLE_COARSE_END_VBASE (PGTABLE_BASE_VBASE+0x00003000) +#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_BASE_VBASE+0x00003000) +#define PGTABLE_END_VBASE (PGTABLE_BASE_VBASE+0x00004000) + +#define PGTBALE_COARSE_TABLE_SIZE (4*256) +#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_END_VBASE-PGTABLE_COARSE_BASE_VBASE) +#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC) + +/* This is the base address of the interrupt vectors on the ARM926 */ + +#define VECTOR_BASE IMX_VECTOR_VBASE + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/imx/imx_uart.h b/nuttx/arch/arm/src/imx/imx_uart.h new file mode 100644 index 000000000..d050e5ee7 --- /dev/null +++ b/nuttx/arch/arm/src/imx/imx_uart.h @@ -0,0 +1,219 @@ +/************************************************************************************ + * arch/arm/src/imx/imx_uart.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_UART_H +#define __ARCH_ARM_IMX_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* UART Register Offsets ************************************************************/ + +#define UART_RXD0 0x0000 /* UART receiver register 0 */ +#define UART_RXD1 0x0004 /* UART receiver register 1 */ +#define UART_RXD2 0x0008 /* UART receiver register 2 */ +#define UART_RXD3 0x000c /* UART receiver register 3 */ +#define UART_TXD0 0x0040 /* UART receiver register 0 */ +#define UART_TXD1 0x0044 /* UART receiver register 1 */ +#define UART_TXD2 0x0048 /* UART receiver register 2 */ +#define UART_TXD3 0x004c /* UART receiver register 3 */ +#define UART_UCR1 0x0080 /* UART control register 1 */ +#define UART_UCR2 0x0084 /* UART control register 2 */ +#define UART_UCR3 0x0088 /* UART control register 3 */ +#define UART_UCR4 0x008c /* UART control register 4 */ +#define UART_UFCR 0x0090 /* UART FIFO control register */ +#define UART_USR1 0x0094 /* UART status register 1 */ +#define UART_USR2 0x0098 /* UART status register 2 */ +#define UART_UESC 0x009c /* UART escape character register */ +#define UART_UTIM 0x00a0 /* UART escape timer register */ +#define UART_UBIR 0x00a4 /* UART BRM incremental register */ +#define UART_UBMR 0x00a8 /* UART BRM modulator register */ +#define UART_UBRC 0x00ac /* UART baud rate counter register */ +#define UART_BIPR1 0x00b0 /* UART BRM incremental preset register 1 */ +#define UART_BIPR2 0x00b4 /* UART BRM incremental preset register 2 */ +#define UART_BIPR3 0x00b8 /* UART BRM incremental preset register 3 */ +#define UART_BIPR4 0x00bc /* UART BRM incremental preset register 4 */ +#define UART_BMPR1 0x00c0 /* UART BRM modulator preset register 1 */ +#define UART_BMPR2 0x00c4 /* UART BRM modulator preset register 2 */ +#define UART_BMPR3 0x00c8 /* UART BRM modulator preset register 3 */ +#define UART_BMPR4 0x00cc /* UART BRM modulator preset register 4 */ +#define UART_UTS 0x00d0 /* UART test register */ + +/* UART Register Bit Definitions ****************************************************/ + +/* UART Receiver Register */ + +#define UART_RXD_DATA_SHIFT 0 /* Bits 0-7: Received Data */ +#define UART_RXD_DATA_MASK (0x7f << UART_RXD_DATA_SHIFT) +#define UART_RXD_PRERR (1 << 10) /* Bit 10: Parity Error */ +#define UART_RXD_BRK (1 << 11) /* Bit 11: Break Detect */ +#define UART_RXD_FRMERR (1 << 12) /* Bit 12: Frame Error */ +#define UART_RXD_OVRRUN (1 << 13) /* Bit 13: Receiver Overrun */ +#define UART_RXD_ERR (1 << 14) /* Bit 14: Error Detect */ +#define UART_RXD_CHARRDY (1 << 15) /* Bit 15: Character Ready */ + +/* UART Transmitter Register */ + +#define UART_TXDATA_SHIFT 0 /* Bits 0-7: Transmit Data */ +#define UART_TXDATA_MASK (0xff << UART_UCR4_TXDATA_SHIFT) + +/* UART Control Register 1 */ + +#define UART_UCR1_UARTEN (1 << 0) /* Bit 0: Enable/disable uart */ +#define UART_UCR1_DOZE (1 << 1) /* Bit 1: UART Doze enable */ +#define UART_UCR1_UARTCLEN (1 << 2) /* Bit 2: UART clock enable */ +#define UART_UCR1_TDMAEN (1 << 3) /* Bit 3: Transmitter ready data enable */ +#define UART_UCR1_SNDBRK (1 << 4) /* Bit 4: Send BREAK */ +#define UART_UCR1_RTSDEN (1 << 5) /* Bit 5: RTS Delta interrupt enable */ +#define UART_UCR1_TXEMPTYEN (1 << 6) /* Bit 6: Transmitter empty interrupt enable */ +#define UART_UCR1_IREN (1 << 7) /* Bit 7: Infrared Interface enable */ +#define UART_UCR1_RDMAEN (1 << 8) /* Bit 8: Receive ready DMA enable */ +#define UART_UCR1_RRDYEN (1 << 9) /* Bit 9: Receiver ready interrupt enable */ +#define UART_UCR1_ICD_SHIFT 10 /* Bit 10-11: Idle condition detect */ +#define UART_UCR1_ICD_MASK (0x03 << UART_UCR1_ICD_SHIFT) +#define UART_UCR1_IDEN (1 << 12) /* Bit 12: Idle condition detected interrupt enable */ +#define UART_UCR1_TRDYEN (1 << 13) /* Bit 13: Transmitter ready interrupt enable */ +#define UART_UCR1_ADBR (1 << 14) /* Bit 14: Automatic detection of baud rate */ +#define UART_UCR1_ADEN (1 << 15) /* Bit 15: Automatic baud rate detection interrupt enable */ + +/* UART Control Register 2 */ + +#define UART_UCR2_SRST (1 << 0) /* Bit 0: Software reset */ +#define UART_UCR2_RXEN (1 << 1) /* Bit 1: Receiver enable */ +#define UART_UCR2_TXEN (1 << 2) /* Bit 2: Transmitter enable */ +#define UART_UCR2_RTSEN (1 << 4) /* Bit 4: RTS interrupt enable/disable */ +#define UART_UCR2_WS (1 << 5) /* Bit 5: Word size */ +#define UART_UCR2_STPB (1 << 6) /* Bit 6: Controls number of stop bits */ +#define UART_UCR2_PROE (1 << 7) /* Bit 7: Parity Odd/Even */ +#define UART_UCR2_PREN (1 << 8) /* Bit 8: Parity enable */ +#define UART_UCR2_RTEC_SHIFT 9 /* Bit 9-10: Request to send edge control */ +#define UART_UCR2_RTEC_MASK (0x03 << UART_UCR2_RTEC_SHIFT) +#define UART_UCR2_ESCEN (1 << 11) /* Bit 11: Escape enable */ +#define UART_UCR2_CTS (1 << 12) /* Bit 12: Clear To Send pin */ +#define UART_UCR2_CTSC (1 << 13) /* Bit 13: CTS Pin control */ +#define UART_UCR2_IRTS (1 << 14) /* Bit 14: Ignore RTS Pin */ +#define UART_UCR2_ESCI (1 << 15) /* Bit 15: Escape Sequence Interrupt Enable */ + +/* UART1 Control Register 3 */ + +#define UART1_UCR3_BPEN (1 << 0) /* Bit 0: Preset Registers Enable */ +#define UART1_UCR3_INVT (1 << 1) /* Bit 1: Inverted Infrared Transmission */ +#define UART1_UCR3_REF30 (1 << 2) /* Bit 2: Reference frequency 30 mhz */ +#define UART1_UCR3_REF25 (1 << 3) /* Bit 3: Reference frequency 25 mhz */ +#define UART1_UCR3_AWAKEN (1 << 4) /* Bit 4: Asynchronous wake interrupt enable */ +#define UART1_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asynchronous IR Wake interrupt enable */ +#define UART1_UCR3_RXDSEN (1 << 6) /* Bit 6: Receive status interrupt enable */ +#define UART1_UCR3_FRAERREN (1 << 11) /* Bit 11: Frame error interrupt enable */ +#define UART1_UCR3_PARERREN (1 << 12) /* Bit 12: Parity error interrupt enable */ + +/* UART2/3 Control Register 4 */ + +#define UART2_UCR3_BPEN (1 << 0) /* Bit 0: Preset Registers Enable */ +#define UART2_UCR3_INVT (1 << 1) /* Bit 1: Inverted Infrared Transmission */ +#define UART2_UCR3_REF30 (1 << 2) /* Bit 2: Reference frequency 30 mhz */ +#define UART2_UCR3_REF25 (1 << 3) /* Bit 3: Reference frequency 25 mhz */ +#define UART2_UCR3_AWAKEN (1 << 4) /* Bit 4: Asychronous WAKE Interrupt Enable */ +#define UART2_UCR3_AIRINTEN (1 << 5) /* Bit 5: Asychronous IR WAKE Interrupt Enable */ +#define UART2_UCR3_RXDSEN (1 << 6) /* Bit 6: Receive Status Interrupt Enable */ +#define UART2_UCR3_RI (1 << 7) /* Bit 7: Ring Indicator */ +#define UART2_UCR3_Reserved2 (1 << 8) /* Bit 8: Reserved */ +#define UART2_UCR3_DCD (1 << 9) /* Bit 9: Data Carrier Detect */ +#define UART2_UCR3_DSR (1 << 10) /* Bit 10: Data Set Ready */ +#define UART2_UCR3_FRAERREN (1 << 11) /* Bit 11: Frame Error Interrupt Enable */ +#define UART2_UCR3_PARERREN (1 << 12) /* Bit 12: Parity Error Interrupt Enable */ +#define UART2_UCR3_DTREN (1 << 13) /* Bit 13: Data Terminal Ready Interrupt Enable */ +#define UART2_UCR3_DPEC_SHIFT 14 /* Bit 14-15: DTR Interrupt Edge Control */ +#define UART2_UCR3_DPEC_SHIFT (0x03 << UART_UCR4_DPEC_SHIFT) + +/* UART Control Register 4 */ + +#define UART_UCR4_DREN (1 << 0) /* Bit 0: Receive data ready interrupt enable */ +#define UART_UCR4_OREN (1 << 1) /* Bit 1: Receiver overrun interrupt enable */ +#define UART_UCR4_BKEN (1 << 2) /* Bit 2: Break condition detected interrupt enable */ +#define UART_UCR4_TCEN (1 << 3) /* Bit 3: Transmit complete interrupt enable */ +#define UART_UCR4_IRSC (1 << 5) /* Bit 5: IR special case */ +#define UART_UCR4_REF16 (1 << 6) /* Bit 6: Reference Frequency 16 mhz */ +#define UART_UCR4_WKEN (1 << 7) /* Bit 7: Wake interrupt enable */ +#define UART_UCR4_ENIRI (1 << 8) /* Bit 8: Serial infrared interrupt enable */ +#define UART_UCR4_INVR (1 << 9) /* Bit 9: Inverted infrared reception */ +#define UART_UCR4_CTSTL_SHIFT 10 /* Bits 10-15: CTS trigger level */ +#define UART_UCR4_CTSTL_MASK (0x3f << UART_UCR4_CTSTL_SHIFT) + +/* UART FIFO Control Register */ + +#define UART_UFCR_RXTL_SHIFT 0 /* Bits 0-6: Receiver Trigger Level */ +#define UART_UFCR_RXTL_MASK (0x3f << UART_UFCR_RXTL_SHIFT) +#define UART_UFCR_RFDIV_SHIFT 7 /* Bits 7-9: Reference Frequency Divider */ +#define UART_UFCR_RFDIV_MASK (0x07 << UART_UFCR_RFDIV_SHIFT) +#define UART_UFCR_TXTL_SHIFT 10 /* Bits 10-15: Transmitter Trigger Level */ +#define UART_UFCR_TXTL_MASK (0x3f << UART_UFCR_TXTL_SHIFT) + +/* UART Status 1 Register */ + +#define UART_USR1_AWAKE (1 << 4) /* Bit 4: Asynchronous WAKE Interrupt Flag */ +#define UART_USR1_AIRINT (1 << 5) /* Bit 5: Asynchronous IR WAKE Interrupt Flag */ +#define UART_USR1_RXDS (1 << 6) /* Bit 6: Receiver IDLE Interrupt Flag */ +#define UART_USR1_RRDY (1 << 9) /* Bit 9: RX Ready Interrupt/DMA Flag */ +#define UART_USR1_FRAMERR (1 << 10) /* Bit 10: Frame Error Interrupt Flag */ +#define UART_USR1_ESCF (1 << 11) /* Bit 11: Escape Sequence Interrupt Flag */ +#define UART_USR1_RTSD (1 << 12) /* Bit 12: RTS Delta */ +#define UART_USR1_TRDY (1 << 13) /* Bit 13: TX Ready Interrupt/DMA Flag */ +#define UART_USR1_RTSS (1 << 14) /* Bit 14: RTS Pin Status */ +#define UART_USR1_PARITYERR (1 << 15) /* Bit 15: Parity Error Interrupt Flag */ + +/* UART Status 2 Register */ + +#define UART_USR2_RDR (1 << 0) /* Bit 0: Receive data ready */ +#define UART_USR2_ORE (1 << 1) /* Bit 1: Overrun error */ +#define UART_USR2_BRCD (1 << 2) /* Bit 2: Break condition detected */ +#define UART_USR2_TXDC (1 << 3) /* Bit 3: Transmitter complete */ +#define UART_USR2_RTSF (1 << 4) /* Bit 4: RTS Edge Triggered Interrupt flag */ +#define UART_USR2_WAKE (1 << 7) /* Bit 7: Wake */ +#define UART_USR2_IRINT (1 << 8) /* Bit 8: Serial infrared interrupt flag */ +#define UART_USR2_IDLE (1 << 12) /* Bit 12: Idle condition */ +#define UART_USR2_DTRF (1 << 13) /* Bit 13: DTR edge triggered interrupt flag */ +#define UART_USR2_TXFE (1 << 14) /* Bit 14: Transmit Buffer FIFO empty */ +#define UART_USR2_ADET (1 << 15) /* Bit 15: Automatic baud rate detection complete */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_UART_H */ |