diff options
6 files changed, 82 insertions, 53 deletions
diff --git a/nuttx/arch/arm/include/stm32/stm32f10xxx_irq.h b/nuttx/arch/arm/include/stm32/stm32f10xxx_irq.h index 67f4ba436..0a7c230bc 100644 --- a/nuttx/arch/arm/include/stm32/stm32f10xxx_irq.h +++ b/nuttx/arch/arm/include/stm32/stm32f10xxx_irq.h @@ -61,11 +61,13 @@ * External interrupts (vectors >= 16) */ -#if defined(CONFIG_STM32_VALUELINE) && defined(CONFIG_STM32_MEDIUMDENSITY) + /* Value line devices */ + +#if defined(CONFIG_STM32_VALUELINE) # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ # define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */ # define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ # define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ # define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ @@ -80,12 +82,15 @@ # define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ # define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ # define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ +# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */ /* 19-22: reserved */ # define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ # define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt (TIM16 global interrupt) */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts (TIM17 global interrupt) */ +# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */ # define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ # define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ # define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ @@ -100,29 +105,29 @@ # define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ # define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ # define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALR (57) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */ # define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */ -# if defined(CONFIG_STM32_HIGHDENSITY) -# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ -# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ -# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ +# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ +# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ +# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ /* 46-47: reserved */ -# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ +# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ /* 49: reserved */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI1 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: USART3 global interrupt */ -# else - /* 43-53: reserved */ -# endif +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */ # define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ # define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ # define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ # define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ # define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 global interrupt */ -# define NR_IRQS (76) +# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */ +# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ +# define NR_IRQS (77) + +/* Connectivity Line Devices */ + #elif defined(CONFIG_STM32_CONNECTIVITYLINE) # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ @@ -193,6 +198,9 @@ # define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */ # define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */ # define NR_IRQS (84) + +/* Medium and High Density Devices */ + #else # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h index 160676802..52a513215 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f103vc_pinmap.h @@ -129,7 +129,7 @@ #if 0 /* Needs further investigation */ -#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4) #define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5) #endif diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h index 7a5ec3381..054a7337d 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h @@ -85,7 +85,7 @@ #endif #if 0 /* Needs further investigation */ -#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4) #define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5) #endif diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h index 9bbc21479..2419620fc 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h @@ -85,7 +85,7 @@ #endif #if 0 /* Needs further investigation */ -#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4) #define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5) #endif diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h index ed1bc2625..e38414f31 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h @@ -60,7 +60,14 @@ #define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00 - 0x40000fff: TIM5 timer */ #define STM32_TIM6_BASE 0x40001000 /* 0x40001000 - 0x400013ff: TIM6 timer */ #define STM32_TIM7_BASE 0x40001400 /* 0x40001400 - 0x400007ff: TIM7 timer */ - /* 0x40001800 - 0x40000fff: Reserved */ +#if defined(CONFIG_STM32_VALUELINE) +# define STM32_TIM12_BASE 0x40001800 /* 0x40001800 - 0x40001bff: TIM12 timer */ +# define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00 - 0x40001fff: TIM13 timer */ +# define STM32_TIM14_BASE 0x40002000 /* 0x40002000 - 0x400023ff: TIM14 timer */ + /* 0x40002400 - 0x400027ff: Reserved */ +#else + /* 0x40001800 - 0x40027fff: Reserved */ +#endif #define STM32_RTC_BASE 0x40002800 /* 0x40002800 - 0x40002bff: RTC */ #define STM32_WWDG_BASE 0x40002c00 /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */ #define STM32_IWDG_BASE 0x40003000 /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */ @@ -83,7 +90,12 @@ #define STM32_BKP_BASE 0x40006c00 /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */ #define STM32_PWR_BASE 0x40007000 /* 0x40007000 - 0x400073ff: Power control PWR */ #define STM32_DAC_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC */ +#if defined(CONFIG_STM32_VALUELINE) +# define STM32_CEC_BASE 0x40007800 /* 0x40007800 - 0x40007bff: CEC */ + /* 0x40007c00 - 0x4000ffff: Reserved */ +#else /* 0x40007800 - 0x4000ffff: Reserved */ +#endif /* APB2 bus */ @@ -102,44 +114,53 @@ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000 - 0x400133ff: SPI1 */ #define STM32_TIM8_BASE 0x40013400 /* 0x40013400 - 0x400137ff: TIM8 timer */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800 - 0x40013bff: USART1 */ -#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013fff: ADC3 */ - /* 0x40014000 - 0x40017fff: Reserved */ +#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013c00: ADC3 */ +#if defined(CONFIG_STM32_VALUELINE) + /* 0x40013c00 - 0x40013fff: Reserved */ +# define STM32_TIM15_BASE 0x40014400 /* 0x40014400 - 0x400147ff: TIM15 */ +# define STM32_TIM16_BASE 0x40014400 /* 0x40014400 - 0x400147ff: TIM16 */ +# define STM32_TIM17_BASE 0x40014800 /* 0x40014800 - 0x40014bff: TIM17 */ + /* 0x40014c00 - 0x4001ffff: Reserved */ +#else + /* 0x40013c00 - 0x4001ffff: Reserved */ +#endif + /* AHB bus */ -#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */ - /* 0x40018400 - 0x40017fff: Reserved */ -#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */ -#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */ - /* 0x40020800 - 0x40020fff: Reserved */ -#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */ - /* 0x40021400 - 0x40021fff: Reserved */ -#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */ -#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */ -#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: CRC */ - /* 0x40023400 - 0x40027fff: Reserved */ -#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */ - /* 0x40030000 - 0x4fffffff: Reserved */ +#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */ + /* 0x40018400 - 0x40017fff: Reserved */ +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */ +#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */ + /* 0x40020800 - 0x40020fff: Reserved */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */ + /* 0x40021400 - 0x40021fff: Reserved */ +#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: CRC */ + /* 0x40023400 - 0x40027fff: Reserved */ +#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */ + /* 0x40030000 - 0x4fffffff: Reserved */ /* Peripheral BB base */ -#define STM32_PERIPHBB_BASE 0x42000000 +#define STM32_PERIPHBB_BASE 0x42000000 /* Flexible SRAM controller (FSMC) */ -#define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -#define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ -#define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -#define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/ -#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) +#define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +#define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/ +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) -#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */ /* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this * address range */ -#define STM32_SCS_BASE 0xe000e000 -#define STM32_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h index b8d71799f..1259f2fce 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h @@ -49,15 +49,15 @@ * definition that provides the number of supported vectors. */ -#ifdef CONFIG_ARMV7M_CMNVECTOR +# ifdef CONFIG_ARMV7M_CMNVECTOR -/* Reserve 60 interrupt table entries for I/O interrupts. */ +/* Reserve 61 interrupt table entries for I/O interrupts. */ -# define ARMV7M_PERIPHERAL_INTERRUPTS 60 +# define ARMV7M_PERIPHERAL_INTERRUPTS 61 #else -# error This target requires CONFIG_ARMV7M_CMNVECTOR -#endif /* CONFIG_ARMV7M_CMNVECTOR */ +# error This target requires CONFIG_ARMV7M_CMNVECTOR +# endif /* CONFIG_ARMV7M_CMNVECTOR */ #elif defined(CONFIG_STM32_CONNECTIVITYLINE) |