diff options
| -rw-r--r-- | nuttx/ChangeLog | 6 | ||||
| -rw-r--r-- | nuttx/Documentation/NuttX.html | 6 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h | 38 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h (renamed from nuttx/arch/arm/src/sam34/chip/sam_matrix.h) | 129 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pio.h | 1 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h | 584 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_supc.h | 238 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam4s_pio.h | 1 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_clockconfig.c | 34 | ||||
| -rw-r--r-- | nuttx/configs/sam3u-ek/include/board.h | 12 | ||||
| -rw-r--r-- | nuttx/mm/Kconfig | 9 |
12 files changed, 698 insertions, 368 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c3e842043..60d7be5be 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4937,4 +4937,8 @@ * configs/sam4l-xplained/src/sam_cxxinitialize.c: Added C++ support to the SAM4L Xplained Pro board configuration (2013-6-9). * arm/src/sam34/chip/sam_irq.c: Extend IRQ support to handle the - larger number of NVIC interrupts used by the SAM4L (2013-6-9).
\ No newline at end of file + larger number of NVIC interrupts used by the SAM4L (2013-6-9). + * arch/srcm/sam45/chip: Beginning updates of SAM3U header files + to include support for the SAM4S: WDT, SUPC, EEFC, MATRIX, and PMC + (2013-6-10). + diff --git a/nuttx/Documentation/NuttX.html b/nuttx/Documentation/NuttX.html index cfa518a64..d08327d25 100644 --- a/nuttx/Documentation/NuttX.html +++ b/nuttx/Documentation/NuttX.html @@ -2977,7 +2977,7 @@ nsh> </p> <p> <b>Memory Usage</b>. - The ATSAM4LC4C comes in a 61004-pin package and has 256KB FLASH and 32KB of SRAM. + The ATSAM4LC4C comes in a 100-pin package and has 256KB FLASH and 32KB of SRAM. Below is the current memory usage for the NSH configuration (June 9, 2013). This is <i>not</i> a minimal implementation, but a full-featured NSH configuration. </p> @@ -3469,10 +3469,6 @@ Mem: 29232 5920 23312 23312 </td> </tr> <tr> - <td><br></td> - <td><br></td> -</tr> -<tr> <td valign="top"><img height="20" width="20" src="favicon.ico"></td> <td bgcolor="#5eaee1"> <a name="superh"><b>Renesas/Hitachi SuperH</b>.</a> diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h index 05ffad19b..974aef0cd 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_eefc.h + * Enhanced Embedded Flash Controller (EEFC) defintions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -74,20 +75,38 @@ #define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET) /* EEFC register bit definitions ********************************************************/ +/* EEFC Flash Mode Register */ #define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ #define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ #define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FMR_SCOD (1 << 16) /* Bit 16: Sequential Code Optimization Disable */ +#endif + #define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FMR_CLOE (1 << 26) /* Bit 26: Code Loops Optimization Enable */ +#endif + +/* EEFC Flash Command Register */ + #define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ #define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) + # define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ # define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ # define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ # define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ # define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ # define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FCR_FCMD_EPA (7 << EEFC_FCR_FCMD_SHIFT) /* Erase Pages */ +#endif + # define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ # define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ # define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ @@ -96,15 +115,32 @@ # define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ # define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ # define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FCR_FCMD_GCALB (16 << EEFC_FCR_FCMD_SHIFT) /* Get CALIB Bit */ +# define EEFC_FCR_FCMD_ES (17 << EEFC_FCR_FCMD_SHIFT) /* Erase Sector */ +# define EEFC_FCR_FCMD_WUS (18 << EEFC_FCR_FCMD_SHIFT) /* Write User Signature */ +# define EEFC_FCR_FCMD_EUS (19 << EEFC_FCR_FCMD_SHIFT) /* Erase User Signature */ +# define EEFC_FCR_FCMD_STUS (20 << EEFC_FCR_FCMD_SHIFT) /* Start Read User Signature */ +# define EEFC_FCR_FCMD_SPUS (21 << EEFC_FCR_FCMD_SHIFT) /* Stop Read User Signature */ +#endif + #define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ #define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) #define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ -#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) +#define EEFC_FCR_FKEY_MASK (0xff << EEFC_FCR_FKEY_SHIFT) +# define EEFC_FCR_FKEY_PASSWD (0x5a << EEFC_FCR_FKEY_SHIFT) + +/* EEFC Flash Status Register */ #define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ #define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ #define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define EEFC_FSR_FLERR (1 << 3) /* Bit 3: Flash Error Status */ +#endif + /**************************************************************************************** * Public Types ****************************************************************************************/ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h b/nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h index 6fed14092..6a8274006 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_matrix.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_matrix.h @@ -1,5 +1,6 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam_matric.h + * arch/arm/src/sam34/chip/sam_34matrix.h + * Bux matrix definitions for the SAM3U and SAM4S * * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -33,8 +34,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H /**************************************************************************************** * Included Files @@ -64,12 +65,16 @@ #define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ #define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ #define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ -#define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ -#define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ -#define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ -#define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ -#define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ - /* 0x0068-0x007c: Reserved */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +# define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +# define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +# define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +# define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ + /* 0x0068-0x007c: Reserved (SAM3U) */ +#endif + /* 0x0054-0x007c: Reserved (SAM4S) */ #define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) #define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ /* 0x0084: Reserved */ @@ -80,19 +85,29 @@ #define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ /* 0x009c: Reserved */ #define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) /* 0x00a4: Reserved */ -#define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ +# define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ /* 0x00ac: Reserved */ -#define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ +# define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ /* 0x00b4: Reserved */ -#define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ +# define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ /* 0x00bc: Reserved */ -#define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ +# define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ /* 0x00c4: Reserved */ -#define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ +# define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ /* 0x00cc-0x00fc: Reserved */ -#define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ - /* 0x0104-0x010c: Reserved */ +# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0x0104-0x01e0: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x00a4-0x110: Reserved */ +# define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */ + /* 0x0118: Reserved */ +# define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x011c /* SMC Chip Select NAND Flash Assignment Register */ + /* 0x0120-0x01e0: Reserved */ +#endif + #define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ #define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ /* 0x0110 - 0x01fc: Reserved */ @@ -112,11 +127,13 @@ #define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET) #define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET) #define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET) -#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) -#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) -#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) -#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) -#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) +# define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) +# define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) +# define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) +# define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#endif #define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n)) #define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET) @@ -124,17 +141,26 @@ #define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET) #define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET) #define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET) -#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) -#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) -#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) -#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) -#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) +# define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) +# define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) +# define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) +# define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#endif + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_MATRIX_CCFG_SYSIO (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET) +# define SAM_MATRIX_CCFG_SMCNFCS (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET) +#endif -#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) #define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) #define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) /* MATRIX register bit definitions ******************************************************/ +/* Master Configuration Registers */ #define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ #define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) @@ -144,6 +170,8 @@ # define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ # define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ +/* Bus Matrix Slave Configuration Registers */ + #define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ #define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) #define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ @@ -165,12 +193,13 @@ # define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) # define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) # define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) - #define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ #define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) # define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ # define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ +/* Bus Matrix Priority Registers For Slaves */ + #define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) #define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) #define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ @@ -184,16 +213,46 @@ #define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ #define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) -#define MATRIX_MRCR_RCB(x) (1 << (x)) -#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ -#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ -#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ -#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ -#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ +/* System I/O Configuration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define MATRIX_CCFG_SYSIO_SYSIO4 (1 << 4) /* Bit 4: PB4 or TDI Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO5 (1 << 5) /* Bit 5: PB5 or TDO/TRACESWO Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO10 (1 << 10) /* Bit 10: PB10 or DDM Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO11 (1 << 11) /* Bit 11: PB11 or DDP Assignment */ +# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */ +#endif + +/* SMC Chip Select NAND Flash Assignment Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS0 (1 << 0) /* Bit 0: SMC NAND Flash Chip Select 0 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS1 (1 << 1) /* Bit 1: SMC NAND Flash Chip Select 2 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS2 (1 << 2) /* Bit 2: SMC NAND Flash Chip Select 2 Assignment */ +# define MATRIX_CCFG_SMCNFCS_SMC_NFCS3 (1 << 3) /* Bit 3: SMC NAND Flash Chip Select 3 Assignment */ +#endif + +/* Master Remap Control Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define MATRIX_MRCR_RCB(x) (1 << (x)) +# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ +# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ +# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ +# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ +# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ +#endif + +/* Write Protect Mode Register */ #define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ #define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) +# define MATRIX_WPMR_WPKEY (0x004d4154 << MATRIX_WPMR_WPKEY_SHIFT) + +/* Write Protect Status Register */ #define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ #define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ @@ -211,4 +270,4 @@ * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MATRIX_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h index 14ceb0724..f43832813 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_pio.h + * Parallel Input/Output (PIO) Controller definitions for the SAM3U * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h index 762110081..4f26b83d9 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -1,5 +1,6 @@ -/**************************************************************************************** +/******************************************************************************************** * arch/arm/src/sam34/chip/sam3u_pmc.h + * Power Management Controller (PMC) for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -31,285 +32,434 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************/ + ********************************************************************************************/ #ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H #define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H -/**************************************************************************************** +/******************************************************************************************** * Included Files - ****************************************************************************************/ + ********************************************************************************************/ #include <nuttx/config.h> #include "chip.h" #include "chip/sam_memorymap.h" -/**************************************************************************************** +/******************************************************************************************** * Pre-processor Definitions - ****************************************************************************************/ - -/* PMC register offsets *****************************************************************/ - -#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ -#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ -#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ - /* 0x000c: Reserved */ -#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ -#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ -#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ -#define SAM_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ -#define SAM_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ -#define SAM_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ -#define SAM_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ - /* 0x002c: Reserved */ -#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ - /* 0x0034-0x003C Reserved */ -#define SAM_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) -#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ -#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ -#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ - /* 0x004c-0x005c: Reserved */ -#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ -#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ -#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ -#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ -#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ -#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ -#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ - /* 0x007c-0x00fc: Reserved */ -#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ - -/* PMC register adresses ****************************************************************/ - -#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) -#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) -#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) -#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) -#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) -#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) -#define SAM_CKGR_UCKR (SAM_PMC_BASE+SAM_CKGR_UCKR_OFFSET) -#define SAM_CKGR_MOR (SAM_PMC_BASE+SAM_CKGR_MOR_OFFSET) -#define SAM_CKGR_MCFR (SAM_PMC_BASE+SAM_CKGR_MCFR_OFFSET) -#define SAM_CKGR_PLLAR (SAM_PMC_BASE+SAM_CKGR_PLLAR_OFFSET) -#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) -#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) -#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) -#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) -#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) -#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) -#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) -#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) -#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) -#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) -#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) -#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) -#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) -#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) - -/* PMC register bit definitions *********************************************************/ + ********************************************************************************************/ + +/* PMC register offsets *********************************************************************/ + +#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#endif + /* 0x001c: Reserved (SAM4S)*/ +#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */ +#endif + /* 0x002c: Reserved (SAM3U)*/ +#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x0034 Reserved */ +# define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register PMC_USB */ + /* 0x003c Reserved */ +#endif + /* 0x0034-0x003c Reserved (SAM3U) */ +#define SAM_PMC_PCK_OFFSET(n) (0x0040 + ((n) << 2)) +#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ +#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c-0x00e0: Reserved */ +#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) + /* 0x00ec-0x00fc Reserved */ +# define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */ +# define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */ +# define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */ + /* 0x010c Reserved */ +# define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */ + /* 0x003c Reserved */ +#endif + +/* PMC register adresses ********************************************************************/ + +#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) +#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) +#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) +#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) +#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) +#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_CKGR_UCKR (SAM_PMC_BASE+SAM_PMC_CKGR_UCKR_OFFSET) +#endif + +#define SAM_PMC_CKGR_MOR (SAM_PMC_BASE+SAM_PMC_CKGR_MOR_OFFSET) +#define SAM_PMC_CKGR_MCFR (SAM_PMC_BASE+SAM_PMC_CKGR_MCFR_OFFSET) +#define SAM_PMC_CKGR_PLLAR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLAR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_CKGR_PLLBR (SAM_PMC_BASE+SAM_PMC_CKGR_PLLBR_OFFSET) +# define SAM_PMC_USB (SAM_PMC_BASE+SAM_PMC_USB_OFFSET) +#endif + +#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET) +#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n)) +#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET) +#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET) +#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET) +#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET) +#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET) +#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET) +#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET) +#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET) +#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET) +#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET) +#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET) +#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET) +# define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET) +# define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET) +# define SAM_PMC_OCR (SAM_PMC_BASE+SAM_PMC_OCR_OFFSET) +#endif + +/* PMC register bit definitions *************************************************************/ /* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System * Clock Status Register common bit-field definitions */ -#define PMC_PCK(n) (1 <<((n)+8) -#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ -#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ -#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_UDP (1 << 7) /* Bit 7: USB Device Port Clock Enable */ +#endif + +#define PMC_PCK(n) (1 << ((n) + 8) +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ /* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC * Peripheral Clock Status Register common bit-field definitions. */ -#define PMC_PID(n) (1<<(n)) -#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ -#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ -#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ -#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ -#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ -#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ -#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ -#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ -#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ -#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ -#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ -#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ -#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ -#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ -#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ -#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ -#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ -#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ -#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ -#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ -#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ -#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ -#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ -#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ -#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ -#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ -#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ -#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ -#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ -#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ +#define PMC_PID(n) (1 << (n)) +#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ /* PMC UTMI Clock Configuration Register */ -#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ -#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ -#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +# define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +# define PMC_CKGR_UCKR_UPLLCOUNT_MASK (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) +#endif /* PMC Clock Generator Main Oscillator Register */ -#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) -#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ -#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) -#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ +#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define PMC_CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ +#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ +#define PMC_CKGR_MOR_MOSCRCF_MASK (7 << PMC_CKGR_MOR_MOSCRCF_SHIFT) +# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */ +# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */ +# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */ +#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT) +#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT) +# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT) +#define PMC_CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define PMC_CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ /* PMC Clock Generator Main Clock Frequency Register */ -#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ -#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) -#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ +#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT) +#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */ +#endif /* PMC Clock Generator PLLA Register */ -#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ -#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) -# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ -# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ -# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ -#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ -#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) -# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ -# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ -#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ -#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) -#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ +#define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +#define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT) +# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ + +#define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ +# define PMC_CKGR_PLLAR_STMODE_MASK (3 << PMC_CKGR_PLLAR_STMODE_SHIFT) +# define PMC_CKGR_PLLAR_STMODE_FAST (0 << PMC_CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ +# define PMC_CKGR_PLLAR_STMODE_NORMAL (2 << PMC_CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ +#endif + +#define PMC_CKGR_PLLAR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +#define PMC_CKGR_PLLAR_MUL_MASK (0x7ff << PMC_CKGR_PLLAR_MUL_SHIFT) +#define PMC_CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PLLB Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_PLLBR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +# define PMC_CKGR_PLLBR_DIV_MASK (0xff << PMC_CKGR_PLLBR_DIV_SHIFT) +# define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLBR_DIV_BYPASS (1 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLBR_DIV(n) ((n) << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ +# define PMC_CKGR_PLLBR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +# define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT) +# define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +# define PMC_CKGR_PLLBR_MUL_MASK (0x7ff << PMC_CKGR_PLLBR_MUL_SHIFT) +#endif + +/* USB Clock Register PMC_USB */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */ +# define PMC_USB_USBS_PLLA (0) +# define PMC_USB_USBS_PLLB PMC_USB_USBS +# define PMC_USB_USBDIV_SHIFT (8) /* Bits 8-11: Divider for USB Clock */ +# define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT) +#endif /* PMC Master Clock Register */ -#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ -#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) -# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ -# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ -# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ -# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ -#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ -#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) -# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ -# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ -# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ -#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ + +# if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_MCKR_CSS_PLLB (3 << PMC_MCKR_CSS_SHIFT) /* PLLB Clock */ +# elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +# endif + +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_MCKR_PLLADIV2 (1 << 13) /* Bit 13: PLLA Divider */ +# define PMC_MCKR_PLLBDIV2 (1 << 14) /* Bit 14: PLLB Divider */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ +#endif /* PMC Programmable Clock Register (0,1,2) */ -#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ -#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) -# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ -# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ -# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ -# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ -# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ -#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ -#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) -# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ -# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_MASK) /* PLLB Clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +#endif + +# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_MASK) /* Master Clock */ + +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ /* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, * and PMC Interrupt Mask Register common bit-field definitions */ -#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ -#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ -#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ -#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ -#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ -#define PMC_INT_PCKRDY(n) (1 << ((n)+8) -#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ -#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ -#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ -#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ -#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ -#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ -#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ -#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_INT_LOCKB (1 << 2) /* Bit 2: PLL B Lock Interrupt */ +#endif + +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#endif + +#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ +#define PMC_INT_PCKRDY(n) (1 << ((n)+8) +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ /* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field * definitions */ -#define PMC_FSTI(n) (1 << (n)) -#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ -#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ -#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ -#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ -#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ -#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ -#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ -#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ -#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ -#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ -#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ -#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ -#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ -#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ -#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ -#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ - -#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ -#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ -#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ -#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ +#define PMC_FSTI(n) (1 << (n)) +#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ +#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ +#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ +#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ +#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ +#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ +#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ +#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ +#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ +#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ +#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ +#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ +#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ +#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ +#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ +#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ +#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ +#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ +#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_FSMR_FLPM_SHIFT (21) /* Bit 21-22: Low Power Mode (MR only) */ +# define PMC_FSMR_FLPM_MASK (3 << PMC_FSMR_FLPM_SHIFT) +# define PMC_FSMR_FLPM_PWRDOWN (0 << PMC_FSMR_FLPM_SHIFT) /* Flash Standby Mode */ +# define PMC_FSMR_FLPM_STANDBY (1 << PMC_FSMR_FLPM_SHIFT) /* Flash deep power down mode */ +# define PMC_FSMR_FLPM_IDLE (2 << PMC_FSMR_FLPM_SHIFT) /* Idle mode */ +#endif + +/* Fast Startup Polarity Register */ + +#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarityn, n=0..15 */ /* PMC Fault Output Clear Register */ -#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ /* PMC Write Protect Mode Register */ -#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) +# define PMC_WPMR_WPKEY (0x00504d43 << PMC_WPMR_WPKEY_SHIFT) /* PMC Write Protect Status Register */ -#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/* Peripheral Clock Enable Register 1 */ +/* Peripheral Clock Disable Register 1 */ +/* Peripheral Clock Status Register 1 */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_PIC32 (1 << 0) /* Bit 0: PID32 */ +# define PMC_PIC33 (1 << 1) /* Bit 1: PID33 */ +# define PMC_PIC34 (1 << 2) /* Bit 2: PID34 */ +#endif + +/* Oscillator Calibration Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_OCR_CAL4_SHIFT (0) /* Bits 0-6: 4MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL4_MASK (0x7f << PMC_OCR_CAL4_SHIFT) +# define PMC_OCR_SEL4 (1 << 7) /* Bit 7: Select 4MHz RC Oscillator Calibration */ +# define PMC_OCR_CAL8_SHIFT (8) /* Bits 8-14: 8MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT) +# define PMC_OCR_SEL8 (1 << 15) /* Bit 15: Select 8MHz RC Oscillator Calibration */ +# define PMC_OCR_CAL12_SHIFT (16) /* Bits 16-22: 12MHzRC Oscillator Calibration */ +# define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT) +# define PMC_OCR_SEL12 (1 << 23) /* Bit 23: Select 12MHz RC Oscillator Calibration */ +#endif + +/******************************************************************************************** * Public Types - ****************************************************************************************/ + ********************************************************************************************/ -/**************************************************************************************** +/******************************************************************************************** * Public Data - ****************************************************************************************/ + ********************************************************************************************/ -/**************************************************************************************** +/******************************************************************************************** * Public Functions - ****************************************************************************************/ + ********************************************************************************************/ #endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h index 88f9452d8..aea757717 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_supc.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_supc.h + * Supply Controller (SUPC) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -51,93 +52,159 @@ /* SUPC register offsets ****************************************************************/ -#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ -#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ -#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ -#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ -#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ -#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ +#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ +#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ +#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ +#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ +#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ +#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ /* SUPC register adresses ***************************************************************/ -#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) -#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) -#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) -#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) -#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) -#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) +#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET) +#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET) +#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET) +#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET) +#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET) +#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET) /* SUPC register bit definitions ********************************************************/ +/* Supply Controller Control Register */ + +#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ +#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ +#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) +# define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT) + +/* Supply Controller Supply Monitor Mode Register */ + +#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) + +# if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */ +# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */ +# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */ +# define SUPC_SMMR_SMTH_2p0V (3 << SUPC_SMMR_SMTH_SHIFT) /* 1.91 < 1.96 < 2.01 */ +# define SUPC_SMMR_SMTH_2p1V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.03 < 2.08 < 2.13 */ +# define SUPC_SMMR_SMTH_2p2V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.15 < 2.2 < 2.23 */ +# define SUPC_SMMR_SMTH_2p3V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.26 < 2.32 < 2.38 */ +# define SUPC_SMMR_SMTH_2p4V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.38 < 2.44 < 2.50 */ +# define SUPC_SMMR_SMTH_2p6V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.50 < 2.56 < 2.62 */ +# define SUPC_SMMR_SMTH_2p7V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.61 < 2.68 < 2.75 */ +# define SUPC_SMMR_SMTH_2p8V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.73 < 2.8 < 2.87 */ +# define SUPC_SMMR_SMTH_2p9V (11 << SUPC_SMMR_SMTH_SHIFT) /* 2.85 < 2.92 < 2.99 */ +# define SUPC_SMMR_SMTH_3p0V (12 << SUPC_SMMR_SMTH_SHIFT) /* 2.96 < 3.04 < 3.12 */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */ +# elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ +# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ +# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ +# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ +# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ +# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ +# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ +# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ +# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ +# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ +# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ +# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ +# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ +#endif + +#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) +# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ +# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ +# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ + +/* Supply Controller Mode Register */ + +#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ +#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ +#endif + +#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ +#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ +#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) + +/* Supply Controller Wake Up Mode Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ +#endif + +#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */ +# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */ +# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ +# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) +# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ +# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ +#endif + +#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) +# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */ +# define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT) +# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */ +# define SUPC_WUMR_LPDBC_2_RTCOUT0 (1 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 2 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_3_RTCOUT0 (2 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 3 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_4_RTCOUT0 (3 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 4 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_5_RTCOUT0 (4 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 5 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_6_RTCOUT0 (5 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 6 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_7_RTCOUT0 (6 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 7 RTCOUT0 */ +# define SUPC_WUMR_LPDBC_8_RTCOUT0 (7 << SUPC_WUMR_LPDBC_SHIFT) /* WKUP0/1 for 8 RTCOUT0 */ +#endif + +/* System Controller Wake Up Inputs Register */ + +#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ +#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) +# define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ +#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) +# define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) + +/* Supply Controller Status Register */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ +#endif -#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ -#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ -#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) - -#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) -# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ -# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ -# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ -# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ -# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ -# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ -# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ -# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ -# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ -# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ -# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ -# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ -# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ -# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ -# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ -# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ -#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) -# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ -# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ -# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ -# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ - -#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ -#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ -#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ -#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ -#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ -#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) - -#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ -#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ -#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) - #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ - #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) -# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ -# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ - -#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ -#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ -#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) -#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) - -#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ #define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ #define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ #define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ @@ -145,7 +212,14 @@ #define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ #define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ #define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ -#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */ +# define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */ +#endif + #define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ #define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h index b4d28c71a..04132cd4b 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam3u_wdt.h + * Watchdog Timer (WDT) definitions for the SAM3U and SAM4S * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -62,22 +63,27 @@ #define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET) /* WDT register bit definitions ********************************************************/ +/* Watchdog Timer Control Register */ #define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ #define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ #define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) +/* Watchdog Timer Mode Register */ + #define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ #define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) #define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ #define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ #define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ #define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */ #define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) #define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ #define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ +/* Watchdog Timer Status Register */ + #define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ #define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h index c65d5dcbe..e5412a5f4 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pio.h @@ -1,5 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam4s_pio.h + * Parallel Input/Output (PIO) Controller definitions for the SAM4S * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> diff --git a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c index 9470c3aa0..1a911b7a3 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c @@ -53,7 +53,7 @@ #include "chip/sam3u_eefc.h" #include "chip/sam3u_wdt.h" #include "chip/sam3u_supc.h" -#include "chip/sam_matrix.h" +#include "chip/sam3u_matrix.h" /**************************************************************************** * Pre-processor Definitions @@ -63,21 +63,17 @@ * in board.h */ -#define CKGR_MOR_KEY (0x37 << CKGR_MOR_KEY_SHIFT) -#define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT) +#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \ + PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN) -#define BOARD_CKGR_MOR (CKGR_MOR_KEY|BOARD_CKGR_MOR_MOSCXTST|\ - CKGR_MOR_MOSCRCEN|CKGR_MOR_MOSCXTEN) +#define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \ + BOARD_CKGR_PLLAR_DIV) -#define BOARD_CKGR_PLLAR (CKGR_PLLAR_ONE|BOARD_CKGR_PLLAR_MULA|\ - BOARD_CKGR_PLLAR_STMODE|BOARD_CKGR_PLLAR_PLLACOUNT|\ - BOARD_CKGR_PLLAR_DIVA) - -#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES|PMC_MCKR_CSS_MAIN) -#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES|BOARD_PMC_MCKR_CSS) - -#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT|CKGR_UCKR_UPLLEN) +#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN) +#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS) +#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN) /**************************************************************************** * Public Data @@ -170,7 +166,7 @@ static inline void sam_pmcsetup(void) /* Enable main oscillator (if it has not already been selected) */ - if ((getreg32(SAM_CKGR_MOR) & CKGR_MOR_MOSCSEL) == 0) + if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0) { /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to * enable the main oscillator, the MOSCXTS bit in the Power Management @@ -180,7 +176,7 @@ static inline void sam_pmcsetup(void) * indicating that the main clock is valid." */ - putreg32(BOARD_CKGR_MOR, SAM_CKGR_MOR); + putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); sam_pmcwait(PMC_INT_MOSCXTS); } @@ -196,7 +192,7 @@ static inline void sam_pmcsetup(void) * 1 = Selection is in progress */ - putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM_CKGR_MOR); + putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR); sam_pmcwait(PMC_INT_MOSCSELS); /* "Select the master clock. "The Master Clock selection is made by writing @@ -216,15 +212,15 @@ static inline void sam_pmcsetup(void) /* Settup PLLA and wait for LOCKA */ - putreg32(BOARD_CKGR_PLLAR, SAM_CKGR_PLLAR); + putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); sam_pmcwait(PMC_INT_LOCKA); /* Setup UTMI for USB and wait for LOCKU */ #ifdef CONFIG_USBDEV - regval = getreg32(SAM_CKGR_UCKR); + regval = getreg32(SAM_PMC_CKGR_UCKR); regval |= BOARD_CKGR_UCKR; - putreg32(regval, SAM_CKGR_UCKR); + putreg32(regval, SAM_PMC_CKGR_UCKR); sam_pmcwait(PMC_INT_LOCKU); #endif diff --git a/nuttx/configs/sam3u-ek/include/board.h b/nuttx/configs/sam3u-ek/include/board.h index b5e112479..683c15004 100644 --- a/nuttx/configs/sam3u-ek/include/board.h +++ b/nuttx/configs/sam3u-ek/include/board.h @@ -60,14 +60,14 @@ /* Main oscillator register settings */ -#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ +#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ /* PLLA configuration */ -#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT) -#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST -#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS +#define BOARD_CKGR_PLLAR_MUL (7 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS /* PMC master clock register settings */ @@ -76,7 +76,7 @@ /* USB UTMI PLL start-up time */ -#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT) +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) /* Resulting frequencies */ diff --git a/nuttx/mm/Kconfig b/nuttx/mm/Kconfig index 960c979e8..20d83b5db 100644 --- a/nuttx/mm/Kconfig +++ b/nuttx/mm/Kconfig @@ -56,7 +56,14 @@ config MM_SMALL MM_SMALL can be defined so that those MCUs will also benefit from the smaller, 16-bit-based allocation overhead. - NOTE: If MM_MULTIHEAP is selected, then this applies to all heaps. + WARNING: This selection will also change the alignment of allocated + memory. For example, on ARM memory will have 8-byte alignment by + default. If MM_SMALL is selected, then allocated memory will have + only 4-byte alignment. This may be important on some platforms where + 64-bit data is in allocated structures and 8-byte alignment is required. + + NOTE: If MM_MULTIHEAP is selected, then this selection applies to all + heaps. config MM_REGIONS int "Number of memory regions" |