diff options
| -rw-r--r-- | nuttx/ChangeLog | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/sam34/chip.h | 216 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/sam34/irq.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/sam34/sam3u_irq.h | 14 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/sam34/sam3x_irq.h | 429 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/sam34/sam4l_irq.h | 16 | ||||
| -rw-r--r-- | nuttx/arch/arm/include/sam34/sam4s_irq.h | 10 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/Kconfig | 48 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/src/sam4s-xplained.h | 1 |
9 files changed, 688 insertions, 50 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c4228ff50..5635dbf05 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5054,4 +5054,6 @@ for SAM4S B and C peripherals (2013-6-26) * configs/sam4s-xplained/src/sam_sram.c: Added support for on-board 1MB SRAM (2013-6-26). + * arch/arm/src/include/sam34/chip.h and sam3x_irq.h: Add support for + SAM3X and SAM3A chips (2013-6-26). diff --git a/nuttx/arch/arm/include/sam34/chip.h b/nuttx/arch/arm/include/sam34/chip.h index d40952d7a..3a4364c52 100644 --- a/nuttx/arch/arm/include/sam34/chip.h +++ b/nuttx/arch/arm/include/sam34/chip.h @@ -66,6 +66,152 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +/* AT91SAM3X/3A Families ************************************************************/ +/* FEATURE SAM3X8E SAM3X8C SAM3X4E SAM3X4C SAM3A8C SAM3A4C + * ------------ -------- -------- -------- -------- -------- -------- + * Flash 2x256KB 2x256KB 2x128KB 2x128KB 2x256KB 2x128KB + * SRAM 64+32KB 64+32KB 32+32KB 32+32KB 64+32KB 32+32KB + * NFC Yes --- Yes --- --- --- + * NFC SRAM 4KB --- 4KB --- --- --- + * Package LQFP144 LQFP100 LQFP144 LQFP100 LQFP100 LQFP100 + * LFBGA144 LFBGA100 LFBGA144 LFBGA100 LFBGA100 LFBGA100 + * No. PIOs 103 63 103 63 63 63 + * SHDN Pin Yes No Yes No No No + * EMAC MII/RMII RMII MII/RMII RMII --- --- + * EBI Yes --- Yes --- --- --- + * SDRAM --- --- --- --- --- --- + * DMA 6 4 6 4 4 4 + * 12-bit ADC 16ch 16ch 16ch 16ch 16ch 16ch + * 12-bit DAC 2ch 2ch 2ch 2ch 2ch 2ch + * 32-bit Timer 9 9 9 9 9 9 + * PDC Channels 17 15 17 15 15 15 + * USART 3 3 3 3 3 3 + * UART 2 1 2 1 1 1 + * SPI 1/4+3 1/4+3 1/4+3 1/4+3 1/4+3 1/4+3 + * HSMCI 8 bit 4 bit 8 bit 4 bit 4 bit 4 bit + */ + +#if defined(CONFIG_ARCH_CHIP_AT91SAM3X8E) + +/* Internal memory */ + +# define SAM34_FLASH_SIZE (512*1024) /* 512KB */ +# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */ +# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */ +# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 6 /* 6 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 1 /* One USB high speed embedded host */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM3X8C) + +/* Internal memory */ + +# define SAM34_FLASH_SIZE (512*1024) /* 512KB */ +# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */ +# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */ +# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 1 /* One USB high speed embedded host */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM3X4E) + +/* Internal memory */ + +# define SAM34_FLASH_SIZE (256*1024) /* 256KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */ +# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 6 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 1 /* One USB high speed embedded host */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM3X4C) + +/* Internal memory */ + +# define SAM34_FLASH_SIZE (256*1024) /* 256KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ +# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */ +# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 1 /* One USB high speed embedded host */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM3A8C) + +/* Internal memory */ + +# define SAM34_FLASH_SIZE (512*1024) /* 512KB */ +# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */ +# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */ +# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 1 /* One USB high speed embedded host */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM3A4C) + +/* Internal memory */ + +# define SAM34_FLASH_SIZE (256*1024) /* 256KB */ +# define SAM34_SRAM0_SIZE (32*1024) /* 64KB */ +# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */ +# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUHPHS 1 /* One USB high speed embedded host */ # define SAM32_NUDPFS 0 /* No USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -125,8 +271,8 @@ # define SAM34_FLASH_SIZE (128*1024) /* 128KB */ # define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -135,6 +281,7 @@ # define SAM32_NSLCD 1 /* 1 segment LCD interface */ # define SAM32_NAESA 1 /* 1 advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ @@ -145,8 +292,8 @@ # define SAM34_FLASH_SIZE (256*1024) /* 256KB */ # define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -155,6 +302,7 @@ # define SAM32_NSLCD 1 /* 1 segment LCD interface */ # define SAM32_NAESA 1 /* 1 advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ @@ -165,8 +313,8 @@ # define SAM34_FLASH_SIZE (128*1024) /* 128KB */ # define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -175,6 +323,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -185,8 +334,8 @@ # define SAM34_FLASH_SIZE (256*1024) /* 256KB */ # define SAM34_SRAM0_SIZE (32*1024) /* 32KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -195,6 +344,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -222,8 +372,8 @@ # define SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */ # define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -232,6 +382,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -240,8 +391,8 @@ # define SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */ # define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -250,6 +401,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -258,8 +410,8 @@ # define SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */ # define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -268,6 +420,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -276,8 +429,8 @@ # define SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */ # define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -286,6 +439,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -294,8 +448,8 @@ # define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ # define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -304,6 +458,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -312,8 +467,8 @@ # define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ # define SAM34_SRAM0_SIZE (160*1024) /* 160KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -322,6 +477,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -330,8 +486,8 @@ # define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ # define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -340,6 +496,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -348,8 +505,8 @@ # define SAM34_FLASH_SIZE (1024*1024) /* 1MB */ # define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -358,6 +515,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -366,8 +524,8 @@ # define SAM34_FLASH_SIZE (512*1024) /* 512KB */ # define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -376,6 +534,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ @@ -384,8 +543,8 @@ # define SAM34_FLASH_SIZE (512*1024) /* 512KB */ # define SAM34_SRAM0_SIZE (128*1024) /* 128KB */ -# define SAM34_SRAM1_SIZE (0) /* None */ -# define SAM34_NFCSRAM_SIZE (0) /* None */ +# define SAM34_SRAM1_SIZE 0 /* None */ +# define SAM34_NFCSRAM_SIZE 0 /* None */ /* Peripherals */ @@ -394,6 +553,7 @@ # define SAM32_NSLCD 0 /* No segment LCD interface */ # define SAM32_NAESA 0 /* No advanced encryption standard */ # define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUHPHS 0 /* No USB high speed embedded host */ # define SAM32_NUDPFS 1 /* 1 USB full speed device */ # define SAM32_NUHPFS 0 /* No USB full speed embedded host */ diff --git a/nuttx/arch/arm/include/sam34/irq.h b/nuttx/arch/arm/include/sam34/irq.h index 4925273eb..205b82d63 100644 --- a/nuttx/arch/arm/include/sam34/irq.h +++ b/nuttx/arch/arm/include/sam34/irq.h @@ -79,6 +79,8 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include <arch/sam34/sam3u_irq.h> +#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) +# include <arch/sam34/sam3x_irq.h> #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include <arch/sam34/sam4l_irq.h> #elif defined(CONFIG_ARCH_CHIP_SAM4S) diff --git a/nuttx/arch/arm/include/sam34/sam3u_irq.h b/nuttx/arch/arm/include/sam34/sam3u_irq.h index e3e8aded7..f71d66883 100644 --- a/nuttx/arch/arm/include/sam34/sam3u_irq.h +++ b/nuttx/arch/arm/include/sam34/sam3u_irq.h @@ -120,7 +120,7 @@ /* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ #ifdef CONFIG_GPIOA_IRQ -# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT) # define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ # define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ # define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ @@ -159,7 +159,7 @@ #endif #ifdef CONFIG_GPIOB_IRQ -# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS) # define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ # define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ # define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ @@ -192,13 +192,13 @@ # define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ # define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ # define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +# define SAM_NGPIOBIRQS 32 #else # define SAM_NGPIOBIRQS 0 #endif #ifdef CONFIG_GPIOC_IRQ -# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS+SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS) # define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ # define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ # define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ @@ -231,15 +231,15 @@ # define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ # define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ # define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +# define SAM_NGPIOCIRQS 32 #else # define SAM_NGPIOCIRQS 0 #endif /* Total number of IRQ numbers */ -#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+\ - SAM_NGPIOAIRQS+SAM_NGPIOBIRQS+SAM_NGPIOCIRQS) +#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \ + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/include/sam34/sam3x_irq.h b/nuttx/arch/arm/include/sam34/sam3x_irq.h new file mode 100644 index 000000000..efe9fa2ac --- /dev/null +++ b/nuttx/arch/arm/include/sam34/sam3x_irq.h @@ -0,0 +1,429 @@ +/**************************************************************************************** + * arch/arm/include/sam34/sam3x_irq.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM3X_IRQ_H +#define __ARCH_ARM_INCLUDE_SAM34_SAM3X_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Definitions + ****************************************************************************************/ + +/* SAM3X Peripheral Identifiers */ + +#define SAM_PID_SUPC (0) /* Supply Controller */ +#define SAM_PID_RSTC (1) /* Reset Controller */ +#define SAM_PID_RTC (2) /* Real Time Clock */ +#define SAM_PID_RTT (3) /* Real Time Timer */ +#define SAM_PID_WDT (4) /* Watchdog Timer */ +#define SAM_PID_PMC (5) /* Power Management Controller */ +#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ +#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ +#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */ +#define SAM_PID_SMC (9) /* Static Memory Controller */ +#define SAM_PID_SDRAMC (10) /* Synchronous Dynamic RAM Controller */ +#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */ +#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */ +#define SAM_PID_PIOC (13) /* Parallel I/O Controller C */ +#define SAM_PID_PIOD (14) /* Parallel I/O Controller D */ +#define SAM_PID_PIOE (15) /* Parallel I/O Controller E */ +#define SAM_PID_PIOF (16) /* Parallel I/O Controller F */ +#define SAM_PID_USART0 (17) /* USART 0 */ +#define SAM_PID_USART1 (18) /* USART 1 */ +#define SAM_PID_USART2 (19) /* USART 2 */ +#define SAM_PID_USART3 (20) /* USART 3 */ +#define SAM_PID_HSMCI (21) /* High Speed Multimedia Card Interface */ +#define SAM_PID_TWI0 (22) /* Two-Wire Interface 0 */ +#define SAM_PID_TWI1 (23) /* Two-Wire Interface 1 */ +#define SAM_PID_SPI0 (24) /* Serial Peripheral Interface 0 */ +#define SAM_PID_SPI1 (25) /* Serial Peripheral Interface 2 */ +#define SAM_PID_SSC (26) /* Synchronous Serial Controller */ +#define SAM_PID_TC0 (27) /* Timer Counter 0 */ +#define SAM_PID_TC1 (28) /* Timer Counter 1 */ +#define SAM_PID_TC2 (29) /* Timer Counter 2 */ +#define SAM_PID_TC3 (30) /* Timer Counter 3 */ +#define SAM_PID_TC4 (31) /* Timer Counter 4 */ +#define SAM_PID_TC5 (32) /* Timer Counter 5 */ +#define SAM_PID_TC6 (33) /* Timer Counter 6 */ +#define SAM_PID_TC7 (34) /* Timer Counter 7 */ +#define SAM_PID_TC8 (35) /* Timer Counter 8 */ +#define SAM_PID_PWM (36) /* Pulse Width Modulation Controller */ +#define SAM_PID_ADC (37) /* ADC Controller */ +#define SAM_PID_DACC (38) /* DAC Controller */ +#define SAM_PID_DMAC (40) /* DMA Controller */ +#define SAM_PID_UOTGHS (40) /* USB OTG High Speed */ +#define SAM_PID_TRNG (41) /* True Random Number Generator */ +#define SAM_PID_EMAC (42) /* Ethernet MAC */ +#define SAM_PID_CAN0 (43) /* CAN Controller 0 */ +#define SAM_PID_CAN1 (44) /* CAN Controller 1 */ + +#define NR_PIDS (45) /* Number of peripheral identifiers */ + +/* External interrupts (vectors >= 16) */ + +#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */ +#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */ +#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */ +#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */ +#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */ +#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ +#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */ +#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */ +#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */ +#define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* Synchronous Dynamic RAM Controller */ +#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */ +#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */ +#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */ +#define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */ +#define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */ +#define SAM_IRQ_PIOF (SAM_IRQ_EXTINT+SAM_PID_PIOF) /* Parallel I/O Controller F */ +#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */ +#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */ +#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */ +#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* USART 3 */ +#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */ +#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */ +#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */ +#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface 0 */ +#define SAM_IRQ_SPI1 (SAM_IRQ_EXTINT+SAM_PID_SPI1) /* Serial Peripheral Interface 1 */ +#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */ +#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */ +#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */ +#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */ +#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* Timer Counter 3 */ +#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* Timer Counter 4 */ +#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* Timer Counter 5 */ +#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+SAM_PID_TC6) /* Timer Counter 6 */ +#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+SAM_PID_TC7) /* Timer Counter 7 */ +#define SAM_IRQ_TC8 (SAM_IRQ_EXTINT+SAM_PID_TC8) /* Timer Counter 8 */ +#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* Pulse Width Modulation Controller */ +#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* ADC Controller */ +#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* DAC Controller */ +#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMA Controller */ +#define SAM_IRQ_UOTGHS (SAM_IRQ_EXTINT+SAM_PID_UOTGHS) /* USB OTG High Speed */ +#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* True Random Number Generator */ +#define SAM_IRQ_EMAC (SAM_IRQ_EXTINT+SAM_PID_EMAC) /* Ethernet MAC */ +#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT+SAM_PID_CAN0) /* CAN Controller 0 */ +#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+SAM_PID_CAN1) /* CAN Controller 1 */ + +#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */ + +/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */ + +#ifdef CONFIG_GPIOA_IRQ +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT) +# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ +# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ +# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ +# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */ +# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */ +# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */ +# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */ +# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */ +# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */ +# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */ +# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */ +# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */ +# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */ +# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */ +# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */ +# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */ +# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */ +# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */ +# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */ +# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */ +# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */ +# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */ +# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */ +# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */ +# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */ +# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */ +# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */ +# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */ +# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */ +# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */ +# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */ +# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */ +# define SAM_NGPIOAIRQS 32 +#else +# define SAM_NGPIOAIRQS 0 +#endif + +#ifdef CONFIG_GPIOB_IRQ +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS) +# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ +# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ +# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ +# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */ +# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */ +# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */ +# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */ +# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */ +# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */ +# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */ +# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */ +# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */ +# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */ +# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */ +# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */ +# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */ +# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */ +# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */ +# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */ +# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */ +# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */ +# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */ +# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */ +# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */ +# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */ +# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */ +# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */ +# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */ +# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */ +# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ +# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ +# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ +# define SAM_NGPIOBIRQS 32 +#else +# define SAM_NGPIOBIRQS 0 +#endif + +#ifdef CONFIG_GPIOC_IRQ +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \ + SAM_NGPIOBIRQS) +# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ +# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ +# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ +# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */ +# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */ +# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */ +# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */ +# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */ +# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */ +# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */ +# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */ +# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */ +# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */ +# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */ +# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */ +# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */ +# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */ +# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */ +# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */ +# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */ +# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */ +# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */ +# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */ +# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */ +# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */ +# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */ +# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */ +# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */ +# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */ +# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ +# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ +# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ +# define SAM_NGPIOCIRQS 32 +#else +# define SAM_NGPIOCIRQS 0 +#endif + +#ifdef CONFIG_GPIOD_IRQ +# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \ + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS) +# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */ +# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */ +# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */ +# define SAM_IRQ_PD3 (SAM_IRQ_GPIOD_PINS+3) /* GPIOD, PIN 3 */ +# define SAM_IRQ_PD4 (SAM_IRQ_GPIOD_PINS+4) /* GPIOD, PIN 4 */ +# define SAM_IRQ_PD5 (SAM_IRQ_GPIOD_PINS+5) /* GPIOD, PIN 5 */ +# define SAM_IRQ_PD6 (SAM_IRQ_GPIOD_PINS+6) /* GPIOD, PIN 6 */ +# define SAM_IRQ_PD7 (SAM_IRQ_GPIOD_PINS+7) /* GPIOD, PIN 7 */ +# define SAM_IRQ_PD8 (SAM_IRQ_GPIOD_PINS+8) /* GPIOD, PIN 8 */ +# define SAM_IRQ_PD9 (SAM_IRQ_GPIOD_PINS+9) /* GPIOD, PIN 9 */ +# define SAM_IRQ_PD10 (SAM_IRQ_GPIOD_PINS+10) /* GPIOD, PIN 10 */ +# define SAM_IRQ_PD11 (SAM_IRQ_GPIOD_PINS+11) /* GPIOD, PIN 11 */ +# define SAM_IRQ_PD12 (SAM_IRQ_GPIOD_PINS+12) /* GPIOD, PIN 12 */ +# define SAM_IRQ_PD13 (SAM_IRQ_GPIOD_PINS+13) /* GPIOD, PIN 13 */ +# define SAM_IRQ_PD14 (SAM_IRQ_GPIOD_PINS+14) /* GPIOD, PIN 14 */ +# define SAM_IRQ_PD15 (SAM_IRQ_GPIOD_PINS+15) /* GPIOD, PIN 15 */ +# define SAM_IRQ_PD16 (SAM_IRQ_GPIOD_PINS+16) /* GPIOD, PIN 16 */ +# define SAM_IRQ_PD17 (SAM_IRQ_GPIOD_PINS+17) /* GPIOD, PIN 17 */ +# define SAM_IRQ_PD18 (SAM_IRQ_GPIOD_PINS+18) /* GPIOD, PIN 18 */ +# define SAM_IRQ_PD19 (SAM_IRQ_GPIOD_PINS+19) /* GPIOD, PIN 19 */ +# define SAM_IRQ_PD20 (SAM_IRQ_GPIOD_PINS+20) /* GPIOD, PIN 20 */ +# define SAM_IRQ_PD21 (SAM_IRQ_GPIOD_PINS+21) /* GPIOD, PIN 21 */ +# define SAM_IRQ_PD22 (SAM_IRQ_GPIOD_PINS+22) /* GPIOD, PIN 22 */ +# define SAM_IRQ_PD23 (SAM_IRQ_GPIOD_PINS+23) /* GPIOD, PIN 23 */ +# define SAM_IRQ_PD24 (SAM_IRQ_GPIOD_PINS+24) /* GPIOD, PIN 24 */ +# define SAM_IRQ_PD25 (SAM_IRQ_GPIOD_PINS+25) /* GPIOD, PIN 25 */ +# define SAM_IRQ_PD26 (SAM_IRQ_GPIOD_PINS+26) /* GPIOD, PIN 26 */ +# define SAM_IRQ_PD27 (SAM_IRQ_GPIOD_PINS+27) /* GPIOD, PIN 27 */ +# define SAM_IRQ_PD28 (SAM_IRQ_GPIOD_PINS+28) /* GPIOD, PIN 28 */ +# define SAM_IRQ_PD29 (SAM_IRQ_GPIOD_PINS+29) /* GPIOD, PIN 29 */ +# define SAM_IRQ_PD30 (SAM_IRQ_GPIOD_PINS+30) /* GPIOD, PIN 30 */ +# define SAM_IRQ_PD31 (SAM_IRQ_GPIOD_PINS+31) /* GPIOD, PIN 31 */ +# define SAM_NGPIODIRQS 32 +#else +# define SAM_NGPIODIRQS 0 +#endif + +#ifdef CONFIG_GPIOE_IRQ +# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \ + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + SAM_NGPIODIRQS) +# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */ +# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */ +# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */ +# define SAM_IRQ_PE3 (SAM_IRQ_GPIOE_PINS+3) /* GPIOE, PIN 3 */ +# define SAM_IRQ_PE4 (SAM_IRQ_GPIOE_PINS+4) /* GPIOE, PIN 4 */ +# define SAM_IRQ_PE5 (SAM_IRQ_GPIOE_PINS+5) /* GPIOE, PIN 5 */ +# define SAM_IRQ_PE6 (SAM_IRQ_GPIOE_PINS+6) /* GPIOE, PIN 6 */ +# define SAM_IRQ_PE7 (SAM_IRQ_GPIOE_PINS+7) /* GPIOE, PIN 7 */ +# define SAM_IRQ_PE8 (SAM_IRQ_GPIOE_PINS+8) /* GPIOE, PIN 8 */ +# define SAM_IRQ_PE9 (SAM_IRQ_GPIOE_PINS+9) /* GPIOE, PIN 9 */ +# define SAM_IRQ_PE10 (SAM_IRQ_GPIOE_PINS+10) /* GPIOE, PIN 10 */ +# define SAM_IRQ_PE11 (SAM_IRQ_GPIOE_PINS+11) /* GPIOE, PIN 11 */ +# define SAM_IRQ_PE12 (SAM_IRQ_GPIOE_PINS+12) /* GPIOE, PIN 12 */ +# define SAM_IRQ_PE13 (SAM_IRQ_GPIOE_PINS+13) /* GPIOE, PIN 13 */ +# define SAM_IRQ_PE14 (SAM_IRQ_GPIOE_PINS+14) /* GPIOE, PIN 14 */ +# define SAM_IRQ_PE15 (SAM_IRQ_GPIOE_PINS+15) /* GPIOE, PIN 15 */ +# define SAM_IRQ_PE16 (SAM_IRQ_GPIOE_PINS+16) /* GPIOE, PIN 16 */ +# define SAM_IRQ_PE17 (SAM_IRQ_GPIOE_PINS+17) /* GPIOE, PIN 17 */ +# define SAM_IRQ_PE18 (SAM_IRQ_GPIOE_PINS+18) /* GPIOE, PIN 18 */ +# define SAM_IRQ_PE19 (SAM_IRQ_GPIOE_PINS+19) /* GPIOE, PIN 19 */ +# define SAM_IRQ_PE20 (SAM_IRQ_GPIOE_PINS+20) /* GPIOE, PIN 20 */ +# define SAM_IRQ_PE21 (SAM_IRQ_GPIOE_PINS+21) /* GPIOE, PIN 21 */ +# define SAM_IRQ_PE22 (SAM_IRQ_GPIOE_PINS+22) /* GPIOE, PIN 22 */ +# define SAM_IRQ_PE23 (SAM_IRQ_GPIOE_PINS+23) /* GPIOE, PIN 23 */ +# define SAM_IRQ_PE24 (SAM_IRQ_GPIOE_PINS+24) /* GPIOE, PIN 24 */ +# define SAM_IRQ_PE25 (SAM_IRQ_GPIOE_PINS+25) /* GPIOE, PIN 25 */ +# define SAM_IRQ_PE26 (SAM_IRQ_GPIOE_PINS+26) /* GPIOE, PIN 26 */ +# define SAM_IRQ_PE27 (SAM_IRQ_GPIOE_PINS+27) /* GPIOE, PIN 27 */ +# define SAM_IRQ_PE28 (SAM_IRQ_GPIOE_PINS+28) /* GPIOE, PIN 28 */ +# define SAM_IRQ_PE29 (SAM_IRQ_GPIOE_PINS+29) /* GPIOE, PIN 29 */ +# define SAM_IRQ_PE30 (SAM_IRQ_GPIOE_PINS+30) /* GPIOE, PIN 30 */ +# define SAM_IRQ_PE31 (SAM_IRQ_GPIOE_PINS+31) /* GPIOE, PIN 31 */ +# define SAM_NGPIOEIRQS 32 +#else +# define SAM_NGPIOEIRQS 0 +#endif + +#ifdef CONFIG_GPIOF_IRQ +# define SAM_IRQ_GPIOF_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \ + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + SAM_NGPIODIRQS + \ + SAM_NGPIOEIRQS) +# define SAM_IRQ_PF0 (SAM_IRQ_GPIOF_PINS+0) /* GPIOF, PIN 0 */ +# define SAM_IRQ_PF1 (SAM_IRQ_GPIOF_PINS+1) /* GPIOF, PIN 1 */ +# define SAM_IRQ_PF2 (SAM_IRQ_GPIOF_PINS+2) /* GPIOF, PIN 2 */ +# define SAM_IRQ_PF3 (SAM_IRQ_GPIOF_PINS+3) /* GPIOF, PIN 3 */ +# define SAM_IRQ_PF4 (SAM_IRQ_GPIOF_PINS+4) /* GPIOF, PIN 4 */ +# define SAM_IRQ_PF5 (SAM_IRQ_GPIOF_PINS+5) /* GPIOF, PIN 5 */ +# define SAM_IRQ_PF6 (SAM_IRQ_GPIOF_PINS+6) /* GPIOF, PIN 6 */ +# define SAM_IRQ_PF7 (SAM_IRQ_GPIOF_PINS+7) /* GPIOF, PIN 7 */ +# define SAM_IRQ_PF8 (SAM_IRQ_GPIOF_PINS+8) /* GPIOF, PIN 8 */ +# define SAM_IRQ_PF9 (SAM_IRQ_GPIOF_PINS+9) /* GPIOF, PIN 9 */ +# define SAM_IRQ_PF10 (SAM_IRQ_GPIOF_PINS+10) /* GPIOF, PIN 10 */ +# define SAM_IRQ_PF11 (SAM_IRQ_GPIOF_PINS+11) /* GPIOF, PIN 11 */ +# define SAM_IRQ_PF12 (SAM_IRQ_GPIOF_PINS+12) /* GPIOF, PIN 12 */ +# define SAM_IRQ_PF13 (SAM_IRQ_GPIOF_PINS+13) /* GPIOF, PIN 13 */ +# define SAM_IRQ_PF14 (SAM_IRQ_GPIOF_PINS+14) /* GPIOF, PIN 14 */ +# define SAM_IRQ_PF15 (SAM_IRQ_GPIOF_PINS+15) /* GPIOF, PIN 15 */ +# define SAM_IRQ_PF16 (SAM_IRQ_GPIOF_PINS+16) /* GPIOF, PIN 16 */ +# define SAM_IRQ_PF17 (SAM_IRQ_GPIOF_PINS+17) /* GPIOF, PIN 17 */ +# define SAM_IRQ_PF18 (SAM_IRQ_GPIOF_PINS+18) /* GPIOF, PIN 18 */ +# define SAM_IRQ_PF19 (SAM_IRQ_GPIOF_PINS+19) /* GPIOF, PIN 19 */ +# define SAM_IRQ_PF20 (SAM_IRQ_GPIOF_PINS+20) /* GPIOF, PIN 20 */ +# define SAM_IRQ_PF21 (SAM_IRQ_GPIOF_PINS+21) /* GPIOF, PIN 21 */ +# define SAM_IRQ_PF22 (SAM_IRQ_GPIOF_PINS+22) /* GPIOF, PIN 22 */ +# define SAM_IRQ_PF23 (SAM_IRQ_GPIOF_PINS+23) /* GPIOF, PIN 23 */ +# define SAM_IRQ_PF24 (SAM_IRQ_GPIOF_PINS+24) /* GPIOF, PIN 24 */ +# define SAM_IRQ_PF25 (SAM_IRQ_GPIOF_PINS+25) /* GPIOF, PIN 25 */ +# define SAM_IRQ_PF26 (SAM_IRQ_GPIOF_PINS+26) /* GPIOF, PIN 26 */ +# define SAM_IRQ_PF27 (SAM_IRQ_GPIOF_PINS+27) /* GPIOF, PIN 27 */ +# define SAM_IRQ_PF28 (SAM_IRQ_GPIOF_PINS+28) /* GPIOF, PIN 28 */ +# define SAM_IRQ_PF29 (SAM_IRQ_GPIOF_PINS+29) /* GPIOF, PIN 29 */ +# define SAM_IRQ_PF30 (SAM_IRQ_GPIOF_PINS+30) /* GPIOF, PIN 30 */ +# define SAM_IRQ_PF31 (SAM_IRQ_GPIOF_PINS+31) /* GPIOF, PIN 31 */ +# define SAM_NGPIOFIRQS 32 +#else +# define SAM_NGPIOFIRQS 0 +#endif + +/* Total number of IRQ numbers */ + +#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \ + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \ + SAM_NGPIODIRQS + SAM_NGPIOEIRQS + SAM_NGPIOFIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Variables + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM3X_IRQ_H */ + diff --git a/nuttx/arch/arm/include/sam34/sam4l_irq.h b/nuttx/arch/arm/include/sam34/sam4l_irq.h index 061a5fe16..713ff4f61 100644 --- a/nuttx/arch/arm/include/sam34/sam4l_irq.h +++ b/nuttx/arch/arm/include/sam34/sam4l_irq.h @@ -66,7 +66,7 @@ #define SAM_PID_TWIS1_RHR (10) /* DIR=RX REGISTER: TWIS1 RHR */ #define SAM_PID_ADCIFE_LCV (11) /* DIR=RX REGISTER: ADCIFE LCV */ #define SAM_PID_CATB_RX (12) /* DIR=RX REGISTER: CATB Multiple */ - /* 13: Reserved */ + /* 13: Reserved */ #define SAM_PID_IISC0_RHR (14) /* DIR=RX REGISTER: IISC RHR (CH0) */ #define SAM_PID_IISC1_RHR (15) /* DIR=RX REGISTER: IISC RHR (CH1) */ #define SAM_PID_PARC_RHR (16) /* DIR=RX REGISTER: PARC RHR */ @@ -181,7 +181,7 @@ /* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */ #ifdef CONFIG_GPIOA_IRQ -# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) +# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT) # define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */ # define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */ # define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */ @@ -220,7 +220,7 @@ #endif #ifdef CONFIG_GPIOB_IRQ -# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS) # define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ # define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ # define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ @@ -253,13 +253,13 @@ # define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ # define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ # define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +# define SAM_NGPIOBIRQS 32 #else # define SAM_NGPIOBIRQS 0 #endif #ifdef CONFIG_GPIOC_IRQ -# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS+SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS) # define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ # define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ # define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ @@ -292,15 +292,15 @@ # define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ # define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ # define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +# define SAM_NGPIOCIRQS 32 #else # define SAM_NGPIOCIRQS 0 #endif /* Total number of IRQ numbers */ -#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+\ - SAM_NGPIOAIRQS+SAM_NGPIOBIRQS+SAM_NGPIOCIRQS) +#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \ + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS) /**************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/include/sam34/sam4s_irq.h b/nuttx/arch/arm/include/sam34/sam4s_irq.h index 9bef95f4d..8126075d9 100644 --- a/nuttx/arch/arm/include/sam34/sam4s_irq.h +++ b/nuttx/arch/arm/include/sam34/sam4s_irq.h @@ -170,7 +170,7 @@ #endif #ifdef CONFIG_GPIOB_IRQ -# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_IRQ_GPIOA_PINS) +# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS) # define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */ # define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */ # define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */ @@ -203,13 +203,13 @@ # define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */ # define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */ # define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +# define SAM_NGPIOBIRQS 32 #else # define SAM_NGPIOBIRQS 0 #endif #ifdef CONFIG_GPIOC_IRQ -# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_IRQ_GPIOA_PINS + SAM_IRQ_GPIOB_PINS) +# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS) # define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */ # define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */ # define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */ @@ -242,14 +242,14 @@ # define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */ # define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */ # define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */ -# define SAM_NGPIOAIRQS 32 +# define SAM_NGPIOCIRQS 32 #else # define SAM_NGPIOCIRQS 0 #endif /* Total number of IRQ numbers */ -#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT + \ +#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \ SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS) /**************************************************************************************** diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index 927a6619d..e295e01c0 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -15,7 +15,45 @@ config ARCH_CHIP_AT91SAM3U4E select ARCH_CORTEXM3 select ARCH_CHIP_SAM3U -config ARCH_CHIP_SAM34_NDMACHANC2C +config ARCH_CHIP_AT91SAM3X8E + bool "AT91SAMSAM3X8E" + select ARCH_CORTEXM3 + select ARCH_CHIP_SAM3X + select ARCH_HAVE_EXTNOR + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 + +config ARCH_CHIP_AT91SAM3X8C + bool "AT91SAM3X8C" + select ARCH_CORTEXM3 + select ARCH_CHIP_SAM3X + +config ARCH_CHIP_AT91SAM3X4E + bool "AT91SAM3X4E" + select ARCH_CORTEXM3 + select ARCH_CHIP_SAM3X + select ARCH_HAVE_EXTNOR + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 + +config ARCH_CHIP_AT91SAM3X4C + bool "AT91SAM3X4C" + select ARCH_CORTEXM3 + select ARCH_CHIP_SAM3X + +config ARCH_CHIP_AT91SAM3A8C + bool "AT91SAM3A8C" + select ARCH_CORTEXM3 + select ARCH_CHIP_SAM3A + +config ARCH_CHIP_AT91SAM3A4C + bool "AT91SAM3A4C" + select ARCH_CORTEXM3 + select ARCH_CHIP_SAM3A + +config ARCH_CHIP_ATSAM4LC2C bool "ATSAM4LC2C" select ARCH_CORTEXM4 select ARCH_CHIP_SAM4L @@ -135,6 +173,14 @@ config ARCH_CHIP_SAM3U select ARCH_HAVE_EXTSRAM0 select ARCH_HAVE_EXTSRAM1 +config ARCH_CHIP_SAM3X + bool + default n + +config ARCH_CHIP_SAM3A + bool + default n + config ARCH_CHIP_SAM4L bool default n diff --git a/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h b/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h index ace4bb186..891a4c104 100644 --- a/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h +++ b/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h @@ -86,7 +86,6 @@ * 2Hz, then a fatal error has been detected and the system has halted. */ - #define GPIO_D9 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ GPIO_PORT_PIOC | GPIO_PIN10) #define GPIO_D10 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ |